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adac54ffc5
Add support for MTE to strcmp. Regression tested with xcheck and benchmarked with glibc's benchtests on the Cortex-A53, Cortex-A72, and Neoverse N1. The existing implementation assumes that any access to the pages in which the string resides is safe. This assumption is not true when MTE is enabled. This patch updates the algorithm to ensure that accesses remain within the bounds of an MTE tag (16-byte chunks) and improves overall performance. Co-authored-by: Branislav Rankov <branislav.rankov@arm.com> Co-authored-by: Wilco Dijkstra <wilco.dijkstra@arm.com>
201 lines
4.7 KiB
ArmAsm
201 lines
4.7 KiB
ArmAsm
/* Copyright (C) 2012-2020 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<https://www.gnu.org/licenses/>. */
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/* Assumptions:
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*
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* ARMv8-a, AArch64.
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* MTE compatible.
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*/
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#include <sysdep.h>
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#define REP8_01 0x0101010101010101
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#define REP8_7f 0x7f7f7f7f7f7f7f7f
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/* Parameters and result. */
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#define src1 x0
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#define src2 x1
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#define result x0
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/* Internal variables. */
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#define data1 x2
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#define data1w w2
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#define data2 x3
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#define data2w w3
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#define has_nul x4
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#define diff x5
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#define off1 x5
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#define syndrome x6
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#define tmp x6
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#define data3 x7
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#define zeroones x8
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#define shift x9
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#define off2 x10
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/* On big-endian early bytes are at MSB and on little-endian LSB.
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LS_FW means shifting towards early bytes. */
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#ifdef __AARCH64EB__
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# define LS_FW lsl
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#else
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# define LS_FW lsr
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#endif
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/* NUL detection works on the principle that (X - 1) & (~X) & 0x80
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(=> (X - 1) & ~(X | 0x7f)) is non-zero iff a byte is zero, and
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can be done in parallel across the entire word.
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Since carry propagation makes 0x1 bytes before a NUL byte appear
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NUL too in big-endian, byte-reverse the data before the NUL check. */
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ENTRY(strcmp)
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DELOUSE (0)
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DELOUSE (1)
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sub off2, src2, src1
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mov zeroones, REP8_01
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and tmp, src1, 7
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tst off2, 7
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b.ne L(misaligned8)
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cbnz tmp, L(mutual_align)
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.p2align 4
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L(loop_aligned):
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ldr data2, [src1, off2]
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ldr data1, [src1], 8
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L(start_realigned):
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#ifdef __AARCH64EB__
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rev tmp, data1
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sub has_nul, tmp, zeroones
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orr tmp, tmp, REP8_7f
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#else
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sub has_nul, data1, zeroones
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orr tmp, data1, REP8_7f
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#endif
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bics has_nul, has_nul, tmp /* Non-zero if NUL terminator. */
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ccmp data1, data2, 0, eq
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b.eq L(loop_aligned)
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#ifdef __AARCH64EB__
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rev has_nul, has_nul
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#endif
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eor diff, data1, data2
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orr syndrome, diff, has_nul
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L(end):
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#ifndef __AARCH64EB__
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rev syndrome, syndrome
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rev data1, data1
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rev data2, data2
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#endif
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clz shift, syndrome
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/* The most-significant-non-zero bit of the syndrome marks either the
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first bit that is different, or the top bit of the first zero byte.
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Shifting left now will bring the critical information into the
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top bits. */
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lsl data1, data1, shift
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lsl data2, data2, shift
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/* But we need to zero-extend (char is unsigned) the value and then
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perform a signed 32-bit subtraction. */
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lsr data1, data1, 56
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sub result, data1, data2, lsr 56
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ret
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.p2align 4
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L(mutual_align):
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/* Sources are mutually aligned, but are not currently at an
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alignment boundary. Round down the addresses and then mask off
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the bytes that precede the start point. */
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bic src1, src1, 7
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ldr data2, [src1, off2]
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ldr data1, [src1], 8
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neg shift, src2, lsl 3 /* Bits to alignment -64. */
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mov tmp, -1
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LS_FW tmp, tmp, shift
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orr data1, data1, tmp
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orr data2, data2, tmp
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b L(start_realigned)
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L(misaligned8):
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/* Align SRC1 to 8 bytes and then compare 8 bytes at a time, always
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checking to make sure that we don't access beyond the end of SRC2. */
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cbz tmp, L(src1_aligned)
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L(do_misaligned):
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ldrb data1w, [src1], 1
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ldrb data2w, [src2], 1
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cmp data1w, 0
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ccmp data1w, data2w, 0, ne /* NZCV = 0b0000. */
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b.ne L(done)
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tst src1, 7
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b.ne L(do_misaligned)
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L(src1_aligned):
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neg shift, src2, lsl 3
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bic src2, src2, 7
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ldr data3, [src2], 8
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#ifdef __AARCH64EB__
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rev data3, data3
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#endif
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lsr tmp, zeroones, shift
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orr data3, data3, tmp
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sub has_nul, data3, zeroones
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orr tmp, data3, REP8_7f
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bics has_nul, has_nul, tmp
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b.ne L(tail)
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sub off1, src2, src1
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.p2align 4
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L(loop_unaligned):
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ldr data3, [src1, off1]
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ldr data2, [src1, off2]
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#ifdef __AARCH64EB__
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rev data3, data3
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#endif
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sub has_nul, data3, zeroones
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orr tmp, data3, REP8_7f
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ldr data1, [src1], 8
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bics has_nul, has_nul, tmp
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ccmp data1, data2, 0, eq
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b.eq L(loop_unaligned)
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lsl tmp, has_nul, shift
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#ifdef __AARCH64EB__
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rev tmp, tmp
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#endif
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eor diff, data1, data2
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orr syndrome, diff, tmp
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cbnz syndrome, L(end)
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L(tail):
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ldr data1, [src1]
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neg shift, shift
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lsr data2, data3, shift
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lsr has_nul, has_nul, shift
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#ifdef __AARCH64EB__
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rev data2, data2
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rev has_nul, has_nul
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#endif
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eor diff, data1, data2
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orr syndrome, diff, has_nul
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b L(end)
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L(done):
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sub result, data1, data2
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ret
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END(strcmp)
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libc_hidden_builtin_def (strcmp)
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