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Revision 3.50 of the MIPS architecture defined FCSR ABS2008 and NAN2008
bits as optionally read/write [1][2]. No hardware implementation has
ever made use of this feature though. For example the first processor
to implement these bits, the MIPS32r3 proAptiv core, has both bits
read-only, hardwired to 1 [3]. And as from revision 5.03 of the MIPS
architecture the bits are required to be read-only, preset by hardware
[4][5]. Additionally all hardware implementations in existence have the
bits hardwired both to the same value, either of `0' and `1'.
These bits may still be read/write or hardwired to opposite values in
simulated hardware implementations such as QEMU or the FPU emulator
included with the Linux kernel. However to match real hardware
implementations the Linux kernel will set FCSR ABS2008 and NAN2008 bits
both to the same value where possible, reflecting the setting of the
EF_MIPS_NAN2008 ELF file header bit.
Therefore update the bit patterns in macro definitions we use for the
control word, in the 2008-NaN encoding mode, so that both bits have the
same value in a given bit pattern. Additionally mark the FCSR ABS2008
bit as reserved, so that high-level calls to change the control word do
not affect the bit.
This covers the regular FPU configurations, only leaving exotic corner
cases with the value of FCSR control word initially set by the kernel
different to what our code thinks it is. To address the remaining cases
the AT_FPUCW auxiliary vector entry would have to be implemented in the
Linux kernel, which currently is not.
References:
[1] "MIPS Architecture For Programmers, Volume I-A: Introduction to the
MIPS32 Architecture", MIPS Technologies, Inc., Document Number:
MD00082, Revision 3.50, September 20, 2012, Table 5.5 "FCSR Register
Field Descriptions", p. 80
[2] "MIPS Architecture For Programmers, Volume I-A: Introduction to the
MIPS64 Architecture", MIPS Technologies, Inc., Document Number:
MD00083, Revision 3.50, September 20, 2012, Table 5.5 "FCSR Register
Field Descriptions", p. 82
[3] "MIPS32 proAptiv Multiprocessing System Software User's Manual",
MIPS Technologies, Inc., Document Number: MD00878, Revision 01.22,
May 14, 2013, Table 12.10 "FCSR Bit Field Descriptions", p. 570
[4] "MIPS Architecture For Programmers, Volume I-A: Introduction to the
MIPS32 Architecture", MIPS Technologies, Inc., Document Number:
MD00082, Revision 5.03, Sept. 9, 2013, Table 5.7 "FCSR Register
Field Descriptions", p. 82
[5] "MIPS Architecture For Programmers, Volume I-A: Introduction to the
MIPS64 Architecture", MIPS Technologies, Inc., Document Number:
MD00083, Revision 5.03, Sept. 9, 2013, Table 5.7 "FCSR Register
Field Descriptions", p. 84
* sysdeps/mips/fpu_control.h (_FPU_RESERVED): Include ABS2008.
(_FPU_DEFAULT, _FPU_IEEE) [__mips_nan2008]: Set ABS2008.
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| .. | ||
| bits | ||
| fpu | ||
| ieee754 | ||
| include/sys | ||
| mips32 | ||
| mips64 | ||
| nptl | ||
| sys | ||
| __longjmp.c | ||
| abort-instr.h | ||
| add_n.S | ||
| addmul_1.S | ||
| atomic-machine.h | ||
| backtrace.c | ||
| bsd-_setjmp.S | ||
| bsd-setjmp.S | ||
| configure | ||
| configure.ac | ||
| dl-dtprocnum.h | ||
| dl-machine-reject-phdr.h | ||
| dl-machine.h | ||
| dl-procinfo.c | ||
| dl-procinfo.h | ||
| dl-tls.h | ||
| dl-trampoline.c | ||
| fpregdef.h | ||
| fpu_control.h | ||
| gccframe.h | ||
| Implies | ||
| jmpbuf-unwind.h | ||
| ldsodefs.h | ||
| libc-tls.c | ||
| linkmap.h | ||
| lshift.S | ||
| machine-gmon.h | ||
| Makefile | ||
| math_private.h | ||
| math-tests.h | ||
| memcpy.S | ||
| memset.S | ||
| memusage.h | ||
| mul_1.S | ||
| preconfigure | ||
| regdef.h | ||
| rshift.S | ||
| setjmp_aux.c | ||
| setjmp.S | ||
| sgidefs.h | ||
| sotruss-lib.c | ||
| stackinfo.h | ||
| start.S | ||
| strcmp.S | ||
| sub_n.S | ||
| submul_1.S | ||
| tininess.h | ||
| tls-macros.h | ||
| tst-abi-fp32mod.c | ||
| tst-abi-fp64amod.c | ||
| tst-abi-fp64mod.c | ||
| tst-abi-fpxxmod.c | ||
| tst-abi-fpxxomod.c | ||
| tst-abi-interlink.c | ||
| tst-audit.h | ||
| tst-mode-switch-1.c | ||
| tst-mode-switch-2.c | ||
| tst-mode-switch-3.c | ||