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POWER ISA 3.0 introduces the xssqrtqp instructions, which expects operands to be in Vector Registers (Altivec/VMX), even though this instruction belongs to the Vector-Scalar Instruction Set. In GCC's Extended Assembly for POWER, the 'wq' register constraint is provided for use with IEEE 754 128-bit floating-point values. However, this constraint does not limit the register allocation to Vector Registers (Altivec/VMX) and could assign a Vector-Scalar Register (VSX) to the operands of the instruction. This patch changes the register constraint used in sqrtf128 from 'wq' to 'v', in order to request a Vector Register (Altivec/VMX) for use with the xssqrtqp instruction. Tested for powerpc64le and --with-cpu=power9. [BZ #21941] * sysdeps/powerpc/fpu/math_private.h (__ieee754_sqrtf128): Since xssqrtqp requires operands to be in Vector Registers (Altivec/VMX), replace the register constraint 'wq' with 'v'. * sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c (__ieee754_sqrtf128): Likewise. |
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| multiarch | ||
| power7 | ||
| power8 | ||
| power9 | ||
| configure | ||
| configure.ac | ||
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