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This patch optimizes the performance of memset for A64FX [1] which implements ARMv8-A SVE and has L1 64KB cache per core and L2 8MB cache per NUMA node. The performance optimization makes use of Scalable Vector Register with several techniques such as loop unrolling, memory access alignment, cache zero fill and prefetch. SVE assembler code for memset is implemented as Vector Length Agnostic code so theoretically it can be run on any SOC which supports ARMv8-A SVE standard. We confirmed that all testcases have been passed by running 'make check' and 'make xcheck' not only on A64FX but also on ThunderX2. And also we confirmed that the SVE 512 bit vector register performance is roughly 4 times better than Advanced SIMD 128 bit register and 8 times better than scalar 64 bit register by running 'make bench'. [1] https://github.com/fujitsu/A64FX Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com> Reviewed-by: Szabolcs Nagy <Szabolcs.Nagy@arm.com> |
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| .. | ||
| ifunc-impl-list.c | ||
| init-arch.h | ||
| Makefile | ||
| memchr_generic.S | ||
| memchr_nosimd.S | ||
| memchr.c | ||
| memcpy_a64fx.S | ||
| memcpy_advsimd.S | ||
| memcpy_falkor.S | ||
| memcpy_generic.S | ||
| memcpy_thunderx2.S | ||
| memcpy_thunderx.S | ||
| memcpy.c | ||
| memmove.c | ||
| memset_a64fx.S | ||
| memset_base64.S | ||
| memset_emag.S | ||
| memset_falkor.S | ||
| memset_generic.S | ||
| memset_kunpeng.S | ||
| memset.c | ||
| rtld-memset.S | ||
| strlen_asimd.S | ||
| strlen_mte.S | ||
| strlen.c | ||