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vulkan-sdk-1.3.280
glslang/Test/baseResults/spv.subgroupShuffle.comp.out

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SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
spv.subgroupShuffle.comp
// Module Version 10300
Update CHANGES for release 11.12.0
2022-10-13 00:16:41 +00:00
// Generated by (magic number): 8000b
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
// Id's are bound by 420
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Capability Shader
Capability Float64
Capability GroupNonUniform
Capability GroupNonUniformShuffle
1: ExtInstImport "GLSL.std.450"
MemoryModel Logical GLSL450
EntryPoint GLCompute 4 "main" 10 12
ExecutionMode 4 LocalSize 8 8 1
Source GLSL 450
SourceExtension "GL_KHR_shader_subgroup_basic"
SourceExtension "GL_KHR_shader_subgroup_shuffle"
Name 4 "main"
Name 8 "invocation"
Name 10 "gl_SubgroupInvocationID"
Name 12 "gl_SubgroupSize"
Name 24 "Buffers"
MemberName 24(Buffers) 0 "f4"
MemberName 24(Buffers) 1 "i4"
MemberName 24(Buffers) 2 "u4"
MemberName 24(Buffers) 3 "d4"
Name 27 "data"
Decorate 10(gl_SubgroupInvocationID) RelaxedPrecision
Decorate 10(gl_SubgroupInvocationID) BuiltIn SubgroupLocalInvocationId
Decorate 11 RelaxedPrecision
Decorate 12(gl_SubgroupSize) RelaxedPrecision
Decorate 12(gl_SubgroupSize) BuiltIn SubgroupSize
Decorate 13 RelaxedPrecision
Decorate 14 RelaxedPrecision
Decorate 16 RelaxedPrecision
MemberDecorate 24(Buffers) 0 Offset 0
MemberDecorate 24(Buffers) 1 Offset 16
MemberDecorate 24(Buffers) 2 Offset 32
MemberDecorate 24(Buffers) 3 Offset 64
Fix 8-bit storage nearly always using the UniformAndStorageBuffer8BitAccess capability. When using the 8-bit storage extension it basically always used the `UniformAndStorageBuffer8BitAccess` capability, even in cases where it wasn't required. For instance if we are targeting Vulkan 1.1 (SPIR-V 1.3 or higher), and we are only using 8-bit types in an SSBO, we only need the `StorageBuffer8BitAccess` capability. I fixed this by enabling storage buffer use in Vulkan 1.1 / SPIR-V 1.3 or higher, and then changing the logic to match. I also added some tests that will output different capabilities when run on Vulkan 1.0 and 1.1, thus they are added twice to the test list (one for each version). Fixes #1539
2018-10-23 14:02:29 +00:00
Decorate 24(Buffers) Block
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Decorate 27(data) DescriptorSet 0
Decorate 27(data) Binding 0
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
Decorate 419 BuiltIn WorkgroupSize
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
2: TypeVoid
3: TypeFunction 2
6: TypeInt 32 0
7: TypePointer Function 6(int)
9: TypePointer Input 6(int)
10(gl_SubgroupInvocationID): 9(ptr) Variable Input
12(gl_SubgroupSize): 9(ptr) Variable Input
15: 6(int) Constant 4
17: TypeFloat 32
18: TypeVector 17(float) 4
19: TypeInt 32 1
20: TypeVector 19(int) 4
21: TypeVector 6(int) 4
22: TypeFloat 64
Add bit width of types to disassembleInstruction
2018-05-23 04:13:30 +00:00
23: TypeVector 22(float64_t) 4
24(Buffers): TypeStruct 18(fvec4) 20(ivec4) 21(ivec4) 23(f64vec4)
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
25: TypeArray 24(Buffers) 15
Fix 8-bit storage nearly always using the UniformAndStorageBuffer8BitAccess capability. When using the 8-bit storage extension it basically always used the `UniformAndStorageBuffer8BitAccess` capability, even in cases where it wasn't required. For instance if we are targeting Vulkan 1.1 (SPIR-V 1.3 or higher), and we are only using 8-bit types in an SSBO, we only need the `StorageBuffer8BitAccess` capability. I fixed this by enabling storage buffer use in Vulkan 1.1 / SPIR-V 1.3 or higher, and then changing the logic to match. I also added some tests that will output different capabilities when run on Vulkan 1.0 and 1.1, thus they are added twice to the test list (one for each version). Fixes #1539
2018-10-23 14:02:29 +00:00
26: TypePointer StorageBuffer 25
27(data): 26(ptr) Variable StorageBuffer
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
29: 19(int) Constant 0
30: 6(int) Constant 0
Fix 8-bit storage nearly always using the UniformAndStorageBuffer8BitAccess capability. When using the 8-bit storage extension it basically always used the `UniformAndStorageBuffer8BitAccess` capability, even in cases where it wasn't required. For instance if we are targeting Vulkan 1.1 (SPIR-V 1.3 or higher), and we are only using 8-bit types in an SSBO, we only need the `StorageBuffer8BitAccess` capability. I fixed this by enabling storage buffer use in Vulkan 1.1 / SPIR-V 1.3 or higher, and then changing the logic to match. I also added some tests that will output different capabilities when run on Vulkan 1.0 and 1.1, thus they are added twice to the test list (one for each version). Fixes #1539
2018-10-23 14:02:29 +00:00
31: TypePointer StorageBuffer 17(float)
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
35: 6(int) Constant 3
39: 19(int) Constant 1
40: TypeVector 17(float) 2
Fix 8-bit storage nearly always using the UniformAndStorageBuffer8BitAccess capability. When using the 8-bit storage extension it basically always used the `UniformAndStorageBuffer8BitAccess` capability, even in cases where it wasn't required. For instance if we are targeting Vulkan 1.1 (SPIR-V 1.3 or higher), and we are only using 8-bit types in an SSBO, we only need the `StorageBuffer8BitAccess` capability. I fixed this by enabling storage buffer use in Vulkan 1.1 / SPIR-V 1.3 or higher, and then changing the logic to match. I also added some tests that will output different capabilities when run on Vulkan 1.0 and 1.1, thus they are added twice to the test list (one for each version). Fixes #1539
2018-10-23 14:02:29 +00:00
41: TypePointer StorageBuffer 18(fvec4)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
49: 6(int) Constant 1
53: 19(int) Constant 2
54: TypeVector 17(float) 3
64: 6(int) Constant 2
68: 19(int) Constant 3
75: TypePointer StorageBuffer 19(int)
82: TypeVector 19(int) 2
83: TypePointer StorageBuffer 20(ivec4)
94: TypeVector 19(int) 3
113: TypePointer StorageBuffer 6(int)
120: TypeVector 6(int) 2
121: TypePointer StorageBuffer 21(ivec4)
132: TypeVector 6(int) 3
151: TypePointer StorageBuffer 22(float64_t)
158: TypeVector 22(float64_t) 2
159: TypePointer StorageBuffer 23(f64vec4)
170: TypeVector 22(float64_t) 3
191: TypeBool
201: 82(ivec2) ConstantComposite 29 29
202: TypeVector 191(bool) 2
206: 82(ivec2) ConstantComposite 39 39
216: 94(ivec3) ConstantComposite 29 29 29
217: TypeVector 191(bool) 3
221: 94(ivec3) ConstantComposite 39 39 39
232: 20(ivec4) ConstantComposite 29 29 29 29
233: TypeVector 191(bool) 4
237: 20(ivec4) ConstantComposite 39 39 39 39
418: 6(int) Constant 8
419: 132(ivec3) ConstantComposite 418 418 49
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
4(main): 2 Function None 3
5: Label
8(invocation): 7(ptr) Variable Function
11: 6(int) Load 10(gl_SubgroupInvocationID)
13: 6(int) Load 12(gl_SubgroupSize)
14: 6(int) IAdd 11 13
16: 6(int) UMod 14 15
Store 8(invocation) 16
28: 6(int) Load 8(invocation)
32: 31(ptr) AccessChain 27(data) 29 29 30
33: 17(float) Load 32
34: 6(int) Load 8(invocation)
36: 17(float) GroupNonUniformShuffle 35 33 34
37: 31(ptr) AccessChain 27(data) 28 29 30
Store 37 36
38: 6(int) Load 8(invocation)
42: 41(ptr) AccessChain 27(data) 39 29
43: 18(fvec4) Load 42
44: 40(fvec2) VectorShuffle 43 43 0 1
45: 6(int) Load 8(invocation)
46: 40(fvec2) GroupNonUniformShuffle 35 44 45
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
47: 31(ptr) AccessChain 27(data) 38 29 30
48: 17(float) CompositeExtract 46 0
Store 47 48
50: 31(ptr) AccessChain 27(data) 38 29 49
51: 17(float) CompositeExtract 46 1
Store 50 51
52: 6(int) Load 8(invocation)
55: 41(ptr) AccessChain 27(data) 53 29
56: 18(fvec4) Load 55
57: 54(fvec3) VectorShuffle 56 56 0 1 2
58: 6(int) Load 8(invocation)
59: 54(fvec3) GroupNonUniformShuffle 35 57 58
60: 31(ptr) AccessChain 27(data) 52 29 30
61: 17(float) CompositeExtract 59 0
Store 60 61
62: 31(ptr) AccessChain 27(data) 52 29 49
63: 17(float) CompositeExtract 59 1
Store 62 63
65: 31(ptr) AccessChain 27(data) 52 29 64
66: 17(float) CompositeExtract 59 2
Store 65 66
67: 6(int) Load 8(invocation)
69: 41(ptr) AccessChain 27(data) 68 29
70: 18(fvec4) Load 69
71: 6(int) Load 8(invocation)
72: 18(fvec4) GroupNonUniformShuffle 35 70 71
73: 41(ptr) AccessChain 27(data) 67 29
Store 73 72
74: 6(int) Load 8(invocation)
76: 75(ptr) AccessChain 27(data) 29 39 30
77: 19(int) Load 76
78: 6(int) Load 8(invocation)
79: 19(int) GroupNonUniformShuffle 35 77 78
80: 75(ptr) AccessChain 27(data) 74 39 30
Store 80 79
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
81: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
84: 83(ptr) AccessChain 27(data) 39 39
85: 20(ivec4) Load 84
86: 82(ivec2) VectorShuffle 85 85 0 1
87: 6(int) Load 8(invocation)
88: 82(ivec2) GroupNonUniformShuffle 35 86 87
89: 75(ptr) AccessChain 27(data) 81 39 30
90: 19(int) CompositeExtract 88 0
Store 89 90
91: 75(ptr) AccessChain 27(data) 81 39 49
92: 19(int) CompositeExtract 88 1
Store 91 92
93: 6(int) Load 8(invocation)
95: 83(ptr) AccessChain 27(data) 53 39
96: 20(ivec4) Load 95
97: 94(ivec3) VectorShuffle 96 96 0 1 2
98: 6(int) Load 8(invocation)
99: 94(ivec3) GroupNonUniformShuffle 35 97 98
100: 75(ptr) AccessChain 27(data) 93 39 30
101: 19(int) CompositeExtract 99 0
Store 100 101
102: 75(ptr) AccessChain 27(data) 93 39 49
103: 19(int) CompositeExtract 99 1
Store 102 103
104: 75(ptr) AccessChain 27(data) 93 39 64
105: 19(int) CompositeExtract 99 2
Store 104 105
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
106: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
107: 83(ptr) AccessChain 27(data) 68 39
108: 20(ivec4) Load 107
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
109: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
110: 20(ivec4) GroupNonUniformShuffle 35 108 109
111: 83(ptr) AccessChain 27(data) 106 39
Store 111 110
112: 6(int) Load 8(invocation)
114: 113(ptr) AccessChain 27(data) 29 53 30
115: 6(int) Load 114
116: 6(int) Load 8(invocation)
117: 6(int) GroupNonUniformShuffle 35 115 116
118: 113(ptr) AccessChain 27(data) 112 53 30
Store 118 117
119: 6(int) Load 8(invocation)
122: 121(ptr) AccessChain 27(data) 39 53
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
123: 21(ivec4) Load 122
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
124: 120(ivec2) VectorShuffle 123 123 0 1
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
125: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
126: 120(ivec2) GroupNonUniformShuffle 35 124 125
127: 113(ptr) AccessChain 27(data) 119 53 30
128: 6(int) CompositeExtract 126 0
Store 127 128
129: 113(ptr) AccessChain 27(data) 119 53 49
130: 6(int) CompositeExtract 126 1
Store 129 130
131: 6(int) Load 8(invocation)
133: 121(ptr) AccessChain 27(data) 53 53
134: 21(ivec4) Load 133
135: 132(ivec3) VectorShuffle 134 134 0 1 2
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
136: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
137: 132(ivec3) GroupNonUniformShuffle 35 135 136
138: 113(ptr) AccessChain 27(data) 131 53 30
139: 6(int) CompositeExtract 137 0
Store 138 139
140: 113(ptr) AccessChain 27(data) 131 53 49
141: 6(int) CompositeExtract 137 1
Store 140 141
142: 113(ptr) AccessChain 27(data) 131 53 64
143: 6(int) CompositeExtract 137 2
Store 142 143
144: 6(int) Load 8(invocation)
145: 121(ptr) AccessChain 27(data) 68 53
146: 21(ivec4) Load 145
147: 6(int) Load 8(invocation)
148: 21(ivec4) GroupNonUniformShuffle 35 146 147
149: 121(ptr) AccessChain 27(data) 144 53
Store 149 148
150: 6(int) Load 8(invocation)
152: 151(ptr) AccessChain 27(data) 29 68 30
153:22(float64_t) Load 152
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
154: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
155:22(float64_t) GroupNonUniformShuffle 35 153 154
156: 151(ptr) AccessChain 27(data) 150 68 30
Store 156 155
157: 6(int) Load 8(invocation)
160: 159(ptr) AccessChain 27(data) 39 68
161: 23(f64vec4) Load 160
162:158(f64vec2) VectorShuffle 161 161 0 1
163: 6(int) Load 8(invocation)
164:158(f64vec2) GroupNonUniformShuffle 35 162 163
165: 151(ptr) AccessChain 27(data) 157 68 30
166:22(float64_t) CompositeExtract 164 0
Store 165 166
167: 151(ptr) AccessChain 27(data) 157 68 49
168:22(float64_t) CompositeExtract 164 1
Store 167 168
169: 6(int) Load 8(invocation)
171: 159(ptr) AccessChain 27(data) 53 68
172: 23(f64vec4) Load 171
173:170(f64vec3) VectorShuffle 172 172 0 1 2
174: 6(int) Load 8(invocation)
175:170(f64vec3) GroupNonUniformShuffle 35 173 174
176: 151(ptr) AccessChain 27(data) 169 68 30
177:22(float64_t) CompositeExtract 175 0
Store 176 177
178: 151(ptr) AccessChain 27(data) 169 68 49
179:22(float64_t) CompositeExtract 175 1
Store 178 179
180: 151(ptr) AccessChain 27(data) 169 68 64
181:22(float64_t) CompositeExtract 175 2
Store 180 181
182: 6(int) Load 8(invocation)
183: 159(ptr) AccessChain 27(data) 68 68
184: 23(f64vec4) Load 183
185: 6(int) Load 8(invocation)
186: 23(f64vec4) GroupNonUniformShuffle 35 184 185
187: 159(ptr) AccessChain 27(data) 182 68
Store 187 186
188: 6(int) Load 8(invocation)
189: 75(ptr) AccessChain 27(data) 29 39 30
190: 19(int) Load 189
192: 191(bool) SLessThan 190 29
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
193: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
194: 191(bool) GroupNonUniformShuffle 35 192 193
195: 19(int) Select 194 39 29
196: 75(ptr) AccessChain 27(data) 188 39 30
Store 196 195
197: 6(int) Load 8(invocation)
198: 83(ptr) AccessChain 27(data) 39 39
199: 20(ivec4) Load 198
200: 82(ivec2) VectorShuffle 199 199 0 1
203: 202(bvec2) SLessThan 200 201
204: 6(int) Load 8(invocation)
205: 202(bvec2) GroupNonUniformShuffle 35 203 204
207: 82(ivec2) Select 205 206 201
208: 75(ptr) AccessChain 27(data) 197 39 30
209: 19(int) CompositeExtract 207 0
Store 208 209
210: 75(ptr) AccessChain 27(data) 197 39 49
211: 19(int) CompositeExtract 207 1
Store 210 211
212: 6(int) Load 8(invocation)
213: 83(ptr) AccessChain 27(data) 39 39
214: 20(ivec4) Load 213
215: 94(ivec3) VectorShuffle 214 214 0 1 2
218: 217(bvec3) SLessThan 215 216
219: 6(int) Load 8(invocation)
220: 217(bvec3) GroupNonUniformShuffle 35 218 219
222: 94(ivec3) Select 220 221 216
223: 75(ptr) AccessChain 27(data) 212 39 30
224: 19(int) CompositeExtract 222 0
Store 223 224
225: 75(ptr) AccessChain 27(data) 212 39 49
226: 19(int) CompositeExtract 222 1
Store 225 226
227: 75(ptr) AccessChain 27(data) 212 39 64
228: 19(int) CompositeExtract 222 2
Store 227 228
229: 6(int) Load 8(invocation)
230: 83(ptr) AccessChain 27(data) 39 39
231: 20(ivec4) Load 230
234: 233(bvec4) SLessThan 231 232
235: 6(int) Load 8(invocation)
236: 233(bvec4) GroupNonUniformShuffle 35 234 235
238: 20(ivec4) Select 236 237 232
239: 83(ptr) AccessChain 27(data) 229 39
Store 239 238
240: 6(int) Load 8(invocation)
241: 31(ptr) AccessChain 27(data) 29 29 30
242: 17(float) Load 241
243: 6(int) Load 8(invocation)
244: 17(float) GroupNonUniformShuffleXor 35 242 243
245: 31(ptr) AccessChain 27(data) 240 29 30
Store 245 244
246: 6(int) Load 8(invocation)
247: 41(ptr) AccessChain 27(data) 39 29
248: 18(fvec4) Load 247
249: 40(fvec2) VectorShuffle 248 248 0 1
250: 6(int) Load 8(invocation)
251: 40(fvec2) GroupNonUniformShuffleXor 35 249 250
252: 31(ptr) AccessChain 27(data) 246 29 30
253: 17(float) CompositeExtract 251 0
Store 252 253
254: 31(ptr) AccessChain 27(data) 246 29 49
255: 17(float) CompositeExtract 251 1
Store 254 255
256: 6(int) Load 8(invocation)
257: 41(ptr) AccessChain 27(data) 53 29
258: 18(fvec4) Load 257
259: 54(fvec3) VectorShuffle 258 258 0 1 2
260: 6(int) Load 8(invocation)
261: 54(fvec3) GroupNonUniformShuffleXor 35 259 260
262: 31(ptr) AccessChain 27(data) 256 29 30
263: 17(float) CompositeExtract 261 0
Store 262 263
264: 31(ptr) AccessChain 27(data) 256 29 49
265: 17(float) CompositeExtract 261 1
Store 264 265
266: 31(ptr) AccessChain 27(data) 256 29 64
267: 17(float) CompositeExtract 261 2
Store 266 267
268: 6(int) Load 8(invocation)
269: 41(ptr) AccessChain 27(data) 68 29
270: 18(fvec4) Load 269
271: 6(int) Load 8(invocation)
272: 18(fvec4) GroupNonUniformShuffleXor 35 270 271
273: 41(ptr) AccessChain 27(data) 268 29
Store 273 272
274: 6(int) Load 8(invocation)
275: 75(ptr) AccessChain 27(data) 29 39 30
276: 19(int) Load 275
277: 6(int) Load 8(invocation)
278: 19(int) GroupNonUniformShuffleXor 35 276 277
279: 75(ptr) AccessChain 27(data) 274 39 30
Store 279 278
280: 6(int) Load 8(invocation)
281: 83(ptr) AccessChain 27(data) 39 39
282: 20(ivec4) Load 281
283: 82(ivec2) VectorShuffle 282 282 0 1
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
284: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
285: 82(ivec2) GroupNonUniformShuffleXor 35 283 284
286: 75(ptr) AccessChain 27(data) 280 39 30
287: 19(int) CompositeExtract 285 0
Store 286 287
288: 75(ptr) AccessChain 27(data) 280 39 49
289: 19(int) CompositeExtract 285 1
Store 288 289
290: 6(int) Load 8(invocation)
291: 83(ptr) AccessChain 27(data) 53 39
292: 20(ivec4) Load 291
293: 94(ivec3) VectorShuffle 292 292 0 1 2
294: 6(int) Load 8(invocation)
295: 94(ivec3) GroupNonUniformShuffleXor 35 293 294
296: 75(ptr) AccessChain 27(data) 290 39 30
297: 19(int) CompositeExtract 295 0
Store 296 297
298: 75(ptr) AccessChain 27(data) 290 39 49
299: 19(int) CompositeExtract 295 1
Store 298 299
300: 75(ptr) AccessChain 27(data) 290 39 64
301: 19(int) CompositeExtract 295 2
Store 300 301
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
302: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
303: 83(ptr) AccessChain 27(data) 68 39
304: 20(ivec4) Load 303
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
305: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
306: 20(ivec4) GroupNonUniformShuffleXor 35 304 305
307: 83(ptr) AccessChain 27(data) 302 39
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Store 307 306
308: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
309: 113(ptr) AccessChain 27(data) 29 53 30
310: 6(int) Load 309
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
311: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
312: 6(int) GroupNonUniformShuffleXor 35 310 311
313: 113(ptr) AccessChain 27(data) 308 53 30
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Store 313 312
314: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
315: 121(ptr) AccessChain 27(data) 39 53
316: 21(ivec4) Load 315
317: 120(ivec2) VectorShuffle 316 316 0 1
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
318: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
319: 120(ivec2) GroupNonUniformShuffleXor 35 317 318
320: 113(ptr) AccessChain 27(data) 314 53 30
321: 6(int) CompositeExtract 319 0
Store 320 321
322: 113(ptr) AccessChain 27(data) 314 53 49
323: 6(int) CompositeExtract 319 1
Store 322 323
324: 6(int) Load 8(invocation)
325: 121(ptr) AccessChain 27(data) 53 53
326: 21(ivec4) Load 325
327: 132(ivec3) VectorShuffle 326 326 0 1 2
328: 6(int) Load 8(invocation)
329: 132(ivec3) GroupNonUniformShuffleXor 35 327 328
330: 113(ptr) AccessChain 27(data) 324 53 30
331: 6(int) CompositeExtract 329 0
Store 330 331
332: 113(ptr) AccessChain 27(data) 324 53 49
333: 6(int) CompositeExtract 329 1
Store 332 333
334: 113(ptr) AccessChain 27(data) 324 53 64
335: 6(int) CompositeExtract 329 2
Store 334 335
336: 6(int) Load 8(invocation)
337: 121(ptr) AccessChain 27(data) 68 53
338: 21(ivec4) Load 337
339: 6(int) Load 8(invocation)
340: 21(ivec4) GroupNonUniformShuffleXor 35 338 339
341: 121(ptr) AccessChain 27(data) 336 53
Store 341 340
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
342: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
343: 151(ptr) AccessChain 27(data) 29 68 30
344:22(float64_t) Load 343
345: 6(int) Load 8(invocation)
346:22(float64_t) GroupNonUniformShuffleXor 35 344 345
347: 151(ptr) AccessChain 27(data) 342 68 30
Store 347 346
348: 6(int) Load 8(invocation)
349: 159(ptr) AccessChain 27(data) 39 68
350: 23(f64vec4) Load 349
351:158(f64vec2) VectorShuffle 350 350 0 1
352: 6(int) Load 8(invocation)
353:158(f64vec2) GroupNonUniformShuffleXor 35 351 352
354: 151(ptr) AccessChain 27(data) 348 68 30
355:22(float64_t) CompositeExtract 353 0
Store 354 355
356: 151(ptr) AccessChain 27(data) 348 68 49
357:22(float64_t) CompositeExtract 353 1
Store 356 357
358: 6(int) Load 8(invocation)
359: 159(ptr) AccessChain 27(data) 53 68
360: 23(f64vec4) Load 359
361:170(f64vec3) VectorShuffle 360 360 0 1 2
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
362: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
363:170(f64vec3) GroupNonUniformShuffleXor 35 361 362
364: 151(ptr) AccessChain 27(data) 358 68 30
365:22(float64_t) CompositeExtract 363 0
Store 364 365
366: 151(ptr) AccessChain 27(data) 358 68 49
367:22(float64_t) CompositeExtract 363 1
Store 366 367
368: 151(ptr) AccessChain 27(data) 358 68 64
369:22(float64_t) CompositeExtract 363 2
Store 368 369
370: 6(int) Load 8(invocation)
371: 159(ptr) AccessChain 27(data) 68 68
372: 23(f64vec4) Load 371
373: 6(int) Load 8(invocation)
374: 23(f64vec4) GroupNonUniformShuffleXor 35 372 373
375: 159(ptr) AccessChain 27(data) 370 68
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Store 375 374
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
376: 6(int) Load 8(invocation)
377: 75(ptr) AccessChain 27(data) 29 39 30
378: 19(int) Load 377
379: 191(bool) SLessThan 378 29
380: 6(int) Load 8(invocation)
381: 191(bool) GroupNonUniformShuffleXor 35 379 380
382: 19(int) Select 381 39 29
383: 75(ptr) AccessChain 27(data) 376 39 30
Store 383 382
384: 6(int) Load 8(invocation)
385: 83(ptr) AccessChain 27(data) 39 39
386: 20(ivec4) Load 385
387: 82(ivec2) VectorShuffle 386 386 0 1
388: 202(bvec2) SLessThan 387 201
389: 6(int) Load 8(invocation)
390: 202(bvec2) GroupNonUniformShuffleXor 35 388 389
391: 82(ivec2) Select 390 206 201
392: 75(ptr) AccessChain 27(data) 384 39 30
393: 19(int) CompositeExtract 391 0
Store 392 393
394: 75(ptr) AccessChain 27(data) 384 39 49
395: 19(int) CompositeExtract 391 1
Store 394 395
396: 6(int) Load 8(invocation)
397: 83(ptr) AccessChain 27(data) 39 39
398: 20(ivec4) Load 397
399: 94(ivec3) VectorShuffle 398 398 0 1 2
400: 217(bvec3) SLessThan 399 216
401: 6(int) Load 8(invocation)
402: 217(bvec3) GroupNonUniformShuffleXor 35 400 401
403: 94(ivec3) Select 402 221 216
404: 75(ptr) AccessChain 27(data) 396 39 30
405: 19(int) CompositeExtract 403 0
Store 404 405
406: 75(ptr) AccessChain 27(data) 396 39 49
407: 19(int) CompositeExtract 403 1
Store 406 407
408: 75(ptr) AccessChain 27(data) 396 39 64
409: 19(int) CompositeExtract 403 2
Store 408 409
410: 6(int) Load 8(invocation)
411: 83(ptr) AccessChain 27(data) 39 39
412: 20(ivec4) Load 411
413: 233(bvec4) SLessThan 412 232
414: 6(int) Load 8(invocation)
415: 233(bvec4) GroupNonUniformShuffleXor 35 413 414
416: 20(ivec4) Select 415 237 232
417: 83(ptr) AccessChain 27(data) 410 39
Store 417 416
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
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FunctionEnd
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