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glslang/Test/baseResults/spv.image.frag.out

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Tests: Move to just linefeed to simply cross-platform test changes.
2015-12-11 01:01:54 +00:00
spv.image.frag
Modify testing to only record validation pass/fail * Changed unit tests to only record known the validation pass/fail status * errors are output as part of the failure message if the result is unexpected * can turn off validation for each test individually * Moved some SPV_KHR_vulkan_memory_model tests to be compiled for Vulkan 1.1
2018-12-04 15:43:23 +00:00
Validation failed
SPV Version: Emit the requested SPIR-V version, not the header version. Fixes #1236.
2018-02-01 01:35:56 +00:00
// Module Version 10000
Update CHANGES for release 11.12.0
2022-10-13 00:16:41 +00:00
// Generated by (magic number): 8000b
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
// Id's are bound by 405
Tests: Move to just linefeed to simply cross-platform test changes.
2015-12-11 01:01:54 +00:00
Capability Shader
SPV: Correct selection of storage-image capabilities. Fixes #986. Code was reflecting an old historical use of sampled as a SPIR-V 2-valued operand, instead of its current 3 values.
2017-08-15 04:10:00 +00:00
Capability StorageImageMultisample
Capability ImageCubeArray
Capability ImageRect
Capability Image1D
Capability ImageBuffer
SPV Capabilities: Image types. SampledBuffer ImageBuffer Sampled1D Image1D SampledCubeArray ImageCubeArray SampledRect ImageRect InputAttachment ImageMSArray StorageImageMultisample
2016-02-15 00:37:30 +00:00
Capability ImageMSArray
SPV Capabilities: StorageImageExtendedFormats, StorageImageReadWithoutFormat, and StorageImageWriteWithoutFormat.
2016-02-15 18:57:00 +00:00
Capability StorageImageExtendedFormats
SPV Capabilities: SampleRateShading, SparseResidency, MinLod, and ImageQuery.
2016-02-15 18:09:46 +00:00
Capability ImageQuery
SPV Capabilities: StorageImageExtendedFormats, StorageImageReadWithoutFormat, and StorageImageWriteWithoutFormat.
2016-02-15 18:57:00 +00:00
Capability StorageImageWriteWithoutFormat
Tests: Move to just linefeed to simply cross-platform test changes.
2015-12-11 01:01:54 +00:00
1: ExtInstImport "GLSL.std.450"
MemoryModel Logical GLSL450
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
EntryPoint Fragment 4 "main" 143 153 163 258 391 404
SPV: Implement Vulkan version of GLSL (KHR_vulkan_glsl).
2016-02-16 03:58:50 +00:00
ExecutionMode 4 OriginUpperLeft
Tests: Move to just linefeed to simply cross-platform test changes.
2015-12-11 01:01:54 +00:00
Source GLSL 450
Name 4 "main"
Name 9 "iv"
Name 15 "i1D"
Name 27 "i2D"
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
Name 41 "i3D"
Name 48 "iCube"
Name 60 "iCubeArray"
Name 67 "i2DRect"
Name 79 "i1DArray"
Name 91 "i2DArray"
Name 98 "iBuffer"
Name 107 "i2DMS"
Name 119 "i2DMSArray"
Name 138 "v"
Name 143 "ic1D"
Name 153 "ic2D"
Name 163 "ic3D"
Name 240 "ui"
Name 243 "ii1D"
Name 255 "ui2D"
Name 258 "value"
Name 367 "ii2DMS"
Name 377 "ui2DMSArray"
Name 386 "wo2D"
Name 391 "fragData"
Name 404 "ic4D"
SPV: Implement Vulkan version of GLSL (KHR_vulkan_glsl).
2016-02-16 03:58:50 +00:00
Decorate 15(i1D) DescriptorSet 0
Tests: Move to just linefeed to simply cross-platform test changes.
2015-12-11 01:01:54 +00:00
Decorate 15(i1D) Binding 0
SPV: Implement Vulkan version of GLSL (KHR_vulkan_glsl).
2016-02-16 03:58:50 +00:00
Decorate 27(i2D) DescriptorSet 0
Tests: Move to just linefeed to simply cross-platform test changes.
2015-12-11 01:01:54 +00:00
Decorate 27(i2D) Binding 1
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
Decorate 41(i3D) DescriptorSet 0
Decorate 41(i3D) Binding 2
Decorate 48(iCube) DescriptorSet 0
Decorate 48(iCube) Binding 3
Decorate 60(iCubeArray) DescriptorSet 0
Decorate 60(iCubeArray) Binding 4
Decorate 67(i2DRect) DescriptorSet 0
Decorate 67(i2DRect) Binding 5
Decorate 79(i1DArray) DescriptorSet 0
Decorate 79(i1DArray) Binding 6
Decorate 91(i2DArray) DescriptorSet 0
Decorate 91(i2DArray) Binding 7
Decorate 98(iBuffer) DescriptorSet 0
Decorate 98(iBuffer) Binding 8
Decorate 107(i2DMS) DescriptorSet 0
Decorate 107(i2DMS) Binding 9
Decorate 119(i2DMSArray) DescriptorSet 0
Decorate 119(i2DMSArray) Binding 10
Decorate 143(ic1D) Flat
Decorate 143(ic1D) Location 0
Decorate 153(ic2D) Flat
Decorate 153(ic2D) Location 1
Decorate 163(ic3D) Flat
Decorate 163(ic3D) Location 2
Decorate 243(ii1D) DescriptorSet 0
Decorate 243(ii1D) Binding 11
Decorate 255(ui2D) DescriptorSet 0
Decorate 255(ui2D) Binding 12
Decorate 258(value) Flat
Decorate 258(value) Location 4
Decorate 367(ii2DMS) DescriptorSet 0
Decorate 367(ii2DMS) Binding 13
Decorate 377(ui2DMSArray) DescriptorSet 0
Decorate 377(ui2DMSArray) Binding 14
Decorate 386(wo2D) DescriptorSet 0
Decorate 386(wo2D) Binding 1
Decorate 386(wo2D) NonReadable
Decorate 391(fragData) Location 0
Decorate 404(ic4D) Flat
Decorate 404(ic4D) Location 3
Tests: Move to just linefeed to simply cross-platform test changes.
2015-12-11 01:01:54 +00:00
2: TypeVoid
3: TypeFunction 2
6: TypeInt 32 1
7: TypeVector 6(int) 3
8: TypePointer Function 7(ivec3)
10: 6(int) Constant 0
11: 7(ivec3) ConstantComposite 10 10 10
12: TypeFloat 32
13: TypeImage 12(float) 1D nonsampled format:Rgba32f
14: TypePointer UniformConstant 13
15(i1D): 14(ptr) Variable UniformConstant
18: TypeInt 32 0
19: 18(int) Constant 0
20: TypePointer Function 6(int)
25: TypeImage 12(float) 2D nonsampled format:Rgba32f
26: TypePointer UniformConstant 25
27(i2D): 26(ptr) Variable UniformConstant
29: TypeVector 6(int) 2
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
36: 18(int) Constant 1
39: TypeImage 12(float) 3D nonsampled format:Rgba32f
40: TypePointer UniformConstant 39
41(i3D): 40(ptr) Variable UniformConstant
46: TypeImage 12(float) Cube nonsampled format:Rgba32f
47: TypePointer UniformConstant 46
48(iCube): 47(ptr) Variable UniformConstant
58: TypeImage 12(float) Cube array nonsampled format:Rgba32f
59: TypePointer UniformConstant 58
60(iCubeArray): 59(ptr) Variable UniformConstant
65: TypeImage 12(float) Rect nonsampled format:Rgba32f
66: TypePointer UniformConstant 65
67(i2DRect): 66(ptr) Variable UniformConstant
77: TypeImage 12(float) 1D array nonsampled format:Rgba32f
78: TypePointer UniformConstant 77
79(i1DArray): 78(ptr) Variable UniformConstant
89: TypeImage 12(float) 2D array nonsampled format:Rg16
90: TypePointer UniformConstant 89
91(i2DArray): 90(ptr) Variable UniformConstant
96: TypeImage 12(float) Buffer nonsampled format:Rgba32f
Tests: Move to just linefeed to simply cross-platform test changes.
2015-12-11 01:01:54 +00:00
97: TypePointer UniformConstant 96
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
98(iBuffer): 97(ptr) Variable UniformConstant
105: TypeImage 12(float) 2D multi-sampled nonsampled format:Rgba32f
106: TypePointer UniformConstant 105
107(i2DMS): 106(ptr) Variable UniformConstant
117: TypeImage 12(float) 2D array multi-sampled nonsampled format:Rgba32f
118: TypePointer UniformConstant 117
119(i2DMSArray): 118(ptr) Variable UniformConstant
136: TypeVector 12(float) 4
137: TypePointer Function 136(fvec4)
139: 12(float) Constant 0
140: 136(fvec4) ConstantComposite 139 139 139 139
142: TypePointer Input 6(int)
143(ic1D): 142(ptr) Variable Input
152: TypePointer Input 29(ivec2)
153(ic2D): 152(ptr) Variable Input
162: TypePointer Input 7(ivec3)
163(ic3D): 162(ptr) Variable Input
221: 6(int) Constant 1
227: 6(int) Constant 2
231: 6(int) Constant 3
237: 6(int) Constant 4
239: TypePointer Function 18(int)
241: TypeImage 6(int) 1D nonsampled format:R32i
242: TypePointer UniformConstant 241
243(ii1D): 242(ptr) Variable UniformConstant
245: 6(int) Constant 10
246: TypePointer Image 6(int)
253: TypeImage 18(int) 2D nonsampled format:R32ui
254: TypePointer UniformConstant 253
255(ui2D): 254(ptr) Variable UniformConstant
257: TypePointer Input 18(int)
258(value): 257(ptr) Variable Input
260: TypePointer Image 18(int)
266: 6(int) Constant 11
280: 6(int) Constant 12
294: 6(int) Constant 13
308: 6(int) Constant 14
322: 6(int) Constant 15
336: 6(int) Constant 16
350: 6(int) Constant 18
351: 6(int) Constant 17
359: 18(int) Constant 19
365: TypeImage 6(int) 2D multi-sampled nonsampled format:R32i
Fix a parse issue of imageAtomicCompSwap() The max count of arguments is 5 when image2DMS/image2DMSArray is specified.
2018-10-17 05:55:11 +00:00
366: TypePointer UniformConstant 365
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
367(ii2DMS): 366(ptr) Variable UniformConstant
375: TypeImage 18(int) 2D array multi-sampled nonsampled format:R32ui
376: TypePointer UniformConstant 375
377(ui2DMSArray): 376(ptr) Variable UniformConstant
384: TypeImage 12(float) 2D nonsampled format:Unknown
385: TypePointer UniformConstant 384
386(wo2D): 385(ptr) Variable UniformConstant
390: TypePointer Output 136(fvec4)
391(fragData): 390(ptr) Variable Output
396: TypeBool
399: TypeVector 396(bool) 4
402: TypeVector 6(int) 4
403: TypePointer Input 402(ivec4)
404(ic4D): 403(ptr) Variable Input
Tests: Move to just linefeed to simply cross-platform test changes.
2015-12-11 01:01:54 +00:00
4(main): 2 Function None 3
5: Label
9(iv): 8(ptr) Variable Function
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
138(v): 137(ptr) Variable Function
240(ui): 239(ptr) Variable Function
Tests: Move to just linefeed to simply cross-platform test changes.
2015-12-11 01:01:54 +00:00
Store 9(iv) 11
16: 13 Load 15(i1D)
17: 6(int) ImageQuerySize 16
21: 20(ptr) AccessChain 9(iv) 19
22: 6(int) Load 21
23: 6(int) IAdd 22 17
24: 20(ptr) AccessChain 9(iv) 19
Store 24 23
28: 25 Load 27(i2D)
30: 29(ivec2) ImageQuerySize 28
31: 7(ivec3) Load 9(iv)
32: 29(ivec2) VectorShuffle 31 31 0 1
33: 29(ivec2) IAdd 32 30
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
34: 20(ptr) AccessChain 9(iv) 19
35: 6(int) CompositeExtract 33 0
Store 34 35
37: 20(ptr) AccessChain 9(iv) 36
38: 6(int) CompositeExtract 33 1
Store 37 38
42: 39 Load 41(i3D)
43: 7(ivec3) ImageQuerySize 42
44: 7(ivec3) Load 9(iv)
45: 7(ivec3) IAdd 44 43
Store 9(iv) 45
49: 46 Load 48(iCube)
50: 29(ivec2) ImageQuerySize 49
Tests: Move to just linefeed to simply cross-platform test changes.
2015-12-11 01:01:54 +00:00
51: 7(ivec3) Load 9(iv)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
52: 29(ivec2) VectorShuffle 51 51 0 1
53: 29(ivec2) IAdd 52 50
54: 20(ptr) AccessChain 9(iv) 19
55: 6(int) CompositeExtract 53 0
Store 54 55
56: 20(ptr) AccessChain 9(iv) 36
57: 6(int) CompositeExtract 53 1
Store 56 57
61: 58 Load 60(iCubeArray)
62: 7(ivec3) ImageQuerySize 61
63: 7(ivec3) Load 9(iv)
64: 7(ivec3) IAdd 63 62
Store 9(iv) 64
68: 65 Load 67(i2DRect)
69: 29(ivec2) ImageQuerySize 68
70: 7(ivec3) Load 9(iv)
71: 29(ivec2) VectorShuffle 70 70 0 1
72: 29(ivec2) IAdd 71 69
73: 20(ptr) AccessChain 9(iv) 19
74: 6(int) CompositeExtract 72 0
Store 73 74
75: 20(ptr) AccessChain 9(iv) 36
76: 6(int) CompositeExtract 72 1
Store 75 76
80: 77 Load 79(i1DArray)
81: 29(ivec2) ImageQuerySize 80
82: 7(ivec3) Load 9(iv)
83: 29(ivec2) VectorShuffle 82 82 0 1
84: 29(ivec2) IAdd 83 81
85: 20(ptr) AccessChain 9(iv) 19
86: 6(int) CompositeExtract 84 0
Store 85 86
87: 20(ptr) AccessChain 9(iv) 36
88: 6(int) CompositeExtract 84 1
Store 87 88
92: 89 Load 91(i2DArray)
93: 7(ivec3) ImageQuerySize 92
94: 7(ivec3) Load 9(iv)
95: 7(ivec3) IAdd 94 93
Store 9(iv) 95
99: 96 Load 98(iBuffer)
100: 6(int) ImageQuerySize 99
101: 20(ptr) AccessChain 9(iv) 19
102: 6(int) Load 101
103: 6(int) IAdd 102 100
104: 20(ptr) AccessChain 9(iv) 19
Store 104 103
108: 105 Load 107(i2DMS)
109: 29(ivec2) ImageQuerySize 108
110: 7(ivec3) Load 9(iv)
111: 29(ivec2) VectorShuffle 110 110 0 1
112: 29(ivec2) IAdd 111 109
113: 20(ptr) AccessChain 9(iv) 19
114: 6(int) CompositeExtract 112 0
Store 113 114
115: 20(ptr) AccessChain 9(iv) 36
116: 6(int) CompositeExtract 112 1
Store 115 116
120: 117 Load 119(i2DMSArray)
121: 7(ivec3) ImageQuerySize 120
122: 7(ivec3) Load 9(iv)
123: 7(ivec3) IAdd 122 121
Store 9(iv) 123
124: 105 Load 107(i2DMS)
125: 6(int) ImageQuerySamples 124
126: 20(ptr) AccessChain 9(iv) 19
127: 6(int) Load 126
128: 6(int) IAdd 127 125
129: 20(ptr) AccessChain 9(iv) 19
Store 129 128
130: 117 Load 119(i2DMSArray)
131: 6(int) ImageQuerySamples 130
132: 20(ptr) AccessChain 9(iv) 19
133: 6(int) Load 132
134: 6(int) IAdd 133 131
135: 20(ptr) AccessChain 9(iv) 19
Store 135 134
Store 138(v) 140
141: 13 Load 15(i1D)
144: 6(int) Load 143(ic1D)
145: 136(fvec4) ImageRead 141 144
146: 136(fvec4) Load 138(v)
147: 136(fvec4) FAdd 146 145
Store 138(v) 147
148: 13 Load 15(i1D)
149: 6(int) Load 143(ic1D)
150: 136(fvec4) Load 138(v)
ImageWrite 148 149 150
151: 25 Load 27(i2D)
154: 29(ivec2) Load 153(ic2D)
155: 136(fvec4) ImageRead 151 154
156: 136(fvec4) Load 138(v)
157: 136(fvec4) FAdd 156 155
Store 138(v) 157
158: 25 Load 27(i2D)
159: 29(ivec2) Load 153(ic2D)
160: 136(fvec4) Load 138(v)
ImageWrite 158 159 160
161: 39 Load 41(i3D)
164: 7(ivec3) Load 163(ic3D)
165: 136(fvec4) ImageRead 161 164
166: 136(fvec4) Load 138(v)
167: 136(fvec4) FAdd 166 165
Store 138(v) 167
168: 39 Load 41(i3D)
169: 7(ivec3) Load 163(ic3D)
170: 136(fvec4) Load 138(v)
ImageWrite 168 169 170
171: 46 Load 48(iCube)
172: 7(ivec3) Load 163(ic3D)
173: 136(fvec4) ImageRead 171 172
174: 136(fvec4) Load 138(v)
175: 136(fvec4) FAdd 174 173
Store 138(v) 175
176: 46 Load 48(iCube)
177: 7(ivec3) Load 163(ic3D)
178: 136(fvec4) Load 138(v)
ImageWrite 176 177 178
179: 58 Load 60(iCubeArray)
180: 7(ivec3) Load 163(ic3D)
181: 136(fvec4) ImageRead 179 180
182: 136(fvec4) Load 138(v)
183: 136(fvec4) FAdd 182 181
Store 138(v) 183
184: 58 Load 60(iCubeArray)
185: 7(ivec3) Load 163(ic3D)
186: 136(fvec4) Load 138(v)
ImageWrite 184 185 186
187: 65 Load 67(i2DRect)
188: 29(ivec2) Load 153(ic2D)
189: 136(fvec4) ImageRead 187 188
190: 136(fvec4) Load 138(v)
191: 136(fvec4) FAdd 190 189
Store 138(v) 191
192: 65 Load 67(i2DRect)
193: 29(ivec2) Load 153(ic2D)
194: 136(fvec4) Load 138(v)
ImageWrite 192 193 194
195: 77 Load 79(i1DArray)
196: 29(ivec2) Load 153(ic2D)
197: 136(fvec4) ImageRead 195 196
198: 136(fvec4) Load 138(v)
199: 136(fvec4) FAdd 198 197
Store 138(v) 199
200: 77 Load 79(i1DArray)
201: 29(ivec2) Load 153(ic2D)
202: 136(fvec4) Load 138(v)
ImageWrite 200 201 202
203: 89 Load 91(i2DArray)
204: 7(ivec3) Load 163(ic3D)
205: 136(fvec4) ImageRead 203 204
206: 136(fvec4) Load 138(v)
207: 136(fvec4) FAdd 206 205
Store 138(v) 207
208: 89 Load 91(i2DArray)
209: 7(ivec3) Load 163(ic3D)
210: 136(fvec4) Load 138(v)
ImageWrite 208 209 210
211: 96 Load 98(iBuffer)
212: 6(int) Load 143(ic1D)
213: 136(fvec4) ImageRead 211 212
214: 136(fvec4) Load 138(v)
215: 136(fvec4) FAdd 214 213
Store 138(v) 215
216: 96 Load 98(iBuffer)
217: 6(int) Load 143(ic1D)
218: 136(fvec4) Load 138(v)
ImageWrite 216 217 218
219: 105 Load 107(i2DMS)
220: 29(ivec2) Load 153(ic2D)
222: 136(fvec4) ImageRead 219 220 Sample 221
223: 136(fvec4) Load 138(v)
224: 136(fvec4) FAdd 223 222
Store 138(v) 224
225: 105 Load 107(i2DMS)
226: 29(ivec2) Load 153(ic2D)
228: 136(fvec4) Load 138(v)
ImageWrite 225 226 228 Sample 227
229: 117 Load 119(i2DMSArray)
230: 7(ivec3) Load 163(ic3D)
232: 136(fvec4) ImageRead 229 230 Sample 231
233: 136(fvec4) Load 138(v)
234: 136(fvec4) FAdd 233 232
Store 138(v) 234
235: 117 Load 119(i2DMSArray)
236: 7(ivec3) Load 163(ic3D)
238: 136(fvec4) Load 138(v)
ImageWrite 235 236 238 Sample 237
Store 240(ui) 19
244: 6(int) Load 143(ic1D)
247: 246(ptr) ImageTexelPointer 243(ii1D) 244 19
248: 6(int) AtomicIAdd 247 36 19 245
249: 20(ptr) AccessChain 9(iv) 19
250: 6(int) Load 249
251: 6(int) IAdd 250 248
252: 20(ptr) AccessChain 9(iv) 19
Store 252 251
256: 29(ivec2) Load 153(ic2D)
259: 18(int) Load 258(value)
261: 260(ptr) ImageTexelPointer 255(ui2D) 256 19
262: 18(int) AtomicIAdd 261 36 19 259
263: 18(int) Load 240(ui)
264: 18(int) IAdd 263 262
Store 240(ui) 264
265: 6(int) Load 143(ic1D)
267: 246(ptr) ImageTexelPointer 243(ii1D) 265 19
268: 6(int) AtomicSMin 267 36 19 266
269: 20(ptr) AccessChain 9(iv) 19
270: 6(int) Load 269
271: 6(int) IAdd 270 268
272: 20(ptr) AccessChain 9(iv) 19
Store 272 271
273: 29(ivec2) Load 153(ic2D)
274: 18(int) Load 258(value)
275: 260(ptr) ImageTexelPointer 255(ui2D) 273 19
276: 18(int) AtomicUMin 275 36 19 274
277: 18(int) Load 240(ui)
278: 18(int) IAdd 277 276
Store 240(ui) 278
279: 6(int) Load 143(ic1D)
281: 246(ptr) ImageTexelPointer 243(ii1D) 279 19
282: 6(int) AtomicSMax 281 36 19 280
283: 20(ptr) AccessChain 9(iv) 19
284: 6(int) Load 283
285: 6(int) IAdd 284 282
286: 20(ptr) AccessChain 9(iv) 19
Store 286 285
287: 29(ivec2) Load 153(ic2D)
288: 18(int) Load 258(value)
289: 260(ptr) ImageTexelPointer 255(ui2D) 287 19
290: 18(int) AtomicUMax 289 36 19 288
291: 18(int) Load 240(ui)
292: 18(int) IAdd 291 290
Store 240(ui) 292
293: 6(int) Load 143(ic1D)
295: 246(ptr) ImageTexelPointer 243(ii1D) 293 19
296: 6(int) AtomicAnd 295 36 19 294
297: 20(ptr) AccessChain 9(iv) 19
298: 6(int) Load 297
299: 6(int) IAdd 298 296
300: 20(ptr) AccessChain 9(iv) 19
Store 300 299
301: 29(ivec2) Load 153(ic2D)
302: 18(int) Load 258(value)
303: 260(ptr) ImageTexelPointer 255(ui2D) 301 19
304: 18(int) AtomicAnd 303 36 19 302
305: 18(int) Load 240(ui)
306: 18(int) IAdd 305 304
Store 240(ui) 306
307: 6(int) Load 143(ic1D)
309: 246(ptr) ImageTexelPointer 243(ii1D) 307 19
310: 6(int) AtomicOr 309 36 19 308
311: 20(ptr) AccessChain 9(iv) 19
312: 6(int) Load 311
313: 6(int) IAdd 312 310
314: 20(ptr) AccessChain 9(iv) 19
Store 314 313
315: 29(ivec2) Load 153(ic2D)
316: 18(int) Load 258(value)
317: 260(ptr) ImageTexelPointer 255(ui2D) 315 19
318: 18(int) AtomicOr 317 36 19 316
319: 18(int) Load 240(ui)
320: 18(int) IAdd 319 318
Store 240(ui) 320
321: 6(int) Load 143(ic1D)
323: 246(ptr) ImageTexelPointer 243(ii1D) 321 19
324: 6(int) AtomicXor 323 36 19 322
325: 20(ptr) AccessChain 9(iv) 19
326: 6(int) Load 325
327: 6(int) IAdd 326 324
328: 20(ptr) AccessChain 9(iv) 19
Store 328 327
329: 29(ivec2) Load 153(ic2D)
330: 18(int) Load 258(value)
331: 260(ptr) ImageTexelPointer 255(ui2D) 329 19
332: 18(int) AtomicXor 331 36 19 330
333: 18(int) Load 240(ui)
334: 18(int) IAdd 333 332
Store 240(ui) 334
335: 6(int) Load 143(ic1D)
337: 246(ptr) ImageTexelPointer 243(ii1D) 335 19
338: 6(int) AtomicExchange 337 36 19 336
339: 20(ptr) AccessChain 9(iv) 19
340: 6(int) Load 339
341: 6(int) IAdd 340 338
342: 20(ptr) AccessChain 9(iv) 19
Store 342 341
343: 29(ivec2) Load 153(ic2D)
344: 18(int) Load 258(value)
345: 260(ptr) ImageTexelPointer 255(ui2D) 343 19
346: 18(int) AtomicExchange 345 36 19 344
347: 18(int) Load 240(ui)
348: 18(int) IAdd 347 346
Store 240(ui) 348
349: 6(int) Load 143(ic1D)
352: 246(ptr) ImageTexelPointer 243(ii1D) 349 19
353: 6(int) AtomicCompareExchange 352 36 19 19 351 350
354: 20(ptr) AccessChain 9(iv) 19
355: 6(int) Load 354
356: 6(int) IAdd 355 353
357: 20(ptr) AccessChain 9(iv) 19
Store 357 356
358: 29(ivec2) Load 153(ic2D)
360: 18(int) Load 258(value)
361: 260(ptr) ImageTexelPointer 255(ui2D) 358 19
362: 18(int) AtomicCompareExchange 361 36 19 19 360 359
363: 18(int) Load 240(ui)
364: 18(int) IAdd 363 362
Store 240(ui) 364
368: 29(ivec2) Load 153(ic2D)
369: 246(ptr) ImageTexelPointer 367(ii2DMS) 368 227
370: 6(int) AtomicCompareExchange 369 36 19 19 351 350
371: 20(ptr) AccessChain 9(iv) 19
372: 6(int) Load 371
373: 6(int) IAdd 372 370
374: 20(ptr) AccessChain 9(iv) 19
Store 374 373
378: 7(ivec3) Load 163(ic3D)
379: 18(int) Load 258(value)
380: 260(ptr) ImageTexelPointer 377(ui2DMSArray) 378 231
381: 18(int) AtomicCompareExchange 380 36 19 19 379 359
382: 18(int) Load 240(ui)
383: 18(int) IAdd 382 381
Store 240(ui) 383
387: 384 Load 386(wo2D)
388: 29(ivec2) Load 153(ic2D)
389: 136(fvec4) Load 138(v)
ImageWrite 387 388 389
392: 18(int) Load 240(ui)
393: 20(ptr) AccessChain 9(iv) 36
394: 6(int) Load 393
395: 18(int) Bitcast 394
397: 396(bool) INotEqual 392 395
398: 136(fvec4) Load 138(v)
400: 399(bvec4) CompositeConstruct 397 397 397 397
401: 136(fvec4) Select 400 398 140
Store 391(fragData) 401
Tests: Move to just linefeed to simply cross-platform test changes.
2015-12-11 01:01:54 +00:00
Return
FunctionEnd
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