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glslang/Test/baseResults/hlsl.automap.frag.out

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WIP: HLSL: hlsl register class iomapping Adds --hlsl-iomap option to perform IO mapping in HLSL register space. --shift-cbuffer-binding is now a synonym for --shift-ubo-binding. The idea way to do this seems to be passing in a dedicated IO resolver, but that would require more intrusive restructuring, so maybe best for its own PR. The TDefaultHlslIoResolver class and the former TDefaultIoResolver class share quite a bit of mechanism in a common base class. TODO: tbuffers are landing in the wrong register class, which needs some investigation. They're either wrong upstream, or the detection in the resolver is wrong.
2017-04-18 18:18:01 +00:00
hlsl.automap.frag
Uniform reflection:
Reflection exposes the Shader Stages where a Uniform is present
2018-07-10 15:25:48 +00:00
t1: offset -1, type 8b5d, size 1, index -1, binding 11, stages 16
t2: offset -1, type 8b5e, size 1, index -1, binding 12, stages 16
t3: offset -1, type 8b5f, size 1, index -1, binding 13, stages 16
Reflect array stride, top-level array stride, and block member count
2019-01-29 19:10:56 +00:00
t4.@data: offset 0, type 8b52, size 1, index 0, binding -1, stages 16, arrayStride 16, topLevelArrayStride 16
t5.@data: offset 0, type 1405, size 0, index 1, binding -1, stages 16, arrayStride 4, topLevelArrayStride 4
Reflection exposes the Shader Stages where a Uniform is present
2018-07-10 15:25:48 +00:00
t6: offset -1, type 8dc2, size 1, index -1, binding 16, stages 16
s1: offset -1, type 0, size 1, index -1, binding 31, stages 16
s2: offset -1, type 0, size 1, index -1, binding 32, stages 16
u1: offset -1, type 904c, size 1, index -1, binding 41, stages 16
u2: offset -1, type 904d, size 1, index -1, binding 42, stages 16
u3: offset -1, type 904e, size 1, index -1, binding 43, stages 16
u4: offset -1, type 9051, size 1, index -1, binding 44, stages 16
Reflect array stride, top-level array stride, and block member count
2019-01-29 19:10:56 +00:00
u5.@data: offset 0, type 1405, size 0, index 2, binding -1, stages 16, arrayStride 4, topLevelArrayStride 4
u6.@data: offset 0, type 1406, size 1, index 3, binding -1, stages 16, arrayStride 4, topLevelArrayStride 4
Reflection exposes the Shader Stages where a Uniform is present
2018-07-10 15:25:48 +00:00
cb1: offset 0, type 1404, size 1, index 4, binding -1, stages 16
tb1: offset 0, type 1404, size 1, index 5, binding -1, stages 16
WIP: HLSL: hlsl register class iomapping Adds --hlsl-iomap option to perform IO mapping in HLSL register space. --shift-cbuffer-binding is now a synonym for --shift-ubo-binding. The idea way to do this seems to be passing in a dedicated IO resolver, but that would require more intrusive restructuring, so maybe best for its own PR. The TDefaultHlslIoResolver class and the former TDefaultIoResolver class share quite a bit of mechanism in a common base class. TODO: tbuffers are landing in the wrong register class, which needs some investigation. They're either wrong upstream, or the detection in the resolver is wrong.
2017-04-18 18:18:01 +00:00
Uniform block reflection:
Add Shared/Std140 SSBO process & top-level array elements related (#2231) * Add Shared/Std140 SSBO process & top-level array elements related process 1.Add process options for shared/std140 ssbo, following ubo process 2.Add IO Variables reflection option, would keep all input/output variables in reflection 3.Add Top-level related process, fix top-level array size issues, following spec 4.Split ssbo/ubo reflection options, merge blowup expanding all into function blowupActiveAggregate to allow other functions keep same entry format. Add options in StandAlone and test symbols. 1. Add options in StandAlone for std140/shared ubo/ssbo and all io variables reflection. 2. Add test for ssbo. When EShReflectionSharedStd140SSBO turns on, generated symbol and output would be different, to remind the difference. Defaultly disabled and nothing would change, nor blocking normal test. * Add options in runtest script, refresh test results. Add options in StandAlone: --reflect-all-io-variables --reflect-shared-std140-ubo --reflect-shared-std140-ssbo refresh test results. Now the index, size of unsized array are expected.
2020-06-04 07:47:18 +00:00
t4: offset -1, type ffffffff, size 16, index 0, binding 14, stages 16, numMembers 1
t5: offset -1, type ffffffff, size 4, index 1, binding 15, stages 16, numMembers 1
u5: offset -1, type ffffffff, size 4, index 2, binding 45, stages 16, numMembers 1
u6: offset -1, type ffffffff, size 4, index 3, binding 46, stages 16, numMembers 1
cb: offset -1, type ffffffff, size 4, index 4, binding 51, stages 16, numMembers 1
tb: offset -1, type ffffffff, size 4, index 5, binding 17, stages 16, numMembers 1
WIP: HLSL: hlsl register class iomapping Adds --hlsl-iomap option to perform IO mapping in HLSL register space. --shift-cbuffer-binding is now a synonym for --shift-ubo-binding. The idea way to do this seems to be passing in a dedicated IO resolver, but that would require more intrusive restructuring, so maybe best for its own PR. The TDefaultHlslIoResolver class and the former TDefaultIoResolver class share quite a bit of mechanism in a common base class. TODO: tbuffers are landing in the wrong register class, which needs some investigation. They're either wrong upstream, or the detection in the resolver is wrong.
2017-04-18 18:18:01 +00:00
Add option to reflect buffer blocks & variables separately to uniforms * Also note the uniform indices of atomic counter buffers
2019-01-30 14:18:43 +00:00
Buffer variable reflection:
Buffer block reflection:
Reflect pipeline outputs as well as inputs, optionally from other stages * We add an option to reflect inputs from other stages than vertex, if only a later subset of the stages is linked into the program.
2019-01-29 16:04:44 +00:00
Pipeline input reflection:
Pipeline output reflection:
Fix treatment of array input/output variables in reflection * Non-block arrays should not be ignored when exploding types. * When not exploding, set the array size correctly on each item.
2019-02-11 16:39:12 +00:00
@entryPointOutput: offset 0, type 8b52, size 1, index 0, binding -1, stages 16
WIP: HLSL: hlsl register class iomapping Adds --hlsl-iomap option to perform IO mapping in HLSL register space. --shift-cbuffer-binding is now a synonym for --shift-ubo-binding. The idea way to do this seems to be passing in a dedicated IO resolver, but that would require more intrusive restructuring, so maybe best for its own PR. The TDefaultHlslIoResolver class and the former TDefaultIoResolver class share quite a bit of mechanism in a common base class. TODO: tbuffers are landing in the wrong register class, which needs some investigation. They're either wrong upstream, or the detection in the resolver is wrong.
2017-04-18 18:18:01 +00:00
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