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glslang/Test/baseResults/spv.subgroupArithmetic.comp.out

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SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
spv.subgroupArithmetic.comp
// Module Version 10300
Update CHANGES for release 11.12.0
2022-10-13 00:16:41 +00:00
// Generated by (magic number): 8000b
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
// Id's are bound by 2386
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Capability Shader
Capability Float64
Capability GroupNonUniform
Capability GroupNonUniformArithmetic
1: ExtInstImport "GLSL.std.450"
MemoryModel Logical GLSL450
EntryPoint GLCompute 4 "main" 10 12
ExecutionMode 4 LocalSize 8 1 1
Source GLSL 450
SourceExtension "GL_KHR_shader_subgroup_arithmetic"
SourceExtension "GL_KHR_shader_subgroup_basic"
Name 4 "main"
Name 8 "invocation"
Name 10 "gl_SubgroupInvocationID"
Name 12 "gl_SubgroupSize"
Name 24 "Buffers"
MemberName 24(Buffers) 0 "f4"
MemberName 24(Buffers) 1 "i4"
MemberName 24(Buffers) 2 "u4"
MemberName 24(Buffers) 3 "d4"
Name 27 "data"
Decorate 10(gl_SubgroupInvocationID) RelaxedPrecision
Decorate 10(gl_SubgroupInvocationID) BuiltIn SubgroupLocalInvocationId
Decorate 11 RelaxedPrecision
Decorate 12(gl_SubgroupSize) RelaxedPrecision
Decorate 12(gl_SubgroupSize) BuiltIn SubgroupSize
Decorate 13 RelaxedPrecision
Decorate 14 RelaxedPrecision
Decorate 16 RelaxedPrecision
MemberDecorate 24(Buffers) 0 Offset 0
MemberDecorate 24(Buffers) 1 Offset 16
MemberDecorate 24(Buffers) 2 Offset 32
MemberDecorate 24(Buffers) 3 Offset 64
Fix 8-bit storage nearly always using the UniformAndStorageBuffer8BitAccess capability. When using the 8-bit storage extension it basically always used the `UniformAndStorageBuffer8BitAccess` capability, even in cases where it wasn't required. For instance if we are targeting Vulkan 1.1 (SPIR-V 1.3 or higher), and we are only using 8-bit types in an SSBO, we only need the `StorageBuffer8BitAccess` capability. I fixed this by enabling storage buffer use in Vulkan 1.1 / SPIR-V 1.3 or higher, and then changing the logic to match. I also added some tests that will output different capabilities when run on Vulkan 1.0 and 1.1, thus they are added twice to the test list (one for each version). Fixes #1539
2018-10-23 14:02:29 +00:00
Decorate 24(Buffers) Block
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Decorate 27(data) DescriptorSet 0
Decorate 27(data) Binding 0
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
Decorate 2385 BuiltIn WorkgroupSize
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
2: TypeVoid
3: TypeFunction 2
6: TypeInt 32 0
7: TypePointer Function 6(int)
9: TypePointer Input 6(int)
10(gl_SubgroupInvocationID): 9(ptr) Variable Input
12(gl_SubgroupSize): 9(ptr) Variable Input
15: 6(int) Constant 4
17: TypeFloat 32
18: TypeVector 17(float) 4
19: TypeInt 32 1
20: TypeVector 19(int) 4
21: TypeVector 6(int) 4
22: TypeFloat 64
Add bit width of types to disassembleInstruction
2018-05-23 04:13:30 +00:00
23: TypeVector 22(float64_t) 4
24(Buffers): TypeStruct 18(fvec4) 20(ivec4) 21(ivec4) 23(f64vec4)
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
25: TypeArray 24(Buffers) 15
Fix 8-bit storage nearly always using the UniformAndStorageBuffer8BitAccess capability. When using the 8-bit storage extension it basically always used the `UniformAndStorageBuffer8BitAccess` capability, even in cases where it wasn't required. For instance if we are targeting Vulkan 1.1 (SPIR-V 1.3 or higher), and we are only using 8-bit types in an SSBO, we only need the `StorageBuffer8BitAccess` capability. I fixed this by enabling storage buffer use in Vulkan 1.1 / SPIR-V 1.3 or higher, and then changing the logic to match. I also added some tests that will output different capabilities when run on Vulkan 1.0 and 1.1, thus they are added twice to the test list (one for each version). Fixes #1539
2018-10-23 14:02:29 +00:00
26: TypePointer StorageBuffer 25
27(data): 26(ptr) Variable StorageBuffer
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
29: 19(int) Constant 0
30: 6(int) Constant 0
Fix 8-bit storage nearly always using the UniformAndStorageBuffer8BitAccess capability. When using the 8-bit storage extension it basically always used the `UniformAndStorageBuffer8BitAccess` capability, even in cases where it wasn't required. For instance if we are targeting Vulkan 1.1 (SPIR-V 1.3 or higher), and we are only using 8-bit types in an SSBO, we only need the `StorageBuffer8BitAccess` capability. I fixed this by enabling storage buffer use in Vulkan 1.1 / SPIR-V 1.3 or higher, and then changing the logic to match. I also added some tests that will output different capabilities when run on Vulkan 1.0 and 1.1, thus they are added twice to the test list (one for each version). Fixes #1539
2018-10-23 14:02:29 +00:00
31: TypePointer StorageBuffer 17(float)
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
34: 6(int) Constant 3
38: 19(int) Constant 1
39: TypeVector 17(float) 2
Fix 8-bit storage nearly always using the UniformAndStorageBuffer8BitAccess capability. When using the 8-bit storage extension it basically always used the `UniformAndStorageBuffer8BitAccess` capability, even in cases where it wasn't required. For instance if we are targeting Vulkan 1.1 (SPIR-V 1.3 or higher), and we are only using 8-bit types in an SSBO, we only need the `StorageBuffer8BitAccess` capability. I fixed this by enabling storage buffer use in Vulkan 1.1 / SPIR-V 1.3 or higher, and then changing the logic to match. I also added some tests that will output different capabilities when run on Vulkan 1.0 and 1.1, thus they are added twice to the test list (one for each version). Fixes #1539
2018-10-23 14:02:29 +00:00
40: TypePointer StorageBuffer 18(fvec4)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
47: 6(int) Constant 1
51: 19(int) Constant 2
52: TypeVector 17(float) 3
61: 6(int) Constant 2
65: 19(int) Constant 3
71: TypePointer StorageBuffer 19(int)
77: TypeVector 19(int) 2
78: TypePointer StorageBuffer 20(ivec4)
88: TypeVector 19(int) 3
105: TypePointer StorageBuffer 6(int)
111: TypeVector 6(int) 2
112: TypePointer StorageBuffer 21(ivec4)
122: TypeVector 6(int) 3
139: TypePointer StorageBuffer 22(float64_t)
145: TypeVector 22(float64_t) 2
146: TypePointer StorageBuffer 23(f64vec4)
156: TypeVector 22(float64_t) 3
595: TypeBool
604: 77(ivec2) ConstantComposite 29 29
605: TypeVector 595(bool) 2
608: 77(ivec2) ConstantComposite 38 38
618: 88(ivec3) ConstantComposite 29 29 29
619: TypeVector 595(bool) 3
622: 88(ivec3) ConstantComposite 38 38 38
633: 20(ivec4) ConstantComposite 29 29 29 29
634: TypeVector 595(bool) 4
637: 20(ivec4) ConstantComposite 38 38 38 38
2384: 6(int) Constant 8
2385: 122(ivec3) ConstantComposite 2384 47 47
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
4(main): 2 Function None 3
5: Label
8(invocation): 7(ptr) Variable Function
11: 6(int) Load 10(gl_SubgroupInvocationID)
13: 6(int) Load 12(gl_SubgroupSize)
14: 6(int) IAdd 11 13
16: 6(int) UMod 14 15
Store 8(invocation) 16
28: 6(int) Load 8(invocation)
32: 31(ptr) AccessChain 27(data) 29 29 30
33: 17(float) Load 32
35: 17(float) GroupNonUniformFAdd 34 Reduce 33
36: 31(ptr) AccessChain 27(data) 28 29 30
Store 36 35
37: 6(int) Load 8(invocation)
41: 40(ptr) AccessChain 27(data) 38 29
42: 18(fvec4) Load 41
43: 39(fvec2) VectorShuffle 42 42 0 1
44: 39(fvec2) GroupNonUniformFAdd 34 Reduce 43
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
45: 31(ptr) AccessChain 27(data) 37 29 30
46: 17(float) CompositeExtract 44 0
Store 45 46
48: 31(ptr) AccessChain 27(data) 37 29 47
49: 17(float) CompositeExtract 44 1
Store 48 49
50: 6(int) Load 8(invocation)
53: 40(ptr) AccessChain 27(data) 51 29
54: 18(fvec4) Load 53
55: 52(fvec3) VectorShuffle 54 54 0 1 2
56: 52(fvec3) GroupNonUniformFAdd 34 Reduce 55
57: 31(ptr) AccessChain 27(data) 50 29 30
58: 17(float) CompositeExtract 56 0
Store 57 58
59: 31(ptr) AccessChain 27(data) 50 29 47
60: 17(float) CompositeExtract 56 1
Store 59 60
62: 31(ptr) AccessChain 27(data) 50 29 61
63: 17(float) CompositeExtract 56 2
Store 62 63
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
64: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
66: 40(ptr) AccessChain 27(data) 65 29
67: 18(fvec4) Load 66
68: 18(fvec4) GroupNonUniformFAdd 34 Reduce 67
69: 40(ptr) AccessChain 27(data) 64 29
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Store 69 68
70: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
72: 71(ptr) AccessChain 27(data) 29 38 30
73: 19(int) Load 72
74: 19(int) GroupNonUniformIAdd 34 Reduce 73
75: 71(ptr) AccessChain 27(data) 70 38 30
Store 75 74
76: 6(int) Load 8(invocation)
79: 78(ptr) AccessChain 27(data) 38 38
80: 20(ivec4) Load 79
81: 77(ivec2) VectorShuffle 80 80 0 1
82: 77(ivec2) GroupNonUniformIAdd 34 Reduce 81
83: 71(ptr) AccessChain 27(data) 76 38 30
84: 19(int) CompositeExtract 82 0
Store 83 84
85: 71(ptr) AccessChain 27(data) 76 38 47
86: 19(int) CompositeExtract 82 1
Store 85 86
87: 6(int) Load 8(invocation)
89: 78(ptr) AccessChain 27(data) 51 38
90: 20(ivec4) Load 89
91: 88(ivec3) VectorShuffle 90 90 0 1 2
92: 88(ivec3) GroupNonUniformIAdd 34 Reduce 91
93: 71(ptr) AccessChain 27(data) 87 38 30
94: 19(int) CompositeExtract 92 0
Store 93 94
95: 71(ptr) AccessChain 27(data) 87 38 47
96: 19(int) CompositeExtract 92 1
Store 95 96
97: 71(ptr) AccessChain 27(data) 87 38 61
98: 19(int) CompositeExtract 92 2
Store 97 98
99: 6(int) Load 8(invocation)
100: 78(ptr) AccessChain 27(data) 65 38
101: 20(ivec4) Load 100
102: 20(ivec4) GroupNonUniformIAdd 34 Reduce 101
103: 78(ptr) AccessChain 27(data) 99 38
Store 103 102
104: 6(int) Load 8(invocation)
106: 105(ptr) AccessChain 27(data) 29 51 30
107: 6(int) Load 106
108: 6(int) GroupNonUniformIAdd 34 Reduce 107
109: 105(ptr) AccessChain 27(data) 104 51 30
Store 109 108
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
110: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
113: 112(ptr) AccessChain 27(data) 38 51
114: 21(ivec4) Load 113
115: 111(ivec2) VectorShuffle 114 114 0 1
116: 111(ivec2) GroupNonUniformIAdd 34 Reduce 115
117: 105(ptr) AccessChain 27(data) 110 51 30
118: 6(int) CompositeExtract 116 0
Store 117 118
119: 105(ptr) AccessChain 27(data) 110 51 47
120: 6(int) CompositeExtract 116 1
Store 119 120
121: 6(int) Load 8(invocation)
123: 112(ptr) AccessChain 27(data) 51 51
124: 21(ivec4) Load 123
125: 122(ivec3) VectorShuffle 124 124 0 1 2
126: 122(ivec3) GroupNonUniformIAdd 34 Reduce 125
127: 105(ptr) AccessChain 27(data) 121 51 30
128: 6(int) CompositeExtract 126 0
Store 127 128
129: 105(ptr) AccessChain 27(data) 121 51 47
130: 6(int) CompositeExtract 126 1
Store 129 130
131: 105(ptr) AccessChain 27(data) 121 51 61
132: 6(int) CompositeExtract 126 2
Store 131 132
133: 6(int) Load 8(invocation)
134: 112(ptr) AccessChain 27(data) 65 51
135: 21(ivec4) Load 134
136: 21(ivec4) GroupNonUniformIAdd 34 Reduce 135
137: 112(ptr) AccessChain 27(data) 133 51
Store 137 136
138: 6(int) Load 8(invocation)
140: 139(ptr) AccessChain 27(data) 29 65 30
141:22(float64_t) Load 140
142:22(float64_t) GroupNonUniformFAdd 34 Reduce 141
143: 139(ptr) AccessChain 27(data) 138 65 30
Store 143 142
144: 6(int) Load 8(invocation)
147: 146(ptr) AccessChain 27(data) 38 65
148: 23(f64vec4) Load 147
149:145(f64vec2) VectorShuffle 148 148 0 1
150:145(f64vec2) GroupNonUniformFAdd 34 Reduce 149
151: 139(ptr) AccessChain 27(data) 144 65 30
152:22(float64_t) CompositeExtract 150 0
Store 151 152
153: 139(ptr) AccessChain 27(data) 144 65 47
154:22(float64_t) CompositeExtract 150 1
Store 153 154
155: 6(int) Load 8(invocation)
157: 146(ptr) AccessChain 27(data) 51 65
158: 23(f64vec4) Load 157
159:156(f64vec3) VectorShuffle 158 158 0 1 2
160:156(f64vec3) GroupNonUniformFAdd 34 Reduce 159
161: 139(ptr) AccessChain 27(data) 155 65 30
162:22(float64_t) CompositeExtract 160 0
Store 161 162
163: 139(ptr) AccessChain 27(data) 155 65 47
164:22(float64_t) CompositeExtract 160 1
Store 163 164
165: 139(ptr) AccessChain 27(data) 155 65 61
166:22(float64_t) CompositeExtract 160 2
Store 165 166
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
167: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
168: 146(ptr) AccessChain 27(data) 65 65
169: 23(f64vec4) Load 168
170: 23(f64vec4) GroupNonUniformFAdd 34 Reduce 169
171: 146(ptr) AccessChain 27(data) 167 65
Store 171 170
172: 6(int) Load 8(invocation)
173: 31(ptr) AccessChain 27(data) 29 29 30
174: 17(float) Load 173
175: 17(float) GroupNonUniformFMul 34 Reduce 174
176: 31(ptr) AccessChain 27(data) 172 29 30
Store 176 175
177: 6(int) Load 8(invocation)
178: 40(ptr) AccessChain 27(data) 38 29
179: 18(fvec4) Load 178
180: 39(fvec2) VectorShuffle 179 179 0 1
181: 39(fvec2) GroupNonUniformFMul 34 Reduce 180
182: 31(ptr) AccessChain 27(data) 177 29 30
183: 17(float) CompositeExtract 181 0
Store 182 183
184: 31(ptr) AccessChain 27(data) 177 29 47
185: 17(float) CompositeExtract 181 1
Store 184 185
186: 6(int) Load 8(invocation)
187: 40(ptr) AccessChain 27(data) 51 29
188: 18(fvec4) Load 187
189: 52(fvec3) VectorShuffle 188 188 0 1 2
190: 52(fvec3) GroupNonUniformFMul 34 Reduce 189
191: 31(ptr) AccessChain 27(data) 186 29 30
192: 17(float) CompositeExtract 190 0
Store 191 192
193: 31(ptr) AccessChain 27(data) 186 29 47
194: 17(float) CompositeExtract 190 1
Store 193 194
195: 31(ptr) AccessChain 27(data) 186 29 61
196: 17(float) CompositeExtract 190 2
Store 195 196
197: 6(int) Load 8(invocation)
198: 40(ptr) AccessChain 27(data) 65 29
199: 18(fvec4) Load 198
200: 18(fvec4) GroupNonUniformFMul 34 Reduce 199
201: 40(ptr) AccessChain 27(data) 197 29
Store 201 200
202: 6(int) Load 8(invocation)
203: 71(ptr) AccessChain 27(data) 29 38 30
204: 19(int) Load 203
205: 19(int) GroupNonUniformIMul 34 Reduce 204
206: 71(ptr) AccessChain 27(data) 202 38 30
Store 206 205
207: 6(int) Load 8(invocation)
208: 78(ptr) AccessChain 27(data) 38 38
209: 20(ivec4) Load 208
210: 77(ivec2) VectorShuffle 209 209 0 1
211: 77(ivec2) GroupNonUniformIMul 34 Reduce 210
212: 71(ptr) AccessChain 27(data) 207 38 30
213: 19(int) CompositeExtract 211 0
Store 212 213
214: 71(ptr) AccessChain 27(data) 207 38 47
215: 19(int) CompositeExtract 211 1
Store 214 215
216: 6(int) Load 8(invocation)
217: 78(ptr) AccessChain 27(data) 51 38
218: 20(ivec4) Load 217
219: 88(ivec3) VectorShuffle 218 218 0 1 2
220: 88(ivec3) GroupNonUniformIMul 34 Reduce 219
221: 71(ptr) AccessChain 27(data) 216 38 30
222: 19(int) CompositeExtract 220 0
Store 221 222
223: 71(ptr) AccessChain 27(data) 216 38 47
224: 19(int) CompositeExtract 220 1
Store 223 224
225: 71(ptr) AccessChain 27(data) 216 38 61
226: 19(int) CompositeExtract 220 2
Store 225 226
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
227: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
228: 78(ptr) AccessChain 27(data) 65 38
229: 20(ivec4) Load 228
230: 20(ivec4) GroupNonUniformIMul 34 Reduce 229
231: 78(ptr) AccessChain 27(data) 227 38
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Store 231 230
232: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
233: 105(ptr) AccessChain 27(data) 29 51 30
234: 6(int) Load 233
235: 6(int) GroupNonUniformIMul 34 Reduce 234
236: 105(ptr) AccessChain 27(data) 232 51 30
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Store 236 235
237: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
238: 112(ptr) AccessChain 27(data) 38 51
239: 21(ivec4) Load 238
240: 111(ivec2) VectorShuffle 239 239 0 1
241: 111(ivec2) GroupNonUniformIMul 34 Reduce 240
242: 105(ptr) AccessChain 27(data) 237 51 30
243: 6(int) CompositeExtract 241 0
Store 242 243
244: 105(ptr) AccessChain 27(data) 237 51 47
245: 6(int) CompositeExtract 241 1
Store 244 245
246: 6(int) Load 8(invocation)
247: 112(ptr) AccessChain 27(data) 51 51
248: 21(ivec4) Load 247
249: 122(ivec3) VectorShuffle 248 248 0 1 2
250: 122(ivec3) GroupNonUniformIMul 34 Reduce 249
251: 105(ptr) AccessChain 27(data) 246 51 30
252: 6(int) CompositeExtract 250 0
Store 251 252
253: 105(ptr) AccessChain 27(data) 246 51 47
254: 6(int) CompositeExtract 250 1
Store 253 254
255: 105(ptr) AccessChain 27(data) 246 51 61
256: 6(int) CompositeExtract 250 2
Store 255 256
257: 6(int) Load 8(invocation)
258: 112(ptr) AccessChain 27(data) 65 51
259: 21(ivec4) Load 258
260: 21(ivec4) GroupNonUniformIMul 34 Reduce 259
261: 112(ptr) AccessChain 27(data) 257 51
Store 261 260
262: 6(int) Load 8(invocation)
263: 139(ptr) AccessChain 27(data) 29 65 30
264:22(float64_t) Load 263
265:22(float64_t) GroupNonUniformFMul 34 Reduce 264
266: 139(ptr) AccessChain 27(data) 262 65 30
Store 266 265
267: 6(int) Load 8(invocation)
268: 146(ptr) AccessChain 27(data) 38 65
269: 23(f64vec4) Load 268
270:145(f64vec2) VectorShuffle 269 269 0 1
271:145(f64vec2) GroupNonUniformFMul 34 Reduce 270
272: 139(ptr) AccessChain 27(data) 267 65 30
273:22(float64_t) CompositeExtract 271 0
Store 272 273
274: 139(ptr) AccessChain 27(data) 267 65 47
275:22(float64_t) CompositeExtract 271 1
Store 274 275
276: 6(int) Load 8(invocation)
277: 146(ptr) AccessChain 27(data) 51 65
278: 23(f64vec4) Load 277
279:156(f64vec3) VectorShuffle 278 278 0 1 2
280:156(f64vec3) GroupNonUniformFMul 34 Reduce 279
281: 139(ptr) AccessChain 27(data) 276 65 30
282:22(float64_t) CompositeExtract 280 0
Store 281 282
283: 139(ptr) AccessChain 27(data) 276 65 47
284:22(float64_t) CompositeExtract 280 1
Store 283 284
285: 139(ptr) AccessChain 27(data) 276 65 61
286:22(float64_t) CompositeExtract 280 2
Store 285 286
287: 6(int) Load 8(invocation)
288: 146(ptr) AccessChain 27(data) 65 65
289: 23(f64vec4) Load 288
290: 23(f64vec4) GroupNonUniformFMul 34 Reduce 289
291: 146(ptr) AccessChain 27(data) 287 65
Store 291 290
292: 6(int) Load 8(invocation)
293: 31(ptr) AccessChain 27(data) 29 29 30
294: 17(float) Load 293
295: 17(float) GroupNonUniformFMin 34 Reduce 294
296: 31(ptr) AccessChain 27(data) 292 29 30
Store 296 295
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
297: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
298: 40(ptr) AccessChain 27(data) 38 29
299: 18(fvec4) Load 298
300: 39(fvec2) VectorShuffle 299 299 0 1
301: 39(fvec2) GroupNonUniformFMin 34 Reduce 300
302: 31(ptr) AccessChain 27(data) 297 29 30
303: 17(float) CompositeExtract 301 0
Store 302 303
304: 31(ptr) AccessChain 27(data) 297 29 47
305: 17(float) CompositeExtract 301 1
Store 304 305
306: 6(int) Load 8(invocation)
307: 40(ptr) AccessChain 27(data) 51 29
308: 18(fvec4) Load 307
309: 52(fvec3) VectorShuffle 308 308 0 1 2
310: 52(fvec3) GroupNonUniformFMin 34 Reduce 309
311: 31(ptr) AccessChain 27(data) 306 29 30
312: 17(float) CompositeExtract 310 0
Store 311 312
313: 31(ptr) AccessChain 27(data) 306 29 47
314: 17(float) CompositeExtract 310 1
Store 313 314
315: 31(ptr) AccessChain 27(data) 306 29 61
316: 17(float) CompositeExtract 310 2
Store 315 316
317: 6(int) Load 8(invocation)
318: 40(ptr) AccessChain 27(data) 65 29
319: 18(fvec4) Load 318
320: 18(fvec4) GroupNonUniformFMin 34 Reduce 319
321: 40(ptr) AccessChain 27(data) 317 29
Store 321 320
322: 6(int) Load 8(invocation)
323: 71(ptr) AccessChain 27(data) 29 38 30
324: 19(int) Load 323
325: 19(int) GroupNonUniformSMin 34 Reduce 324
326: 71(ptr) AccessChain 27(data) 322 38 30
Store 326 325
327: 6(int) Load 8(invocation)
328: 78(ptr) AccessChain 27(data) 38 38
329: 20(ivec4) Load 328
330: 77(ivec2) VectorShuffle 329 329 0 1
331: 77(ivec2) GroupNonUniformSMin 34 Reduce 330
332: 71(ptr) AccessChain 27(data) 327 38 30
333: 19(int) CompositeExtract 331 0
Store 332 333
334: 71(ptr) AccessChain 27(data) 327 38 47
335: 19(int) CompositeExtract 331 1
Store 334 335
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
336: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
337: 78(ptr) AccessChain 27(data) 51 38
338: 20(ivec4) Load 337
339: 88(ivec3) VectorShuffle 338 338 0 1 2
340: 88(ivec3) GroupNonUniformSMin 34 Reduce 339
341: 71(ptr) AccessChain 27(data) 336 38 30
342: 19(int) CompositeExtract 340 0
Store 341 342
343: 71(ptr) AccessChain 27(data) 336 38 47
344: 19(int) CompositeExtract 340 1
Store 343 344
345: 71(ptr) AccessChain 27(data) 336 38 61
346: 19(int) CompositeExtract 340 2
Store 345 346
347: 6(int) Load 8(invocation)
348: 78(ptr) AccessChain 27(data) 65 38
349: 20(ivec4) Load 348
350: 20(ivec4) GroupNonUniformSMin 34 Reduce 349
351: 78(ptr) AccessChain 27(data) 347 38
Store 351 350
352: 6(int) Load 8(invocation)
353: 105(ptr) AccessChain 27(data) 29 51 30
354: 6(int) Load 353
355: 6(int) GroupNonUniformUMin 34 Reduce 354
356: 105(ptr) AccessChain 27(data) 352 51 30
Store 356 355
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
357: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
358: 112(ptr) AccessChain 27(data) 38 51
359: 21(ivec4) Load 358
360: 111(ivec2) VectorShuffle 359 359 0 1
361: 111(ivec2) GroupNonUniformUMin 34 Reduce 360
362: 105(ptr) AccessChain 27(data) 357 51 30
363: 6(int) CompositeExtract 361 0
Store 362 363
364: 105(ptr) AccessChain 27(data) 357 51 47
365: 6(int) CompositeExtract 361 1
Store 364 365
366: 6(int) Load 8(invocation)
367: 112(ptr) AccessChain 27(data) 51 51
368: 21(ivec4) Load 367
369: 122(ivec3) VectorShuffle 368 368 0 1 2
370: 122(ivec3) GroupNonUniformUMin 34 Reduce 369
371: 105(ptr) AccessChain 27(data) 366 51 30
372: 6(int) CompositeExtract 370 0
Store 371 372
373: 105(ptr) AccessChain 27(data) 366 51 47
374: 6(int) CompositeExtract 370 1
Store 373 374
375: 105(ptr) AccessChain 27(data) 366 51 61
376: 6(int) CompositeExtract 370 2
Store 375 376
377: 6(int) Load 8(invocation)
378: 112(ptr) AccessChain 27(data) 65 51
379: 21(ivec4) Load 378
380: 21(ivec4) GroupNonUniformUMin 34 Reduce 379
381: 112(ptr) AccessChain 27(data) 377 51
Store 381 380
382: 6(int) Load 8(invocation)
383: 139(ptr) AccessChain 27(data) 29 65 30
384:22(float64_t) Load 383
385:22(float64_t) GroupNonUniformFMin 34 Reduce 384
386: 139(ptr) AccessChain 27(data) 382 65 30
Store 386 385
387: 6(int) Load 8(invocation)
388: 146(ptr) AccessChain 27(data) 38 65
389: 23(f64vec4) Load 388
390:145(f64vec2) VectorShuffle 389 389 0 1
391:145(f64vec2) GroupNonUniformFMin 34 Reduce 390
392: 139(ptr) AccessChain 27(data) 387 65 30
393:22(float64_t) CompositeExtract 391 0
Store 392 393
394: 139(ptr) AccessChain 27(data) 387 65 47
395:22(float64_t) CompositeExtract 391 1
Store 394 395
396: 6(int) Load 8(invocation)
397: 146(ptr) AccessChain 27(data) 51 65
398: 23(f64vec4) Load 397
399:156(f64vec3) VectorShuffle 398 398 0 1 2
400:156(f64vec3) GroupNonUniformFMin 34 Reduce 399
401: 139(ptr) AccessChain 27(data) 396 65 30
402:22(float64_t) CompositeExtract 400 0
Store 401 402
403: 139(ptr) AccessChain 27(data) 396 65 47
404:22(float64_t) CompositeExtract 400 1
Store 403 404
405: 139(ptr) AccessChain 27(data) 396 65 61
406:22(float64_t) CompositeExtract 400 2
Store 405 406
407: 6(int) Load 8(invocation)
408: 146(ptr) AccessChain 27(data) 65 65
409: 23(f64vec4) Load 408
410: 23(f64vec4) GroupNonUniformFMin 34 Reduce 409
411: 146(ptr) AccessChain 27(data) 407 65
Store 411 410
412: 6(int) Load 8(invocation)
413: 31(ptr) AccessChain 27(data) 29 29 30
414: 17(float) Load 413
415: 17(float) GroupNonUniformFMax 34 Reduce 414
416: 31(ptr) AccessChain 27(data) 412 29 30
Store 416 415
417: 6(int) Load 8(invocation)
418: 40(ptr) AccessChain 27(data) 38 29
419: 18(fvec4) Load 418
420: 39(fvec2) VectorShuffle 419 419 0 1
421: 39(fvec2) GroupNonUniformFMax 34 Reduce 420
422: 31(ptr) AccessChain 27(data) 417 29 30
423: 17(float) CompositeExtract 421 0
Store 422 423
424: 31(ptr) AccessChain 27(data) 417 29 47
425: 17(float) CompositeExtract 421 1
Store 424 425
426: 6(int) Load 8(invocation)
427: 40(ptr) AccessChain 27(data) 51 29
428: 18(fvec4) Load 427
429: 52(fvec3) VectorShuffle 428 428 0 1 2
430: 52(fvec3) GroupNonUniformFMax 34 Reduce 429
431: 31(ptr) AccessChain 27(data) 426 29 30
432: 17(float) CompositeExtract 430 0
Store 431 432
433: 31(ptr) AccessChain 27(data) 426 29 47
434: 17(float) CompositeExtract 430 1
Store 433 434
435: 31(ptr) AccessChain 27(data) 426 29 61
436: 17(float) CompositeExtract 430 2
Store 435 436
437: 6(int) Load 8(invocation)
438: 40(ptr) AccessChain 27(data) 65 29
439: 18(fvec4) Load 438
440: 18(fvec4) GroupNonUniformFMax 34 Reduce 439
441: 40(ptr) AccessChain 27(data) 437 29
Store 441 440
442: 6(int) Load 8(invocation)
443: 71(ptr) AccessChain 27(data) 29 38 30
444: 19(int) Load 443
445: 19(int) GroupNonUniformSMax 34 Reduce 444
446: 71(ptr) AccessChain 27(data) 442 38 30
Store 446 445
447: 6(int) Load 8(invocation)
448: 78(ptr) AccessChain 27(data) 38 38
449: 20(ivec4) Load 448
450: 77(ivec2) VectorShuffle 449 449 0 1
451: 77(ivec2) GroupNonUniformSMax 34 Reduce 450
452: 71(ptr) AccessChain 27(data) 447 38 30
453: 19(int) CompositeExtract 451 0
Store 452 453
454: 71(ptr) AccessChain 27(data) 447 38 47
455: 19(int) CompositeExtract 451 1
Store 454 455
456: 6(int) Load 8(invocation)
457: 78(ptr) AccessChain 27(data) 51 38
458: 20(ivec4) Load 457
459: 88(ivec3) VectorShuffle 458 458 0 1 2
460: 88(ivec3) GroupNonUniformSMax 34 Reduce 459
461: 71(ptr) AccessChain 27(data) 456 38 30
462: 19(int) CompositeExtract 460 0
Store 461 462
463: 71(ptr) AccessChain 27(data) 456 38 47
464: 19(int) CompositeExtract 460 1
Store 463 464
465: 71(ptr) AccessChain 27(data) 456 38 61
466: 19(int) CompositeExtract 460 2
Store 465 466
467: 6(int) Load 8(invocation)
468: 78(ptr) AccessChain 27(data) 65 38
469: 20(ivec4) Load 468
470: 20(ivec4) GroupNonUniformSMax 34 Reduce 469
471: 78(ptr) AccessChain 27(data) 467 38
Store 471 470
472: 6(int) Load 8(invocation)
473: 105(ptr) AccessChain 27(data) 29 51 30
474: 6(int) Load 473
475: 6(int) GroupNonUniformUMax 34 Reduce 474
476: 105(ptr) AccessChain 27(data) 472 51 30
Store 476 475
477: 6(int) Load 8(invocation)
478: 112(ptr) AccessChain 27(data) 38 51
479: 21(ivec4) Load 478
480: 111(ivec2) VectorShuffle 479 479 0 1
481: 111(ivec2) GroupNonUniformUMax 34 Reduce 480
482: 105(ptr) AccessChain 27(data) 477 51 30
483: 6(int) CompositeExtract 481 0
Store 482 483
484: 105(ptr) AccessChain 27(data) 477 51 47
485: 6(int) CompositeExtract 481 1
Store 484 485
486: 6(int) Load 8(invocation)
487: 112(ptr) AccessChain 27(data) 51 51
488: 21(ivec4) Load 487
489: 122(ivec3) VectorShuffle 488 488 0 1 2
490: 122(ivec3) GroupNonUniformUMax 34 Reduce 489
491: 105(ptr) AccessChain 27(data) 486 51 30
492: 6(int) CompositeExtract 490 0
Store 491 492
493: 105(ptr) AccessChain 27(data) 486 51 47
494: 6(int) CompositeExtract 490 1
Store 493 494
495: 105(ptr) AccessChain 27(data) 486 51 61
496: 6(int) CompositeExtract 490 2
Store 495 496
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
497: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
498: 112(ptr) AccessChain 27(data) 65 51
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
499: 21(ivec4) Load 498
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
500: 21(ivec4) GroupNonUniformUMax 34 Reduce 499
501: 112(ptr) AccessChain 27(data) 497 51
Store 501 500
502: 6(int) Load 8(invocation)
503: 139(ptr) AccessChain 27(data) 29 65 30
504:22(float64_t) Load 503
505:22(float64_t) GroupNonUniformFMax 34 Reduce 504
506: 139(ptr) AccessChain 27(data) 502 65 30
Store 506 505
507: 6(int) Load 8(invocation)
508: 146(ptr) AccessChain 27(data) 38 65
509: 23(f64vec4) Load 508
510:145(f64vec2) VectorShuffle 509 509 0 1
511:145(f64vec2) GroupNonUniformFMax 34 Reduce 510
512: 139(ptr) AccessChain 27(data) 507 65 30
513:22(float64_t) CompositeExtract 511 0
Store 512 513
514: 139(ptr) AccessChain 27(data) 507 65 47
515:22(float64_t) CompositeExtract 511 1
Store 514 515
516: 6(int) Load 8(invocation)
517: 146(ptr) AccessChain 27(data) 51 65
518: 23(f64vec4) Load 517
519:156(f64vec3) VectorShuffle 518 518 0 1 2
520:156(f64vec3) GroupNonUniformFMax 34 Reduce 519
521: 139(ptr) AccessChain 27(data) 516 65 30
522:22(float64_t) CompositeExtract 520 0
Store 521 522
523: 139(ptr) AccessChain 27(data) 516 65 47
524:22(float64_t) CompositeExtract 520 1
Store 523 524
525: 139(ptr) AccessChain 27(data) 516 65 61
526:22(float64_t) CompositeExtract 520 2
Store 525 526
527: 6(int) Load 8(invocation)
528: 146(ptr) AccessChain 27(data) 65 65
529: 23(f64vec4) Load 528
530: 23(f64vec4) GroupNonUniformFMax 34 Reduce 529
531: 146(ptr) AccessChain 27(data) 527 65
Store 531 530
532: 6(int) Load 8(invocation)
533: 71(ptr) AccessChain 27(data) 29 38 30
534: 19(int) Load 533
535: 19(int) GroupNonUniformBitwiseAnd 34 Reduce 534
536: 71(ptr) AccessChain 27(data) 532 38 30
Store 536 535
537: 6(int) Load 8(invocation)
538: 78(ptr) AccessChain 27(data) 38 38
539: 20(ivec4) Load 538
540: 77(ivec2) VectorShuffle 539 539 0 1
541: 77(ivec2) GroupNonUniformBitwiseAnd 34 Reduce 540
542: 71(ptr) AccessChain 27(data) 537 38 30
543: 19(int) CompositeExtract 541 0
Store 542 543
544: 71(ptr) AccessChain 27(data) 537 38 47
545: 19(int) CompositeExtract 541 1
Store 544 545
546: 6(int) Load 8(invocation)
547: 78(ptr) AccessChain 27(data) 51 38
548: 20(ivec4) Load 547
549: 88(ivec3) VectorShuffle 548 548 0 1 2
550: 88(ivec3) GroupNonUniformBitwiseAnd 34 Reduce 549
551: 71(ptr) AccessChain 27(data) 546 38 30
552: 19(int) CompositeExtract 550 0
Store 551 552
553: 71(ptr) AccessChain 27(data) 546 38 47
554: 19(int) CompositeExtract 550 1
Store 553 554
555: 71(ptr) AccessChain 27(data) 546 38 61
556: 19(int) CompositeExtract 550 2
Store 555 556
557: 6(int) Load 8(invocation)
558: 78(ptr) AccessChain 27(data) 65 38
559: 20(ivec4) Load 558
560: 20(ivec4) GroupNonUniformBitwiseAnd 34 Reduce 559
561: 78(ptr) AccessChain 27(data) 557 38
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Store 561 560
562: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
563: 105(ptr) AccessChain 27(data) 29 51 30
564: 6(int) Load 563
565: 6(int) GroupNonUniformBitwiseAnd 34 Reduce 564
566: 105(ptr) AccessChain 27(data) 562 51 30
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Store 566 565
567: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
568: 112(ptr) AccessChain 27(data) 38 51
569: 21(ivec4) Load 568
570: 111(ivec2) VectorShuffle 569 569 0 1
571: 111(ivec2) GroupNonUniformBitwiseAnd 34 Reduce 570
572: 105(ptr) AccessChain 27(data) 567 51 30
573: 6(int) CompositeExtract 571 0
Store 572 573
574: 105(ptr) AccessChain 27(data) 567 51 47
575: 6(int) CompositeExtract 571 1
Store 574 575
576: 6(int) Load 8(invocation)
577: 112(ptr) AccessChain 27(data) 51 51
578: 21(ivec4) Load 577
579: 122(ivec3) VectorShuffle 578 578 0 1 2
580: 122(ivec3) GroupNonUniformBitwiseAnd 34 Reduce 579
581: 105(ptr) AccessChain 27(data) 576 51 30
582: 6(int) CompositeExtract 580 0
Store 581 582
583: 105(ptr) AccessChain 27(data) 576 51 47
584: 6(int) CompositeExtract 580 1
Store 583 584
585: 105(ptr) AccessChain 27(data) 576 51 61
586: 6(int) CompositeExtract 580 2
Store 585 586
587: 6(int) Load 8(invocation)
588: 112(ptr) AccessChain 27(data) 65 51
589: 21(ivec4) Load 588
590: 21(ivec4) GroupNonUniformBitwiseAnd 34 Reduce 589
591: 112(ptr) AccessChain 27(data) 587 51
Store 591 590
592: 6(int) Load 8(invocation)
593: 71(ptr) AccessChain 27(data) 29 38 30
594: 19(int) Load 593
596: 595(bool) SLessThan 594 29
597: 595(bool) GroupNonUniformLogicalAnd 34 Reduce 596
598: 19(int) Select 597 38 29
599: 71(ptr) AccessChain 27(data) 592 38 30
Store 599 598
600: 6(int) Load 8(invocation)
601: 78(ptr) AccessChain 27(data) 38 38
602: 20(ivec4) Load 601
603: 77(ivec2) VectorShuffle 602 602 0 1
606: 605(bvec2) SLessThan 603 604
607: 605(bvec2) GroupNonUniformLogicalAnd 34 Reduce 606
609: 77(ivec2) Select 607 608 604
610: 71(ptr) AccessChain 27(data) 600 38 30
611: 19(int) CompositeExtract 609 0
Store 610 611
612: 71(ptr) AccessChain 27(data) 600 38 47
613: 19(int) CompositeExtract 609 1
Store 612 613
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
614: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
615: 78(ptr) AccessChain 27(data) 38 38
616: 20(ivec4) Load 615
617: 88(ivec3) VectorShuffle 616 616 0 1 2
620: 619(bvec3) SLessThan 617 618
621: 619(bvec3) GroupNonUniformLogicalAnd 34 Reduce 620
623: 88(ivec3) Select 621 622 618
624: 71(ptr) AccessChain 27(data) 614 38 30
625: 19(int) CompositeExtract 623 0
Store 624 625
626: 71(ptr) AccessChain 27(data) 614 38 47
627: 19(int) CompositeExtract 623 1
Store 626 627
628: 71(ptr) AccessChain 27(data) 614 38 61
629: 19(int) CompositeExtract 623 2
Store 628 629
630: 6(int) Load 8(invocation)
631: 78(ptr) AccessChain 27(data) 38 38
632: 20(ivec4) Load 631
635: 634(bvec4) SLessThan 632 633
636: 634(bvec4) GroupNonUniformLogicalAnd 34 Reduce 635
638: 20(ivec4) Select 636 637 633
639: 78(ptr) AccessChain 27(data) 630 38
Store 639 638
640: 6(int) Load 8(invocation)
641: 71(ptr) AccessChain 27(data) 29 38 30
642: 19(int) Load 641
643: 19(int) GroupNonUniformBitwiseOr 34 Reduce 642
644: 71(ptr) AccessChain 27(data) 640 38 30
Store 644 643
645: 6(int) Load 8(invocation)
646: 78(ptr) AccessChain 27(data) 38 38
647: 20(ivec4) Load 646
648: 77(ivec2) VectorShuffle 647 647 0 1
649: 77(ivec2) GroupNonUniformBitwiseOr 34 Reduce 648
650: 71(ptr) AccessChain 27(data) 645 38 30
651: 19(int) CompositeExtract 649 0
Store 650 651
652: 71(ptr) AccessChain 27(data) 645 38 47
653: 19(int) CompositeExtract 649 1
Store 652 653
654: 6(int) Load 8(invocation)
655: 78(ptr) AccessChain 27(data) 51 38
656: 20(ivec4) Load 655
657: 88(ivec3) VectorShuffle 656 656 0 1 2
658: 88(ivec3) GroupNonUniformBitwiseOr 34 Reduce 657
659: 71(ptr) AccessChain 27(data) 654 38 30
660: 19(int) CompositeExtract 658 0
Store 659 660
661: 71(ptr) AccessChain 27(data) 654 38 47
662: 19(int) CompositeExtract 658 1
Store 661 662
663: 71(ptr) AccessChain 27(data) 654 38 61
664: 19(int) CompositeExtract 658 2
Store 663 664
665: 6(int) Load 8(invocation)
666: 78(ptr) AccessChain 27(data) 65 38
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
667: 20(ivec4) Load 666
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
668: 20(ivec4) GroupNonUniformBitwiseOr 34 Reduce 667
669: 78(ptr) AccessChain 27(data) 665 38
Store 669 668
670: 6(int) Load 8(invocation)
671: 105(ptr) AccessChain 27(data) 29 51 30
672: 6(int) Load 671
673: 6(int) GroupNonUniformBitwiseOr 34 Reduce 672
674: 105(ptr) AccessChain 27(data) 670 51 30
Store 674 673
675: 6(int) Load 8(invocation)
676: 112(ptr) AccessChain 27(data) 38 51
677: 21(ivec4) Load 676
678: 111(ivec2) VectorShuffle 677 677 0 1
679: 111(ivec2) GroupNonUniformBitwiseOr 34 Reduce 678
680: 105(ptr) AccessChain 27(data) 675 51 30
681: 6(int) CompositeExtract 679 0
Store 680 681
682: 105(ptr) AccessChain 27(data) 675 51 47
683: 6(int) CompositeExtract 679 1
Store 682 683
684: 6(int) Load 8(invocation)
685: 112(ptr) AccessChain 27(data) 51 51
686: 21(ivec4) Load 685
687: 122(ivec3) VectorShuffle 686 686 0 1 2
688: 122(ivec3) GroupNonUniformBitwiseOr 34 Reduce 687
689: 105(ptr) AccessChain 27(data) 684 51 30
690: 6(int) CompositeExtract 688 0
Store 689 690
691: 105(ptr) AccessChain 27(data) 684 51 47
692: 6(int) CompositeExtract 688 1
Store 691 692
693: 105(ptr) AccessChain 27(data) 684 51 61
694: 6(int) CompositeExtract 688 2
Store 693 694
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
695: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
696: 112(ptr) AccessChain 27(data) 65 51
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
697: 21(ivec4) Load 696
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
698: 21(ivec4) GroupNonUniformBitwiseOr 34 Reduce 697
699: 112(ptr) AccessChain 27(data) 695 51
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Store 699 698
700: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
701: 71(ptr) AccessChain 27(data) 29 38 30
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
702: 19(int) Load 701
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
703: 595(bool) SLessThan 702 29
704: 595(bool) GroupNonUniformLogicalOr 34 Reduce 703
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
705: 19(int) Select 704 38 29
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
706: 71(ptr) AccessChain 27(data) 700 38 30
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Store 706 705
707: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
708: 78(ptr) AccessChain 27(data) 38 38
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
709: 20(ivec4) Load 708
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
710: 77(ivec2) VectorShuffle 709 709 0 1
711: 605(bvec2) SLessThan 710 604
712: 605(bvec2) GroupNonUniformLogicalOr 34 Reduce 711
713: 77(ivec2) Select 712 608 604
714: 71(ptr) AccessChain 27(data) 707 38 30
715: 19(int) CompositeExtract 713 0
Store 714 715
716: 71(ptr) AccessChain 27(data) 707 38 47
717: 19(int) CompositeExtract 713 1
Store 716 717
718: 6(int) Load 8(invocation)
719: 78(ptr) AccessChain 27(data) 38 38
720: 20(ivec4) Load 719
721: 88(ivec3) VectorShuffle 720 720 0 1 2
722: 619(bvec3) SLessThan 721 618
723: 619(bvec3) GroupNonUniformLogicalOr 34 Reduce 722
724: 88(ivec3) Select 723 622 618
725: 71(ptr) AccessChain 27(data) 718 38 30
726: 19(int) CompositeExtract 724 0
Store 725 726
727: 71(ptr) AccessChain 27(data) 718 38 47
728: 19(int) CompositeExtract 724 1
Store 727 728
729: 71(ptr) AccessChain 27(data) 718 38 61
730: 19(int) CompositeExtract 724 2
Store 729 730
731: 6(int) Load 8(invocation)
732: 78(ptr) AccessChain 27(data) 38 38
733: 20(ivec4) Load 732
734: 634(bvec4) SLessThan 733 633
735: 634(bvec4) GroupNonUniformLogicalOr 34 Reduce 734
736: 20(ivec4) Select 735 637 633
737: 78(ptr) AccessChain 27(data) 731 38
Store 737 736
738: 6(int) Load 8(invocation)
739: 71(ptr) AccessChain 27(data) 29 38 30
740: 19(int) Load 739
741: 19(int) GroupNonUniformBitwiseXor 34 Reduce 740
742: 71(ptr) AccessChain 27(data) 738 38 30
Store 742 741
743: 6(int) Load 8(invocation)
744: 78(ptr) AccessChain 27(data) 38 38
745: 20(ivec4) Load 744
746: 77(ivec2) VectorShuffle 745 745 0 1
747: 77(ivec2) GroupNonUniformBitwiseXor 34 Reduce 746
748: 71(ptr) AccessChain 27(data) 743 38 30
749: 19(int) CompositeExtract 747 0
Store 748 749
750: 71(ptr) AccessChain 27(data) 743 38 47
751: 19(int) CompositeExtract 747 1
Store 750 751
752: 6(int) Load 8(invocation)
753: 78(ptr) AccessChain 27(data) 51 38
754: 20(ivec4) Load 753
755: 88(ivec3) VectorShuffle 754 754 0 1 2
756: 88(ivec3) GroupNonUniformBitwiseXor 34 Reduce 755
757: 71(ptr) AccessChain 27(data) 752 38 30
758: 19(int) CompositeExtract 756 0
Store 757 758
759: 71(ptr) AccessChain 27(data) 752 38 47
760: 19(int) CompositeExtract 756 1
Store 759 760
761: 71(ptr) AccessChain 27(data) 752 38 61
762: 19(int) CompositeExtract 756 2
Store 761 762
763: 6(int) Load 8(invocation)
764: 78(ptr) AccessChain 27(data) 65 38
765: 20(ivec4) Load 764
766: 20(ivec4) GroupNonUniformBitwiseXor 34 Reduce 765
767: 78(ptr) AccessChain 27(data) 763 38
Store 767 766
768: 6(int) Load 8(invocation)
769: 105(ptr) AccessChain 27(data) 29 51 30
770: 6(int) Load 769
771: 6(int) GroupNonUniformBitwiseXor 34 Reduce 770
772: 105(ptr) AccessChain 27(data) 768 51 30
Store 772 771
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
773: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
774: 112(ptr) AccessChain 27(data) 38 51
775: 21(ivec4) Load 774
776: 111(ivec2) VectorShuffle 775 775 0 1
777: 111(ivec2) GroupNonUniformBitwiseXor 34 Reduce 776
778: 105(ptr) AccessChain 27(data) 773 51 30
779: 6(int) CompositeExtract 777 0
Store 778 779
780: 105(ptr) AccessChain 27(data) 773 51 47
781: 6(int) CompositeExtract 777 1
Store 780 781
782: 6(int) Load 8(invocation)
783: 112(ptr) AccessChain 27(data) 51 51
784: 21(ivec4) Load 783
785: 122(ivec3) VectorShuffle 784 784 0 1 2
786: 122(ivec3) GroupNonUniformBitwiseXor 34 Reduce 785
787: 105(ptr) AccessChain 27(data) 782 51 30
788: 6(int) CompositeExtract 786 0
Store 787 788
789: 105(ptr) AccessChain 27(data) 782 51 47
790: 6(int) CompositeExtract 786 1
Store 789 790
791: 105(ptr) AccessChain 27(data) 782 51 61
792: 6(int) CompositeExtract 786 2
Store 791 792
793: 6(int) Load 8(invocation)
794: 112(ptr) AccessChain 27(data) 65 51
795: 21(ivec4) Load 794
796: 21(ivec4) GroupNonUniformBitwiseXor 34 Reduce 795
797: 112(ptr) AccessChain 27(data) 793 51
Store 797 796
798: 6(int) Load 8(invocation)
799: 71(ptr) AccessChain 27(data) 29 38 30
800: 19(int) Load 799
801: 595(bool) SLessThan 800 29
802: 595(bool) GroupNonUniformLogicalXor 34 Reduce 801
803: 19(int) Select 802 38 29
804: 71(ptr) AccessChain 27(data) 798 38 30
Store 804 803
805: 6(int) Load 8(invocation)
806: 78(ptr) AccessChain 27(data) 38 38
807: 20(ivec4) Load 806
808: 77(ivec2) VectorShuffle 807 807 0 1
809: 605(bvec2) SLessThan 808 604
810: 605(bvec2) GroupNonUniformLogicalXor 34 Reduce 809
811: 77(ivec2) Select 810 608 604
812: 71(ptr) AccessChain 27(data) 805 38 30
813: 19(int) CompositeExtract 811 0
Store 812 813
814: 71(ptr) AccessChain 27(data) 805 38 47
815: 19(int) CompositeExtract 811 1
Store 814 815
816: 6(int) Load 8(invocation)
817: 78(ptr) AccessChain 27(data) 38 38
818: 20(ivec4) Load 817
819: 88(ivec3) VectorShuffle 818 818 0 1 2
820: 619(bvec3) SLessThan 819 618
821: 619(bvec3) GroupNonUniformLogicalXor 34 Reduce 820
822: 88(ivec3) Select 821 622 618
823: 71(ptr) AccessChain 27(data) 816 38 30
824: 19(int) CompositeExtract 822 0
Store 823 824
825: 71(ptr) AccessChain 27(data) 816 38 47
826: 19(int) CompositeExtract 822 1
Store 825 826
827: 71(ptr) AccessChain 27(data) 816 38 61
828: 19(int) CompositeExtract 822 2
Store 827 828
829: 6(int) Load 8(invocation)
830: 78(ptr) AccessChain 27(data) 38 38
831: 20(ivec4) Load 830
832: 634(bvec4) SLessThan 831 633
833: 634(bvec4) GroupNonUniformLogicalXor 34 Reduce 832
834: 20(ivec4) Select 833 637 633
835: 78(ptr) AccessChain 27(data) 829 38
Store 835 834
836: 6(int) Load 8(invocation)
837: 31(ptr) AccessChain 27(data) 29 29 30
838: 17(float) Load 837
839: 17(float) GroupNonUniformFAdd 34 InclusiveScan 838
840: 31(ptr) AccessChain 27(data) 836 29 30
Store 840 839
841: 6(int) Load 8(invocation)
842: 40(ptr) AccessChain 27(data) 38 29
843: 18(fvec4) Load 842
844: 39(fvec2) VectorShuffle 843 843 0 1
845: 39(fvec2) GroupNonUniformFAdd 34 InclusiveScan 844
846: 31(ptr) AccessChain 27(data) 841 29 30
847: 17(float) CompositeExtract 845 0
Store 846 847
848: 31(ptr) AccessChain 27(data) 841 29 47
849: 17(float) CompositeExtract 845 1
Store 848 849
850: 6(int) Load 8(invocation)
851: 40(ptr) AccessChain 27(data) 51 29
852: 18(fvec4) Load 851
853: 52(fvec3) VectorShuffle 852 852 0 1 2
854: 52(fvec3) GroupNonUniformFAdd 34 InclusiveScan 853
855: 31(ptr) AccessChain 27(data) 850 29 30
856: 17(float) CompositeExtract 854 0
Store 855 856
857: 31(ptr) AccessChain 27(data) 850 29 47
858: 17(float) CompositeExtract 854 1
Store 857 858
859: 31(ptr) AccessChain 27(data) 850 29 61
860: 17(float) CompositeExtract 854 2
Store 859 860
861: 6(int) Load 8(invocation)
862: 40(ptr) AccessChain 27(data) 65 29
863: 18(fvec4) Load 862
864: 18(fvec4) GroupNonUniformFAdd 34 InclusiveScan 863
865: 40(ptr) AccessChain 27(data) 861 29
Store 865 864
866: 6(int) Load 8(invocation)
867: 71(ptr) AccessChain 27(data) 29 38 30
868: 19(int) Load 867
869: 19(int) GroupNonUniformIAdd 34 InclusiveScan 868
870: 71(ptr) AccessChain 27(data) 866 38 30
Store 870 869
871: 6(int) Load 8(invocation)
872: 78(ptr) AccessChain 27(data) 38 38
873: 20(ivec4) Load 872
874: 77(ivec2) VectorShuffle 873 873 0 1
875: 77(ivec2) GroupNonUniformIAdd 34 InclusiveScan 874
876: 71(ptr) AccessChain 27(data) 871 38 30
877: 19(int) CompositeExtract 875 0
Store 876 877
878: 71(ptr) AccessChain 27(data) 871 38 47
879: 19(int) CompositeExtract 875 1
Store 878 879
880: 6(int) Load 8(invocation)
881: 78(ptr) AccessChain 27(data) 51 38
882: 20(ivec4) Load 881
883: 88(ivec3) VectorShuffle 882 882 0 1 2
884: 88(ivec3) GroupNonUniformIAdd 34 InclusiveScan 883
885: 71(ptr) AccessChain 27(data) 880 38 30
886: 19(int) CompositeExtract 884 0
Store 885 886
887: 71(ptr) AccessChain 27(data) 880 38 47
888: 19(int) CompositeExtract 884 1
Store 887 888
889: 71(ptr) AccessChain 27(data) 880 38 61
890: 19(int) CompositeExtract 884 2
Store 889 890
891: 6(int) Load 8(invocation)
892: 78(ptr) AccessChain 27(data) 65 38
893: 20(ivec4) Load 892
894: 20(ivec4) GroupNonUniformIAdd 34 InclusiveScan 893
895: 78(ptr) AccessChain 27(data) 891 38
Store 895 894
896: 6(int) Load 8(invocation)
897: 105(ptr) AccessChain 27(data) 29 51 30
898: 6(int) Load 897
899: 6(int) GroupNonUniformIAdd 34 InclusiveScan 898
900: 105(ptr) AccessChain 27(data) 896 51 30
Store 900 899
901: 6(int) Load 8(invocation)
902: 112(ptr) AccessChain 27(data) 38 51
903: 21(ivec4) Load 902
904: 111(ivec2) VectorShuffle 903 903 0 1
905: 111(ivec2) GroupNonUniformIAdd 34 InclusiveScan 904
906: 105(ptr) AccessChain 27(data) 901 51 30
907: 6(int) CompositeExtract 905 0
Store 906 907
908: 105(ptr) AccessChain 27(data) 901 51 47
909: 6(int) CompositeExtract 905 1
Store 908 909
910: 6(int) Load 8(invocation)
911: 112(ptr) AccessChain 27(data) 51 51
912: 21(ivec4) Load 911
913: 122(ivec3) VectorShuffle 912 912 0 1 2
914: 122(ivec3) GroupNonUniformIAdd 34 InclusiveScan 913
915: 105(ptr) AccessChain 27(data) 910 51 30
916: 6(int) CompositeExtract 914 0
Store 915 916
917: 105(ptr) AccessChain 27(data) 910 51 47
918: 6(int) CompositeExtract 914 1
Store 917 918
919: 105(ptr) AccessChain 27(data) 910 51 61
920: 6(int) CompositeExtract 914 2
Store 919 920
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
921: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
922: 112(ptr) AccessChain 27(data) 65 51
923: 21(ivec4) Load 922
924: 21(ivec4) GroupNonUniformIAdd 34 InclusiveScan 923
925: 112(ptr) AccessChain 27(data) 921 51
Store 925 924
926: 6(int) Load 8(invocation)
927: 139(ptr) AccessChain 27(data) 29 65 30
928:22(float64_t) Load 927
929:22(float64_t) GroupNonUniformFAdd 34 InclusiveScan 928
930: 139(ptr) AccessChain 27(data) 926 65 30
Store 930 929
931: 6(int) Load 8(invocation)
932: 146(ptr) AccessChain 27(data) 38 65
933: 23(f64vec4) Load 932
934:145(f64vec2) VectorShuffle 933 933 0 1
935:145(f64vec2) GroupNonUniformFAdd 34 InclusiveScan 934
936: 139(ptr) AccessChain 27(data) 931 65 30
937:22(float64_t) CompositeExtract 935 0
Store 936 937
938: 139(ptr) AccessChain 27(data) 931 65 47
939:22(float64_t) CompositeExtract 935 1
Store 938 939
940: 6(int) Load 8(invocation)
941: 146(ptr) AccessChain 27(data) 51 65
942: 23(f64vec4) Load 941
943:156(f64vec3) VectorShuffle 942 942 0 1 2
944:156(f64vec3) GroupNonUniformFAdd 34 InclusiveScan 943
945: 139(ptr) AccessChain 27(data) 940 65 30
946:22(float64_t) CompositeExtract 944 0
Store 945 946
947: 139(ptr) AccessChain 27(data) 940 65 47
948:22(float64_t) CompositeExtract 944 1
Store 947 948
949: 139(ptr) AccessChain 27(data) 940 65 61
950:22(float64_t) CompositeExtract 944 2
Store 949 950
951: 6(int) Load 8(invocation)
952: 146(ptr) AccessChain 27(data) 65 65
953: 23(f64vec4) Load 952
954: 23(f64vec4) GroupNonUniformFAdd 34 InclusiveScan 953
955: 146(ptr) AccessChain 27(data) 951 65
Store 955 954
956: 6(int) Load 8(invocation)
957: 31(ptr) AccessChain 27(data) 29 29 30
958: 17(float) Load 957
959: 17(float) GroupNonUniformFMul 34 InclusiveScan 958
960: 31(ptr) AccessChain 27(data) 956 29 30
Store 960 959
961: 6(int) Load 8(invocation)
962: 40(ptr) AccessChain 27(data) 38 29
963: 18(fvec4) Load 962
964: 39(fvec2) VectorShuffle 963 963 0 1
965: 39(fvec2) GroupNonUniformFMul 34 InclusiveScan 964
966: 31(ptr) AccessChain 27(data) 961 29 30
967: 17(float) CompositeExtract 965 0
Store 966 967
968: 31(ptr) AccessChain 27(data) 961 29 47
969: 17(float) CompositeExtract 965 1
Store 968 969
970: 6(int) Load 8(invocation)
971: 40(ptr) AccessChain 27(data) 51 29
972: 18(fvec4) Load 971
973: 52(fvec3) VectorShuffle 972 972 0 1 2
974: 52(fvec3) GroupNonUniformFMul 34 InclusiveScan 973
975: 31(ptr) AccessChain 27(data) 970 29 30
976: 17(float) CompositeExtract 974 0
Store 975 976
977: 31(ptr) AccessChain 27(data) 970 29 47
978: 17(float) CompositeExtract 974 1
Store 977 978
979: 31(ptr) AccessChain 27(data) 970 29 61
980: 17(float) CompositeExtract 974 2
Store 979 980
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
981: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
982: 40(ptr) AccessChain 27(data) 65 29
983: 18(fvec4) Load 982
984: 18(fvec4) GroupNonUniformFMul 34 InclusiveScan 983
985: 40(ptr) AccessChain 27(data) 981 29
Store 985 984
986: 6(int) Load 8(invocation)
987: 71(ptr) AccessChain 27(data) 29 38 30
988: 19(int) Load 987
989: 19(int) GroupNonUniformIMul 34 InclusiveScan 988
990: 71(ptr) AccessChain 27(data) 986 38 30
Store 990 989
991: 6(int) Load 8(invocation)
992: 78(ptr) AccessChain 27(data) 38 38
993: 20(ivec4) Load 992
994: 77(ivec2) VectorShuffle 993 993 0 1
995: 77(ivec2) GroupNonUniformIMul 34 InclusiveScan 994
996: 71(ptr) AccessChain 27(data) 991 38 30
997: 19(int) CompositeExtract 995 0
Store 996 997
998: 71(ptr) AccessChain 27(data) 991 38 47
999: 19(int) CompositeExtract 995 1
Store 998 999
1000: 6(int) Load 8(invocation)
1001: 78(ptr) AccessChain 27(data) 51 38
1002: 20(ivec4) Load 1001
1003: 88(ivec3) VectorShuffle 1002 1002 0 1 2
1004: 88(ivec3) GroupNonUniformIMul 34 InclusiveScan 1003
1005: 71(ptr) AccessChain 27(data) 1000 38 30
1006: 19(int) CompositeExtract 1004 0
Store 1005 1006
1007: 71(ptr) AccessChain 27(data) 1000 38 47
1008: 19(int) CompositeExtract 1004 1
Store 1007 1008
1009: 71(ptr) AccessChain 27(data) 1000 38 61
1010: 19(int) CompositeExtract 1004 2
Store 1009 1010
1011: 6(int) Load 8(invocation)
1012: 78(ptr) AccessChain 27(data) 65 38
1013: 20(ivec4) Load 1012
1014: 20(ivec4) GroupNonUniformIMul 34 InclusiveScan 1013
1015: 78(ptr) AccessChain 27(data) 1011 38
Store 1015 1014
1016: 6(int) Load 8(invocation)
1017: 105(ptr) AccessChain 27(data) 29 51 30
1018: 6(int) Load 1017
1019: 6(int) GroupNonUniformIMul 34 InclusiveScan 1018
1020: 105(ptr) AccessChain 27(data) 1016 51 30
Store 1020 1019
1021: 6(int) Load 8(invocation)
1022: 112(ptr) AccessChain 27(data) 38 51
1023: 21(ivec4) Load 1022
1024: 111(ivec2) VectorShuffle 1023 1023 0 1
1025: 111(ivec2) GroupNonUniformIMul 34 InclusiveScan 1024
1026: 105(ptr) AccessChain 27(data) 1021 51 30
1027: 6(int) CompositeExtract 1025 0
Store 1026 1027
1028: 105(ptr) AccessChain 27(data) 1021 51 47
1029: 6(int) CompositeExtract 1025 1
Store 1028 1029
1030: 6(int) Load 8(invocation)
1031: 112(ptr) AccessChain 27(data) 51 51
1032: 21(ivec4) Load 1031
1033: 122(ivec3) VectorShuffle 1032 1032 0 1 2
1034: 122(ivec3) GroupNonUniformIMul 34 InclusiveScan 1033
1035: 105(ptr) AccessChain 27(data) 1030 51 30
1036: 6(int) CompositeExtract 1034 0
Store 1035 1036
1037: 105(ptr) AccessChain 27(data) 1030 51 47
1038: 6(int) CompositeExtract 1034 1
Store 1037 1038
1039: 105(ptr) AccessChain 27(data) 1030 51 61
1040: 6(int) CompositeExtract 1034 2
Store 1039 1040
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
1041: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1042: 112(ptr) AccessChain 27(data) 65 51
1043: 21(ivec4) Load 1042
1044: 21(ivec4) GroupNonUniformIMul 34 InclusiveScan 1043
1045: 112(ptr) AccessChain 27(data) 1041 51
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Store 1045 1044
1046: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1047: 139(ptr) AccessChain 27(data) 29 65 30
1048:22(float64_t) Load 1047
1049:22(float64_t) GroupNonUniformFMul 34 InclusiveScan 1048
1050: 139(ptr) AccessChain 27(data) 1046 65 30
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Store 1050 1049
1051: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1052: 146(ptr) AccessChain 27(data) 38 65
1053: 23(f64vec4) Load 1052
1054:145(f64vec2) VectorShuffle 1053 1053 0 1
1055:145(f64vec2) GroupNonUniformFMul 34 InclusiveScan 1054
1056: 139(ptr) AccessChain 27(data) 1051 65 30
1057:22(float64_t) CompositeExtract 1055 0
Store 1056 1057
1058: 139(ptr) AccessChain 27(data) 1051 65 47
1059:22(float64_t) CompositeExtract 1055 1
Store 1058 1059
1060: 6(int) Load 8(invocation)
1061: 146(ptr) AccessChain 27(data) 51 65
1062: 23(f64vec4) Load 1061
1063:156(f64vec3) VectorShuffle 1062 1062 0 1 2
1064:156(f64vec3) GroupNonUniformFMul 34 InclusiveScan 1063
1065: 139(ptr) AccessChain 27(data) 1060 65 30
1066:22(float64_t) CompositeExtract 1064 0
Store 1065 1066
1067: 139(ptr) AccessChain 27(data) 1060 65 47
1068:22(float64_t) CompositeExtract 1064 1
Store 1067 1068
1069: 139(ptr) AccessChain 27(data) 1060 65 61
1070:22(float64_t) CompositeExtract 1064 2
Store 1069 1070
1071: 6(int) Load 8(invocation)
1072: 146(ptr) AccessChain 27(data) 65 65
1073: 23(f64vec4) Load 1072
1074: 23(f64vec4) GroupNonUniformFMul 34 InclusiveScan 1073
1075: 146(ptr) AccessChain 27(data) 1071 65
Store 1075 1074
1076: 6(int) Load 8(invocation)
1077: 31(ptr) AccessChain 27(data) 29 29 30
1078: 17(float) Load 1077
1079: 17(float) GroupNonUniformFMin 34 InclusiveScan 1078
1080: 31(ptr) AccessChain 27(data) 1076 29 30
Store 1080 1079
1081: 6(int) Load 8(invocation)
1082: 40(ptr) AccessChain 27(data) 38 29
1083: 18(fvec4) Load 1082
1084: 39(fvec2) VectorShuffle 1083 1083 0 1
1085: 39(fvec2) GroupNonUniformFMin 34 InclusiveScan 1084
1086: 31(ptr) AccessChain 27(data) 1081 29 30
1087: 17(float) CompositeExtract 1085 0
Store 1086 1087
1088: 31(ptr) AccessChain 27(data) 1081 29 47
1089: 17(float) CompositeExtract 1085 1
Store 1088 1089
1090: 6(int) Load 8(invocation)
1091: 40(ptr) AccessChain 27(data) 51 29
1092: 18(fvec4) Load 1091
1093: 52(fvec3) VectorShuffle 1092 1092 0 1 2
1094: 52(fvec3) GroupNonUniformFMin 34 InclusiveScan 1093
1095: 31(ptr) AccessChain 27(data) 1090 29 30
1096: 17(float) CompositeExtract 1094 0
Store 1095 1096
1097: 31(ptr) AccessChain 27(data) 1090 29 47
1098: 17(float) CompositeExtract 1094 1
Store 1097 1098
1099: 31(ptr) AccessChain 27(data) 1090 29 61
1100: 17(float) CompositeExtract 1094 2
Store 1099 1100
1101: 6(int) Load 8(invocation)
1102: 40(ptr) AccessChain 27(data) 65 29
1103: 18(fvec4) Load 1102
1104: 18(fvec4) GroupNonUniformFMin 34 InclusiveScan 1103
1105: 40(ptr) AccessChain 27(data) 1101 29
Store 1105 1104
1106: 6(int) Load 8(invocation)
1107: 71(ptr) AccessChain 27(data) 29 38 30
1108: 19(int) Load 1107
1109: 19(int) GroupNonUniformSMin 34 InclusiveScan 1108
1110: 71(ptr) AccessChain 27(data) 1106 38 30
Store 1110 1109
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
1111: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1112: 78(ptr) AccessChain 27(data) 38 38
1113: 20(ivec4) Load 1112
1114: 77(ivec2) VectorShuffle 1113 1113 0 1
1115: 77(ivec2) GroupNonUniformSMin 34 InclusiveScan 1114
1116: 71(ptr) AccessChain 27(data) 1111 38 30
1117: 19(int) CompositeExtract 1115 0
Store 1116 1117
1118: 71(ptr) AccessChain 27(data) 1111 38 47
1119: 19(int) CompositeExtract 1115 1
Store 1118 1119
1120: 6(int) Load 8(invocation)
1121: 78(ptr) AccessChain 27(data) 51 38
1122: 20(ivec4) Load 1121
1123: 88(ivec3) VectorShuffle 1122 1122 0 1 2
1124: 88(ivec3) GroupNonUniformSMin 34 InclusiveScan 1123
1125: 71(ptr) AccessChain 27(data) 1120 38 30
1126: 19(int) CompositeExtract 1124 0
Store 1125 1126
1127: 71(ptr) AccessChain 27(data) 1120 38 47
1128: 19(int) CompositeExtract 1124 1
Store 1127 1128
1129: 71(ptr) AccessChain 27(data) 1120 38 61
1130: 19(int) CompositeExtract 1124 2
Store 1129 1130
1131: 6(int) Load 8(invocation)
1132: 78(ptr) AccessChain 27(data) 65 38
1133: 20(ivec4) Load 1132
1134: 20(ivec4) GroupNonUniformSMin 34 InclusiveScan 1133
1135: 78(ptr) AccessChain 27(data) 1131 38
Store 1135 1134
1136: 6(int) Load 8(invocation)
1137: 105(ptr) AccessChain 27(data) 29 51 30
1138: 6(int) Load 1137
1139: 6(int) GroupNonUniformUMin 34 InclusiveScan 1138
1140: 105(ptr) AccessChain 27(data) 1136 51 30
Store 1140 1139
1141: 6(int) Load 8(invocation)
1142: 112(ptr) AccessChain 27(data) 38 51
1143: 21(ivec4) Load 1142
1144: 111(ivec2) VectorShuffle 1143 1143 0 1
1145: 111(ivec2) GroupNonUniformUMin 34 InclusiveScan 1144
1146: 105(ptr) AccessChain 27(data) 1141 51 30
1147: 6(int) CompositeExtract 1145 0
Store 1146 1147
1148: 105(ptr) AccessChain 27(data) 1141 51 47
1149: 6(int) CompositeExtract 1145 1
Store 1148 1149
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
1150: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1151: 112(ptr) AccessChain 27(data) 51 51
1152: 21(ivec4) Load 1151
1153: 122(ivec3) VectorShuffle 1152 1152 0 1 2
1154: 122(ivec3) GroupNonUniformUMin 34 InclusiveScan 1153
1155: 105(ptr) AccessChain 27(data) 1150 51 30
1156: 6(int) CompositeExtract 1154 0
Store 1155 1156
1157: 105(ptr) AccessChain 27(data) 1150 51 47
1158: 6(int) CompositeExtract 1154 1
Store 1157 1158
1159: 105(ptr) AccessChain 27(data) 1150 51 61
1160: 6(int) CompositeExtract 1154 2
Store 1159 1160
1161: 6(int) Load 8(invocation)
1162: 112(ptr) AccessChain 27(data) 65 51
1163: 21(ivec4) Load 1162
1164: 21(ivec4) GroupNonUniformUMin 34 InclusiveScan 1163
1165: 112(ptr) AccessChain 27(data) 1161 51
Store 1165 1164
1166: 6(int) Load 8(invocation)
1167: 139(ptr) AccessChain 27(data) 29 65 30
1168:22(float64_t) Load 1167
1169:22(float64_t) GroupNonUniformFMin 34 InclusiveScan 1168
1170: 139(ptr) AccessChain 27(data) 1166 65 30
Store 1170 1169
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
1171: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1172: 146(ptr) AccessChain 27(data) 38 65
1173: 23(f64vec4) Load 1172
1174:145(f64vec2) VectorShuffle 1173 1173 0 1
1175:145(f64vec2) GroupNonUniformFMin 34 InclusiveScan 1174
1176: 139(ptr) AccessChain 27(data) 1171 65 30
1177:22(float64_t) CompositeExtract 1175 0
Store 1176 1177
1178: 139(ptr) AccessChain 27(data) 1171 65 47
1179:22(float64_t) CompositeExtract 1175 1
Store 1178 1179
1180: 6(int) Load 8(invocation)
1181: 146(ptr) AccessChain 27(data) 51 65
1182: 23(f64vec4) Load 1181
1183:156(f64vec3) VectorShuffle 1182 1182 0 1 2
1184:156(f64vec3) GroupNonUniformFMin 34 InclusiveScan 1183
1185: 139(ptr) AccessChain 27(data) 1180 65 30
1186:22(float64_t) CompositeExtract 1184 0
Store 1185 1186
1187: 139(ptr) AccessChain 27(data) 1180 65 47
1188:22(float64_t) CompositeExtract 1184 1
Store 1187 1188
1189: 139(ptr) AccessChain 27(data) 1180 65 61
1190:22(float64_t) CompositeExtract 1184 2
Store 1189 1190
1191: 6(int) Load 8(invocation)
1192: 146(ptr) AccessChain 27(data) 65 65
1193: 23(f64vec4) Load 1192
1194: 23(f64vec4) GroupNonUniformFMin 34 InclusiveScan 1193
1195: 146(ptr) AccessChain 27(data) 1191 65
Store 1195 1194
1196: 6(int) Load 8(invocation)
1197: 31(ptr) AccessChain 27(data) 29 29 30
1198: 17(float) Load 1197
1199: 17(float) GroupNonUniformFMax 34 InclusiveScan 1198
1200: 31(ptr) AccessChain 27(data) 1196 29 30
Store 1200 1199
1201: 6(int) Load 8(invocation)
1202: 40(ptr) AccessChain 27(data) 38 29
1203: 18(fvec4) Load 1202
1204: 39(fvec2) VectorShuffle 1203 1203 0 1
1205: 39(fvec2) GroupNonUniformFMax 34 InclusiveScan 1204
1206: 31(ptr) AccessChain 27(data) 1201 29 30
1207: 17(float) CompositeExtract 1205 0
Store 1206 1207
1208: 31(ptr) AccessChain 27(data) 1201 29 47
1209: 17(float) CompositeExtract 1205 1
Store 1208 1209
1210: 6(int) Load 8(invocation)
1211: 40(ptr) AccessChain 27(data) 51 29
1212: 18(fvec4) Load 1211
1213: 52(fvec3) VectorShuffle 1212 1212 0 1 2
1214: 52(fvec3) GroupNonUniformFMax 34 InclusiveScan 1213
1215: 31(ptr) AccessChain 27(data) 1210 29 30
1216: 17(float) CompositeExtract 1214 0
Store 1215 1216
1217: 31(ptr) AccessChain 27(data) 1210 29 47
1218: 17(float) CompositeExtract 1214 1
Store 1217 1218
1219: 31(ptr) AccessChain 27(data) 1210 29 61
1220: 17(float) CompositeExtract 1214 2
Store 1219 1220
1221: 6(int) Load 8(invocation)
1222: 40(ptr) AccessChain 27(data) 65 29
1223: 18(fvec4) Load 1222
1224: 18(fvec4) GroupNonUniformFMax 34 InclusiveScan 1223
1225: 40(ptr) AccessChain 27(data) 1221 29
Store 1225 1224
1226: 6(int) Load 8(invocation)
1227: 71(ptr) AccessChain 27(data) 29 38 30
1228: 19(int) Load 1227
1229: 19(int) GroupNonUniformSMax 34 InclusiveScan 1228
1230: 71(ptr) AccessChain 27(data) 1226 38 30
Store 1230 1229
1231: 6(int) Load 8(invocation)
1232: 78(ptr) AccessChain 27(data) 38 38
1233: 20(ivec4) Load 1232
1234: 77(ivec2) VectorShuffle 1233 1233 0 1
1235: 77(ivec2) GroupNonUniformSMax 34 InclusiveScan 1234
1236: 71(ptr) AccessChain 27(data) 1231 38 30
1237: 19(int) CompositeExtract 1235 0
Store 1236 1237
1238: 71(ptr) AccessChain 27(data) 1231 38 47
1239: 19(int) CompositeExtract 1235 1
Store 1238 1239
1240: 6(int) Load 8(invocation)
1241: 78(ptr) AccessChain 27(data) 51 38
1242: 20(ivec4) Load 1241
1243: 88(ivec3) VectorShuffle 1242 1242 0 1 2
1244: 88(ivec3) GroupNonUniformSMax 34 InclusiveScan 1243
1245: 71(ptr) AccessChain 27(data) 1240 38 30
1246: 19(int) CompositeExtract 1244 0
Store 1245 1246
1247: 71(ptr) AccessChain 27(data) 1240 38 47
1248: 19(int) CompositeExtract 1244 1
Store 1247 1248
1249: 71(ptr) AccessChain 27(data) 1240 38 61
1250: 19(int) CompositeExtract 1244 2
Store 1249 1250
1251: 6(int) Load 8(invocation)
1252: 78(ptr) AccessChain 27(data) 65 38
1253: 20(ivec4) Load 1252
1254: 20(ivec4) GroupNonUniformSMax 34 InclusiveScan 1253
1255: 78(ptr) AccessChain 27(data) 1251 38
Store 1255 1254
1256: 6(int) Load 8(invocation)
1257: 105(ptr) AccessChain 27(data) 29 51 30
1258: 6(int) Load 1257
1259: 6(int) GroupNonUniformUMax 34 InclusiveScan 1258
1260: 105(ptr) AccessChain 27(data) 1256 51 30
Store 1260 1259
1261: 6(int) Load 8(invocation)
1262: 112(ptr) AccessChain 27(data) 38 51
1263: 21(ivec4) Load 1262
1264: 111(ivec2) VectorShuffle 1263 1263 0 1
1265: 111(ivec2) GroupNonUniformUMax 34 InclusiveScan 1264
1266: 105(ptr) AccessChain 27(data) 1261 51 30
1267: 6(int) CompositeExtract 1265 0
Store 1266 1267
1268: 105(ptr) AccessChain 27(data) 1261 51 47
1269: 6(int) CompositeExtract 1265 1
Store 1268 1269
1270: 6(int) Load 8(invocation)
1271: 112(ptr) AccessChain 27(data) 51 51
1272: 21(ivec4) Load 1271
1273: 122(ivec3) VectorShuffle 1272 1272 0 1 2
1274: 122(ivec3) GroupNonUniformUMax 34 InclusiveScan 1273
1275: 105(ptr) AccessChain 27(data) 1270 51 30
1276: 6(int) CompositeExtract 1274 0
Store 1275 1276
1277: 105(ptr) AccessChain 27(data) 1270 51 47
1278: 6(int) CompositeExtract 1274 1
Store 1277 1278
1279: 105(ptr) AccessChain 27(data) 1270 51 61
1280: 6(int) CompositeExtract 1274 2
Store 1279 1280
1281: 6(int) Load 8(invocation)
1282: 112(ptr) AccessChain 27(data) 65 51
1283: 21(ivec4) Load 1282
1284: 21(ivec4) GroupNonUniformUMax 34 InclusiveScan 1283
1285: 112(ptr) AccessChain 27(data) 1281 51
Store 1285 1284
1286: 6(int) Load 8(invocation)
1287: 139(ptr) AccessChain 27(data) 29 65 30
1288:22(float64_t) Load 1287
1289:22(float64_t) GroupNonUniformFMax 34 InclusiveScan 1288
1290: 139(ptr) AccessChain 27(data) 1286 65 30
Store 1290 1289
1291: 6(int) Load 8(invocation)
1292: 146(ptr) AccessChain 27(data) 38 65
1293: 23(f64vec4) Load 1292
1294:145(f64vec2) VectorShuffle 1293 1293 0 1
1295:145(f64vec2) GroupNonUniformFMax 34 InclusiveScan 1294
1296: 139(ptr) AccessChain 27(data) 1291 65 30
1297:22(float64_t) CompositeExtract 1295 0
Store 1296 1297
1298: 139(ptr) AccessChain 27(data) 1291 65 47
1299:22(float64_t) CompositeExtract 1295 1
Store 1298 1299
1300: 6(int) Load 8(invocation)
1301: 146(ptr) AccessChain 27(data) 51 65
1302: 23(f64vec4) Load 1301
1303:156(f64vec3) VectorShuffle 1302 1302 0 1 2
1304:156(f64vec3) GroupNonUniformFMax 34 InclusiveScan 1303
1305: 139(ptr) AccessChain 27(data) 1300 65 30
1306:22(float64_t) CompositeExtract 1304 0
Store 1305 1306
1307: 139(ptr) AccessChain 27(data) 1300 65 47
1308:22(float64_t) CompositeExtract 1304 1
Store 1307 1308
1309: 139(ptr) AccessChain 27(data) 1300 65 61
1310:22(float64_t) CompositeExtract 1304 2
Store 1309 1310
1311: 6(int) Load 8(invocation)
1312: 146(ptr) AccessChain 27(data) 65 65
1313: 23(f64vec4) Load 1312
1314: 23(f64vec4) GroupNonUniformFMax 34 InclusiveScan 1313
1315: 146(ptr) AccessChain 27(data) 1311 65
Store 1315 1314
1316: 6(int) Load 8(invocation)
1317: 71(ptr) AccessChain 27(data) 29 38 30
1318: 19(int) Load 1317
1319: 19(int) GroupNonUniformBitwiseAnd 34 InclusiveScan 1318
1320: 71(ptr) AccessChain 27(data) 1316 38 30
Store 1320 1319
1321: 6(int) Load 8(invocation)
1322: 78(ptr) AccessChain 27(data) 38 38
1323: 20(ivec4) Load 1322
1324: 77(ivec2) VectorShuffle 1323 1323 0 1
1325: 77(ivec2) GroupNonUniformBitwiseAnd 34 InclusiveScan 1324
1326: 71(ptr) AccessChain 27(data) 1321 38 30
1327: 19(int) CompositeExtract 1325 0
Store 1326 1327
1328: 71(ptr) AccessChain 27(data) 1321 38 47
1329: 19(int) CompositeExtract 1325 1
Store 1328 1329
1330: 6(int) Load 8(invocation)
1331: 78(ptr) AccessChain 27(data) 51 38
1332: 20(ivec4) Load 1331
1333: 88(ivec3) VectorShuffle 1332 1332 0 1 2
1334: 88(ivec3) GroupNonUniformBitwiseAnd 34 InclusiveScan 1333
1335: 71(ptr) AccessChain 27(data) 1330 38 30
1336: 19(int) CompositeExtract 1334 0
Store 1335 1336
1337: 71(ptr) AccessChain 27(data) 1330 38 47
1338: 19(int) CompositeExtract 1334 1
Store 1337 1338
1339: 71(ptr) AccessChain 27(data) 1330 38 61
1340: 19(int) CompositeExtract 1334 2
Store 1339 1340
1341: 6(int) Load 8(invocation)
1342: 78(ptr) AccessChain 27(data) 65 38
1343: 20(ivec4) Load 1342
1344: 20(ivec4) GroupNonUniformBitwiseAnd 34 InclusiveScan 1343
1345: 78(ptr) AccessChain 27(data) 1341 38
Store 1345 1344
1346: 6(int) Load 8(invocation)
1347: 105(ptr) AccessChain 27(data) 29 51 30
1348: 6(int) Load 1347
1349: 6(int) GroupNonUniformBitwiseAnd 34 InclusiveScan 1348
1350: 105(ptr) AccessChain 27(data) 1346 51 30
Store 1350 1349
1351: 6(int) Load 8(invocation)
1352: 112(ptr) AccessChain 27(data) 38 51
1353: 21(ivec4) Load 1352
1354: 111(ivec2) VectorShuffle 1353 1353 0 1
1355: 111(ivec2) GroupNonUniformBitwiseAnd 34 InclusiveScan 1354
1356: 105(ptr) AccessChain 27(data) 1351 51 30
1357: 6(int) CompositeExtract 1355 0
Store 1356 1357
1358: 105(ptr) AccessChain 27(data) 1351 51 47
1359: 6(int) CompositeExtract 1355 1
Store 1358 1359
1360: 6(int) Load 8(invocation)
1361: 112(ptr) AccessChain 27(data) 51 51
1362: 21(ivec4) Load 1361
1363: 122(ivec3) VectorShuffle 1362 1362 0 1 2
1364: 122(ivec3) GroupNonUniformBitwiseAnd 34 InclusiveScan 1363
1365: 105(ptr) AccessChain 27(data) 1360 51 30
1366: 6(int) CompositeExtract 1364 0
Store 1365 1366
1367: 105(ptr) AccessChain 27(data) 1360 51 47
1368: 6(int) CompositeExtract 1364 1
Store 1367 1368
1369: 105(ptr) AccessChain 27(data) 1360 51 61
1370: 6(int) CompositeExtract 1364 2
Store 1369 1370
1371: 6(int) Load 8(invocation)
1372: 112(ptr) AccessChain 27(data) 65 51
1373: 21(ivec4) Load 1372
1374: 21(ivec4) GroupNonUniformBitwiseAnd 34 InclusiveScan 1373
1375: 112(ptr) AccessChain 27(data) 1371 51
Store 1375 1374
1376: 6(int) Load 8(invocation)
1377: 71(ptr) AccessChain 27(data) 29 38 30
1378: 19(int) Load 1377
1379: 595(bool) SLessThan 1378 29
1380: 595(bool) GroupNonUniformLogicalAnd 34 InclusiveScan 1379
1381: 19(int) Select 1380 38 29
1382: 71(ptr) AccessChain 27(data) 1376 38 30
Store 1382 1381
1383: 6(int) Load 8(invocation)
1384: 78(ptr) AccessChain 27(data) 38 38
1385: 20(ivec4) Load 1384
1386: 77(ivec2) VectorShuffle 1385 1385 0 1
1387: 605(bvec2) SLessThan 1386 604
1388: 605(bvec2) GroupNonUniformLogicalAnd 34 InclusiveScan 1387
1389: 77(ivec2) Select 1388 608 604
1390: 71(ptr) AccessChain 27(data) 1383 38 30
1391: 19(int) CompositeExtract 1389 0
Store 1390 1391
1392: 71(ptr) AccessChain 27(data) 1383 38 47
1393: 19(int) CompositeExtract 1389 1
Store 1392 1393
1394: 6(int) Load 8(invocation)
1395: 78(ptr) AccessChain 27(data) 38 38
1396: 20(ivec4) Load 1395
1397: 88(ivec3) VectorShuffle 1396 1396 0 1 2
1398: 619(bvec3) SLessThan 1397 618
1399: 619(bvec3) GroupNonUniformLogicalAnd 34 InclusiveScan 1398
1400: 88(ivec3) Select 1399 622 618
1401: 71(ptr) AccessChain 27(data) 1394 38 30
1402: 19(int) CompositeExtract 1400 0
Store 1401 1402
1403: 71(ptr) AccessChain 27(data) 1394 38 47
1404: 19(int) CompositeExtract 1400 1
Store 1403 1404
1405: 71(ptr) AccessChain 27(data) 1394 38 61
1406: 19(int) CompositeExtract 1400 2
Store 1405 1406
1407: 6(int) Load 8(invocation)
1408: 78(ptr) AccessChain 27(data) 38 38
1409: 20(ivec4) Load 1408
1410: 634(bvec4) SLessThan 1409 633
1411: 634(bvec4) GroupNonUniformLogicalAnd 34 InclusiveScan 1410
1412: 20(ivec4) Select 1411 637 633
1413: 78(ptr) AccessChain 27(data) 1407 38
Store 1413 1412
1414: 6(int) Load 8(invocation)
1415: 71(ptr) AccessChain 27(data) 29 38 30
1416: 19(int) Load 1415
1417: 19(int) GroupNonUniformBitwiseOr 34 InclusiveScan 1416
1418: 71(ptr) AccessChain 27(data) 1414 38 30
Store 1418 1417
1419: 6(int) Load 8(invocation)
1420: 78(ptr) AccessChain 27(data) 38 38
1421: 20(ivec4) Load 1420
1422: 77(ivec2) VectorShuffle 1421 1421 0 1
1423: 77(ivec2) GroupNonUniformBitwiseOr 34 InclusiveScan 1422
1424: 71(ptr) AccessChain 27(data) 1419 38 30
1425: 19(int) CompositeExtract 1423 0
Store 1424 1425
1426: 71(ptr) AccessChain 27(data) 1419 38 47
1427: 19(int) CompositeExtract 1423 1
Store 1426 1427
1428: 6(int) Load 8(invocation)
1429: 78(ptr) AccessChain 27(data) 51 38
1430: 20(ivec4) Load 1429
1431: 88(ivec3) VectorShuffle 1430 1430 0 1 2
1432: 88(ivec3) GroupNonUniformBitwiseOr 34 InclusiveScan 1431
1433: 71(ptr) AccessChain 27(data) 1428 38 30
1434: 19(int) CompositeExtract 1432 0
Store 1433 1434
1435: 71(ptr) AccessChain 27(data) 1428 38 47
1436: 19(int) CompositeExtract 1432 1
Store 1435 1436
1437: 71(ptr) AccessChain 27(data) 1428 38 61
1438: 19(int) CompositeExtract 1432 2
Store 1437 1438
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
1439: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1440: 78(ptr) AccessChain 27(data) 65 38
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
1441: 20(ivec4) Load 1440
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1442: 20(ivec4) GroupNonUniformBitwiseOr 34 InclusiveScan 1441
1443: 78(ptr) AccessChain 27(data) 1439 38
Store 1443 1442
1444: 6(int) Load 8(invocation)
1445: 105(ptr) AccessChain 27(data) 29 51 30
1446: 6(int) Load 1445
1447: 6(int) GroupNonUniformBitwiseOr 34 InclusiveScan 1446
1448: 105(ptr) AccessChain 27(data) 1444 51 30
Store 1448 1447
1449: 6(int) Load 8(invocation)
1450: 112(ptr) AccessChain 27(data) 38 51
1451: 21(ivec4) Load 1450
1452: 111(ivec2) VectorShuffle 1451 1451 0 1
1453: 111(ivec2) GroupNonUniformBitwiseOr 34 InclusiveScan 1452
1454: 105(ptr) AccessChain 27(data) 1449 51 30
1455: 6(int) CompositeExtract 1453 0
Store 1454 1455
1456: 105(ptr) AccessChain 27(data) 1449 51 47
1457: 6(int) CompositeExtract 1453 1
Store 1456 1457
1458: 6(int) Load 8(invocation)
1459: 112(ptr) AccessChain 27(data) 51 51
1460: 21(ivec4) Load 1459
1461: 122(ivec3) VectorShuffle 1460 1460 0 1 2
1462: 122(ivec3) GroupNonUniformBitwiseOr 34 InclusiveScan 1461
1463: 105(ptr) AccessChain 27(data) 1458 51 30
1464: 6(int) CompositeExtract 1462 0
Store 1463 1464
1465: 105(ptr) AccessChain 27(data) 1458 51 47
1466: 6(int) CompositeExtract 1462 1
Store 1465 1466
1467: 105(ptr) AccessChain 27(data) 1458 51 61
1468: 6(int) CompositeExtract 1462 2
Store 1467 1468
1469: 6(int) Load 8(invocation)
1470: 112(ptr) AccessChain 27(data) 65 51
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
1471: 21(ivec4) Load 1470
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1472: 21(ivec4) GroupNonUniformBitwiseOr 34 InclusiveScan 1471
1473: 112(ptr) AccessChain 27(data) 1469 51
Store 1473 1472
1474: 6(int) Load 8(invocation)
1475: 71(ptr) AccessChain 27(data) 29 38 30
1476: 19(int) Load 1475
1477: 595(bool) SLessThan 1476 29
1478: 595(bool) GroupNonUniformLogicalOr 34 InclusiveScan 1477
1479: 19(int) Select 1478 38 29
1480: 71(ptr) AccessChain 27(data) 1474 38 30
Store 1480 1479
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
1481: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1482: 78(ptr) AccessChain 27(data) 38 38
1483: 20(ivec4) Load 1482
1484: 77(ivec2) VectorShuffle 1483 1483 0 1
1485: 605(bvec2) SLessThan 1484 604
1486: 605(bvec2) GroupNonUniformLogicalOr 34 InclusiveScan 1485
1487: 77(ivec2) Select 1486 608 604
1488: 71(ptr) AccessChain 27(data) 1481 38 30
1489: 19(int) CompositeExtract 1487 0
Store 1488 1489
1490: 71(ptr) AccessChain 27(data) 1481 38 47
1491: 19(int) CompositeExtract 1487 1
Store 1490 1491
1492: 6(int) Load 8(invocation)
1493: 78(ptr) AccessChain 27(data) 38 38
1494: 20(ivec4) Load 1493
1495: 88(ivec3) VectorShuffle 1494 1494 0 1 2
1496: 619(bvec3) SLessThan 1495 618
1497: 619(bvec3) GroupNonUniformLogicalOr 34 InclusiveScan 1496
1498: 88(ivec3) Select 1497 622 618
1499: 71(ptr) AccessChain 27(data) 1492 38 30
1500: 19(int) CompositeExtract 1498 0
Store 1499 1500
1501: 71(ptr) AccessChain 27(data) 1492 38 47
1502: 19(int) CompositeExtract 1498 1
Store 1501 1502
1503: 71(ptr) AccessChain 27(data) 1492 38 61
1504: 19(int) CompositeExtract 1498 2
Store 1503 1504
1505: 6(int) Load 8(invocation)
1506: 78(ptr) AccessChain 27(data) 38 38
1507: 20(ivec4) Load 1506
1508: 634(bvec4) SLessThan 1507 633
1509: 634(bvec4) GroupNonUniformLogicalOr 34 InclusiveScan 1508
1510: 20(ivec4) Select 1509 637 633
1511: 78(ptr) AccessChain 27(data) 1505 38
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Store 1511 1510
1512: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1513: 71(ptr) AccessChain 27(data) 29 38 30
1514: 19(int) Load 1513
1515: 19(int) GroupNonUniformBitwiseXor 34 InclusiveScan 1514
1516: 71(ptr) AccessChain 27(data) 1512 38 30
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Store 1516 1515
1517: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1518: 78(ptr) AccessChain 27(data) 38 38
1519: 20(ivec4) Load 1518
1520: 77(ivec2) VectorShuffle 1519 1519 0 1
1521: 77(ivec2) GroupNonUniformBitwiseXor 34 InclusiveScan 1520
1522: 71(ptr) AccessChain 27(data) 1517 38 30
1523: 19(int) CompositeExtract 1521 0
Store 1522 1523
1524: 71(ptr) AccessChain 27(data) 1517 38 47
1525: 19(int) CompositeExtract 1521 1
Store 1524 1525
1526: 6(int) Load 8(invocation)
1527: 78(ptr) AccessChain 27(data) 51 38
1528: 20(ivec4) Load 1527
1529: 88(ivec3) VectorShuffle 1528 1528 0 1 2
1530: 88(ivec3) GroupNonUniformBitwiseXor 34 InclusiveScan 1529
1531: 71(ptr) AccessChain 27(data) 1526 38 30
1532: 19(int) CompositeExtract 1530 0
Store 1531 1532
1533: 71(ptr) AccessChain 27(data) 1526 38 47
1534: 19(int) CompositeExtract 1530 1
Store 1533 1534
1535: 71(ptr) AccessChain 27(data) 1526 38 61
1536: 19(int) CompositeExtract 1530 2
Store 1535 1536
1537: 6(int) Load 8(invocation)
1538: 78(ptr) AccessChain 27(data) 65 38
1539: 20(ivec4) Load 1538
1540: 20(ivec4) GroupNonUniformBitwiseXor 34 InclusiveScan 1539
1541: 78(ptr) AccessChain 27(data) 1537 38
Store 1541 1540
1542: 6(int) Load 8(invocation)
1543: 105(ptr) AccessChain 27(data) 29 51 30
1544: 6(int) Load 1543
1545: 6(int) GroupNonUniformBitwiseXor 34 InclusiveScan 1544
1546: 105(ptr) AccessChain 27(data) 1542 51 30
Store 1546 1545
1547: 6(int) Load 8(invocation)
1548: 112(ptr) AccessChain 27(data) 38 51
1549: 21(ivec4) Load 1548
1550: 111(ivec2) VectorShuffle 1549 1549 0 1
1551: 111(ivec2) GroupNonUniformBitwiseXor 34 InclusiveScan 1550
1552: 105(ptr) AccessChain 27(data) 1547 51 30
1553: 6(int) CompositeExtract 1551 0
Store 1552 1553
1554: 105(ptr) AccessChain 27(data) 1547 51 47
1555: 6(int) CompositeExtract 1551 1
Store 1554 1555
1556: 6(int) Load 8(invocation)
1557: 112(ptr) AccessChain 27(data) 51 51
1558: 21(ivec4) Load 1557
1559: 122(ivec3) VectorShuffle 1558 1558 0 1 2
1560: 122(ivec3) GroupNonUniformBitwiseXor 34 InclusiveScan 1559
1561: 105(ptr) AccessChain 27(data) 1556 51 30
1562: 6(int) CompositeExtract 1560 0
Store 1561 1562
1563: 105(ptr) AccessChain 27(data) 1556 51 47
1564: 6(int) CompositeExtract 1560 1
Store 1563 1564
1565: 105(ptr) AccessChain 27(data) 1556 51 61
1566: 6(int) CompositeExtract 1560 2
Store 1565 1566
1567: 6(int) Load 8(invocation)
1568: 112(ptr) AccessChain 27(data) 65 51
1569: 21(ivec4) Load 1568
1570: 21(ivec4) GroupNonUniformBitwiseXor 34 InclusiveScan 1569
1571: 112(ptr) AccessChain 27(data) 1567 51
Store 1571 1570
1572: 6(int) Load 8(invocation)
1573: 71(ptr) AccessChain 27(data) 29 38 30
1574: 19(int) Load 1573
1575: 595(bool) SLessThan 1574 29
1576: 595(bool) GroupNonUniformLogicalXor 34 InclusiveScan 1575
1577: 19(int) Select 1576 38 29
1578: 71(ptr) AccessChain 27(data) 1572 38 30
Store 1578 1577
1579: 6(int) Load 8(invocation)
1580: 78(ptr) AccessChain 27(data) 38 38
1581: 20(ivec4) Load 1580
1582: 77(ivec2) VectorShuffle 1581 1581 0 1
1583: 605(bvec2) SLessThan 1582 604
1584: 605(bvec2) GroupNonUniformLogicalXor 34 InclusiveScan 1583
1585: 77(ivec2) Select 1584 608 604
1586: 71(ptr) AccessChain 27(data) 1579 38 30
1587: 19(int) CompositeExtract 1585 0
Store 1586 1587
1588: 71(ptr) AccessChain 27(data) 1579 38 47
1589: 19(int) CompositeExtract 1585 1
Store 1588 1589
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
1590: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1591: 78(ptr) AccessChain 27(data) 38 38
1592: 20(ivec4) Load 1591
1593: 88(ivec3) VectorShuffle 1592 1592 0 1 2
1594: 619(bvec3) SLessThan 1593 618
1595: 619(bvec3) GroupNonUniformLogicalXor 34 InclusiveScan 1594
1596: 88(ivec3) Select 1595 622 618
1597: 71(ptr) AccessChain 27(data) 1590 38 30
1598: 19(int) CompositeExtract 1596 0
Store 1597 1598
1599: 71(ptr) AccessChain 27(data) 1590 38 47
1600: 19(int) CompositeExtract 1596 1
Store 1599 1600
1601: 71(ptr) AccessChain 27(data) 1590 38 61
1602: 19(int) CompositeExtract 1596 2
Store 1601 1602
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
1603: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1604: 78(ptr) AccessChain 27(data) 38 38
1605: 20(ivec4) Load 1604
1606: 634(bvec4) SLessThan 1605 633
1607: 634(bvec4) GroupNonUniformLogicalXor 34 InclusiveScan 1606
1608: 20(ivec4) Select 1607 637 633
1609: 78(ptr) AccessChain 27(data) 1603 38
Store 1609 1608
1610: 6(int) Load 8(invocation)
1611: 31(ptr) AccessChain 27(data) 29 29 30
1612: 17(float) Load 1611
1613: 17(float) GroupNonUniformFAdd 34 ExclusiveScan 1612
1614: 31(ptr) AccessChain 27(data) 1610 29 30
Store 1614 1613
1615: 6(int) Load 8(invocation)
1616: 40(ptr) AccessChain 27(data) 38 29
1617: 18(fvec4) Load 1616
1618: 39(fvec2) VectorShuffle 1617 1617 0 1
1619: 39(fvec2) GroupNonUniformFAdd 34 ExclusiveScan 1618
1620: 31(ptr) AccessChain 27(data) 1615 29 30
1621: 17(float) CompositeExtract 1619 0
Store 1620 1621
1622: 31(ptr) AccessChain 27(data) 1615 29 47
1623: 17(float) CompositeExtract 1619 1
Store 1622 1623
1624: 6(int) Load 8(invocation)
1625: 40(ptr) AccessChain 27(data) 51 29
1626: 18(fvec4) Load 1625
1627: 52(fvec3) VectorShuffle 1626 1626 0 1 2
1628: 52(fvec3) GroupNonUniformFAdd 34 ExclusiveScan 1627
1629: 31(ptr) AccessChain 27(data) 1624 29 30
1630: 17(float) CompositeExtract 1628 0
Store 1629 1630
1631: 31(ptr) AccessChain 27(data) 1624 29 47
1632: 17(float) CompositeExtract 1628 1
Store 1631 1632
1633: 31(ptr) AccessChain 27(data) 1624 29 61
1634: 17(float) CompositeExtract 1628 2
Store 1633 1634
1635: 6(int) Load 8(invocation)
1636: 40(ptr) AccessChain 27(data) 65 29
1637: 18(fvec4) Load 1636
1638: 18(fvec4) GroupNonUniformFAdd 34 ExclusiveScan 1637
1639: 40(ptr) AccessChain 27(data) 1635 29
Store 1639 1638
1640: 6(int) Load 8(invocation)
1641: 71(ptr) AccessChain 27(data) 29 38 30
1642: 19(int) Load 1641
1643: 19(int) GroupNonUniformIAdd 34 ExclusiveScan 1642
1644: 71(ptr) AccessChain 27(data) 1640 38 30
Store 1644 1643
1645: 6(int) Load 8(invocation)
1646: 78(ptr) AccessChain 27(data) 38 38
1647: 20(ivec4) Load 1646
1648: 77(ivec2) VectorShuffle 1647 1647 0 1
1649: 77(ivec2) GroupNonUniformIAdd 34 ExclusiveScan 1648
1650: 71(ptr) AccessChain 27(data) 1645 38 30
1651: 19(int) CompositeExtract 1649 0
Store 1650 1651
1652: 71(ptr) AccessChain 27(data) 1645 38 47
1653: 19(int) CompositeExtract 1649 1
Store 1652 1653
1654: 6(int) Load 8(invocation)
1655: 78(ptr) AccessChain 27(data) 51 38
1656: 20(ivec4) Load 1655
1657: 88(ivec3) VectorShuffle 1656 1656 0 1 2
1658: 88(ivec3) GroupNonUniformIAdd 34 ExclusiveScan 1657
1659: 71(ptr) AccessChain 27(data) 1654 38 30
1660: 19(int) CompositeExtract 1658 0
Store 1659 1660
1661: 71(ptr) AccessChain 27(data) 1654 38 47
1662: 19(int) CompositeExtract 1658 1
Store 1661 1662
1663: 71(ptr) AccessChain 27(data) 1654 38 61
1664: 19(int) CompositeExtract 1658 2
Store 1663 1664
1665: 6(int) Load 8(invocation)
1666: 78(ptr) AccessChain 27(data) 65 38
1667: 20(ivec4) Load 1666
1668: 20(ivec4) GroupNonUniformIAdd 34 ExclusiveScan 1667
1669: 78(ptr) AccessChain 27(data) 1665 38
Store 1669 1668
1670: 6(int) Load 8(invocation)
1671: 105(ptr) AccessChain 27(data) 29 51 30
1672: 6(int) Load 1671
1673: 6(int) GroupNonUniformIAdd 34 ExclusiveScan 1672
1674: 105(ptr) AccessChain 27(data) 1670 51 30
Store 1674 1673
1675: 6(int) Load 8(invocation)
1676: 112(ptr) AccessChain 27(data) 38 51
1677: 21(ivec4) Load 1676
1678: 111(ivec2) VectorShuffle 1677 1677 0 1
1679: 111(ivec2) GroupNonUniformIAdd 34 ExclusiveScan 1678
1680: 105(ptr) AccessChain 27(data) 1675 51 30
1681: 6(int) CompositeExtract 1679 0
Store 1680 1681
1682: 105(ptr) AccessChain 27(data) 1675 51 47
1683: 6(int) CompositeExtract 1679 1
Store 1682 1683
1684: 6(int) Load 8(invocation)
1685: 112(ptr) AccessChain 27(data) 51 51
1686: 21(ivec4) Load 1685
1687: 122(ivec3) VectorShuffle 1686 1686 0 1 2
1688: 122(ivec3) GroupNonUniformIAdd 34 ExclusiveScan 1687
1689: 105(ptr) AccessChain 27(data) 1684 51 30
1690: 6(int) CompositeExtract 1688 0
Store 1689 1690
1691: 105(ptr) AccessChain 27(data) 1684 51 47
1692: 6(int) CompositeExtract 1688 1
Store 1691 1692
1693: 105(ptr) AccessChain 27(data) 1684 51 61
1694: 6(int) CompositeExtract 1688 2
Store 1693 1694
1695: 6(int) Load 8(invocation)
1696: 112(ptr) AccessChain 27(data) 65 51
1697: 21(ivec4) Load 1696
1698: 21(ivec4) GroupNonUniformIAdd 34 ExclusiveScan 1697
1699: 112(ptr) AccessChain 27(data) 1695 51
Store 1699 1698
1700: 6(int) Load 8(invocation)
1701: 139(ptr) AccessChain 27(data) 29 65 30
1702:22(float64_t) Load 1701
1703:22(float64_t) GroupNonUniformFAdd 34 ExclusiveScan 1702
1704: 139(ptr) AccessChain 27(data) 1700 65 30
Store 1704 1703
1705: 6(int) Load 8(invocation)
1706: 146(ptr) AccessChain 27(data) 38 65
1707: 23(f64vec4) Load 1706
1708:145(f64vec2) VectorShuffle 1707 1707 0 1
1709:145(f64vec2) GroupNonUniformFAdd 34 ExclusiveScan 1708
1710: 139(ptr) AccessChain 27(data) 1705 65 30
1711:22(float64_t) CompositeExtract 1709 0
Store 1710 1711
1712: 139(ptr) AccessChain 27(data) 1705 65 47
1713:22(float64_t) CompositeExtract 1709 1
Store 1712 1713
1714: 6(int) Load 8(invocation)
1715: 146(ptr) AccessChain 27(data) 51 65
1716: 23(f64vec4) Load 1715
1717:156(f64vec3) VectorShuffle 1716 1716 0 1 2
1718:156(f64vec3) GroupNonUniformFAdd 34 ExclusiveScan 1717
1719: 139(ptr) AccessChain 27(data) 1714 65 30
1720:22(float64_t) CompositeExtract 1718 0
Store 1719 1720
1721: 139(ptr) AccessChain 27(data) 1714 65 47
1722:22(float64_t) CompositeExtract 1718 1
Store 1721 1722
1723: 139(ptr) AccessChain 27(data) 1714 65 61
1724:22(float64_t) CompositeExtract 1718 2
Store 1723 1724
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
1725: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1726: 146(ptr) AccessChain 27(data) 65 65
1727: 23(f64vec4) Load 1726
1728: 23(f64vec4) GroupNonUniformFAdd 34 ExclusiveScan 1727
1729: 146(ptr) AccessChain 27(data) 1725 65
Store 1729 1728
1730: 6(int) Load 8(invocation)
1731: 31(ptr) AccessChain 27(data) 29 29 30
1732: 17(float) Load 1731
1733: 17(float) GroupNonUniformFMul 34 ExclusiveScan 1732
1734: 31(ptr) AccessChain 27(data) 1730 29 30
Store 1734 1733
1735: 6(int) Load 8(invocation)
1736: 40(ptr) AccessChain 27(data) 38 29
1737: 18(fvec4) Load 1736
1738: 39(fvec2) VectorShuffle 1737 1737 0 1
1739: 39(fvec2) GroupNonUniformFMul 34 ExclusiveScan 1738
1740: 31(ptr) AccessChain 27(data) 1735 29 30
1741: 17(float) CompositeExtract 1739 0
Store 1740 1741
1742: 31(ptr) AccessChain 27(data) 1735 29 47
1743: 17(float) CompositeExtract 1739 1
Store 1742 1743
1744: 6(int) Load 8(invocation)
1745: 40(ptr) AccessChain 27(data) 51 29
1746: 18(fvec4) Load 1745
1747: 52(fvec3) VectorShuffle 1746 1746 0 1 2
1748: 52(fvec3) GroupNonUniformFMul 34 ExclusiveScan 1747
1749: 31(ptr) AccessChain 27(data) 1744 29 30
1750: 17(float) CompositeExtract 1748 0
Store 1749 1750
1751: 31(ptr) AccessChain 27(data) 1744 29 47
1752: 17(float) CompositeExtract 1748 1
Store 1751 1752
1753: 31(ptr) AccessChain 27(data) 1744 29 61
1754: 17(float) CompositeExtract 1748 2
Store 1753 1754
1755: 6(int) Load 8(invocation)
1756: 40(ptr) AccessChain 27(data) 65 29
1757: 18(fvec4) Load 1756
1758: 18(fvec4) GroupNonUniformFMul 34 ExclusiveScan 1757
1759: 40(ptr) AccessChain 27(data) 1755 29
Store 1759 1758
1760: 6(int) Load 8(invocation)
1761: 71(ptr) AccessChain 27(data) 29 38 30
1762: 19(int) Load 1761
1763: 19(int) GroupNonUniformIMul 34 ExclusiveScan 1762
1764: 71(ptr) AccessChain 27(data) 1760 38 30
Store 1764 1763
1765: 6(int) Load 8(invocation)
1766: 78(ptr) AccessChain 27(data) 38 38
1767: 20(ivec4) Load 1766
1768: 77(ivec2) VectorShuffle 1767 1767 0 1
1769: 77(ivec2) GroupNonUniformIMul 34 ExclusiveScan 1768
1770: 71(ptr) AccessChain 27(data) 1765 38 30
1771: 19(int) CompositeExtract 1769 0
Store 1770 1771
1772: 71(ptr) AccessChain 27(data) 1765 38 47
1773: 19(int) CompositeExtract 1769 1
Store 1772 1773
1774: 6(int) Load 8(invocation)
1775: 78(ptr) AccessChain 27(data) 51 38
1776: 20(ivec4) Load 1775
1777: 88(ivec3) VectorShuffle 1776 1776 0 1 2
1778: 88(ivec3) GroupNonUniformIMul 34 ExclusiveScan 1777
1779: 71(ptr) AccessChain 27(data) 1774 38 30
1780: 19(int) CompositeExtract 1778 0
Store 1779 1780
1781: 71(ptr) AccessChain 27(data) 1774 38 47
1782: 19(int) CompositeExtract 1778 1
Store 1781 1782
1783: 71(ptr) AccessChain 27(data) 1774 38 61
1784: 19(int) CompositeExtract 1778 2
Store 1783 1784
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
1785: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1786: 78(ptr) AccessChain 27(data) 65 38
1787: 20(ivec4) Load 1786
1788: 20(ivec4) GroupNonUniformIMul 34 ExclusiveScan 1787
1789: 78(ptr) AccessChain 27(data) 1785 38
Store 1789 1788
1790: 6(int) Load 8(invocation)
1791: 105(ptr) AccessChain 27(data) 29 51 30
1792: 6(int) Load 1791
1793: 6(int) GroupNonUniformIMul 34 ExclusiveScan 1792
1794: 105(ptr) AccessChain 27(data) 1790 51 30
Store 1794 1793
1795: 6(int) Load 8(invocation)
1796: 112(ptr) AccessChain 27(data) 38 51
1797: 21(ivec4) Load 1796
1798: 111(ivec2) VectorShuffle 1797 1797 0 1
1799: 111(ivec2) GroupNonUniformIMul 34 ExclusiveScan 1798
1800: 105(ptr) AccessChain 27(data) 1795 51 30
1801: 6(int) CompositeExtract 1799 0
Store 1800 1801
1802: 105(ptr) AccessChain 27(data) 1795 51 47
1803: 6(int) CompositeExtract 1799 1
Store 1802 1803
1804: 6(int) Load 8(invocation)
1805: 112(ptr) AccessChain 27(data) 51 51
1806: 21(ivec4) Load 1805
1807: 122(ivec3) VectorShuffle 1806 1806 0 1 2
1808: 122(ivec3) GroupNonUniformIMul 34 ExclusiveScan 1807
1809: 105(ptr) AccessChain 27(data) 1804 51 30
1810: 6(int) CompositeExtract 1808 0
Store 1809 1810
1811: 105(ptr) AccessChain 27(data) 1804 51 47
1812: 6(int) CompositeExtract 1808 1
Store 1811 1812
1813: 105(ptr) AccessChain 27(data) 1804 51 61
1814: 6(int) CompositeExtract 1808 2
Store 1813 1814
1815: 6(int) Load 8(invocation)
1816: 112(ptr) AccessChain 27(data) 65 51
1817: 21(ivec4) Load 1816
1818: 21(ivec4) GroupNonUniformIMul 34 ExclusiveScan 1817
1819: 112(ptr) AccessChain 27(data) 1815 51
Store 1819 1818
1820: 6(int) Load 8(invocation)
1821: 139(ptr) AccessChain 27(data) 29 65 30
1822:22(float64_t) Load 1821
1823:22(float64_t) GroupNonUniformFMul 34 ExclusiveScan 1822
1824: 139(ptr) AccessChain 27(data) 1820 65 30
Store 1824 1823
1825: 6(int) Load 8(invocation)
1826: 146(ptr) AccessChain 27(data) 38 65
1827: 23(f64vec4) Load 1826
1828:145(f64vec2) VectorShuffle 1827 1827 0 1
1829:145(f64vec2) GroupNonUniformFMul 34 ExclusiveScan 1828
1830: 139(ptr) AccessChain 27(data) 1825 65 30
1831:22(float64_t) CompositeExtract 1829 0
Store 1830 1831
1832: 139(ptr) AccessChain 27(data) 1825 65 47
1833:22(float64_t) CompositeExtract 1829 1
Store 1832 1833
1834: 6(int) Load 8(invocation)
1835: 146(ptr) AccessChain 27(data) 51 65
1836: 23(f64vec4) Load 1835
1837:156(f64vec3) VectorShuffle 1836 1836 0 1 2
1838:156(f64vec3) GroupNonUniformFMul 34 ExclusiveScan 1837
1839: 139(ptr) AccessChain 27(data) 1834 65 30
1840:22(float64_t) CompositeExtract 1838 0
Store 1839 1840
1841: 139(ptr) AccessChain 27(data) 1834 65 47
1842:22(float64_t) CompositeExtract 1838 1
Store 1841 1842
1843: 139(ptr) AccessChain 27(data) 1834 65 61
1844:22(float64_t) CompositeExtract 1838 2
Store 1843 1844
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
1845: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1846: 146(ptr) AccessChain 27(data) 65 65
1847: 23(f64vec4) Load 1846
1848: 23(f64vec4) GroupNonUniformFMul 34 ExclusiveScan 1847
1849: 146(ptr) AccessChain 27(data) 1845 65
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Store 1849 1848
1850: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1851: 31(ptr) AccessChain 27(data) 29 29 30
1852: 17(float) Load 1851
1853: 17(float) GroupNonUniformFMin 34 ExclusiveScan 1852
1854: 31(ptr) AccessChain 27(data) 1850 29 30
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Store 1854 1853
1855: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1856: 40(ptr) AccessChain 27(data) 38 29
1857: 18(fvec4) Load 1856
1858: 39(fvec2) VectorShuffle 1857 1857 0 1
1859: 39(fvec2) GroupNonUniformFMin 34 ExclusiveScan 1858
1860: 31(ptr) AccessChain 27(data) 1855 29 30
1861: 17(float) CompositeExtract 1859 0
Store 1860 1861
1862: 31(ptr) AccessChain 27(data) 1855 29 47
1863: 17(float) CompositeExtract 1859 1
Store 1862 1863
1864: 6(int) Load 8(invocation)
1865: 40(ptr) AccessChain 27(data) 51 29
1866: 18(fvec4) Load 1865
1867: 52(fvec3) VectorShuffle 1866 1866 0 1 2
1868: 52(fvec3) GroupNonUniformFMin 34 ExclusiveScan 1867
1869: 31(ptr) AccessChain 27(data) 1864 29 30
1870: 17(float) CompositeExtract 1868 0
Store 1869 1870
1871: 31(ptr) AccessChain 27(data) 1864 29 47
1872: 17(float) CompositeExtract 1868 1
Store 1871 1872
1873: 31(ptr) AccessChain 27(data) 1864 29 61
1874: 17(float) CompositeExtract 1868 2
Store 1873 1874
1875: 6(int) Load 8(invocation)
1876: 40(ptr) AccessChain 27(data) 65 29
1877: 18(fvec4) Load 1876
1878: 18(fvec4) GroupNonUniformFMin 34 ExclusiveScan 1877
1879: 40(ptr) AccessChain 27(data) 1875 29
Store 1879 1878
1880: 6(int) Load 8(invocation)
1881: 71(ptr) AccessChain 27(data) 29 38 30
1882: 19(int) Load 1881
1883: 19(int) GroupNonUniformSMin 34 ExclusiveScan 1882
1884: 71(ptr) AccessChain 27(data) 1880 38 30
Store 1884 1883
1885: 6(int) Load 8(invocation)
1886: 78(ptr) AccessChain 27(data) 38 38
1887: 20(ivec4) Load 1886
1888: 77(ivec2) VectorShuffle 1887 1887 0 1
1889: 77(ivec2) GroupNonUniformSMin 34 ExclusiveScan 1888
1890: 71(ptr) AccessChain 27(data) 1885 38 30
1891: 19(int) CompositeExtract 1889 0
Store 1890 1891
1892: 71(ptr) AccessChain 27(data) 1885 38 47
1893: 19(int) CompositeExtract 1889 1
Store 1892 1893
1894: 6(int) Load 8(invocation)
1895: 78(ptr) AccessChain 27(data) 51 38
1896: 20(ivec4) Load 1895
1897: 88(ivec3) VectorShuffle 1896 1896 0 1 2
1898: 88(ivec3) GroupNonUniformSMin 34 ExclusiveScan 1897
1899: 71(ptr) AccessChain 27(data) 1894 38 30
1900: 19(int) CompositeExtract 1898 0
Store 1899 1900
1901: 71(ptr) AccessChain 27(data) 1894 38 47
1902: 19(int) CompositeExtract 1898 1
Store 1901 1902
1903: 71(ptr) AccessChain 27(data) 1894 38 61
1904: 19(int) CompositeExtract 1898 2
Store 1903 1904
1905: 6(int) Load 8(invocation)
1906: 78(ptr) AccessChain 27(data) 65 38
1907: 20(ivec4) Load 1906
1908: 20(ivec4) GroupNonUniformSMin 34 ExclusiveScan 1907
1909: 78(ptr) AccessChain 27(data) 1905 38
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Store 1909 1908
1910: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1911: 105(ptr) AccessChain 27(data) 29 51 30
1912: 6(int) Load 1911
1913: 6(int) GroupNonUniformUMin 34 ExclusiveScan 1912
1914: 105(ptr) AccessChain 27(data) 1910 51 30
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
Store 1914 1913
1915: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
1916: 112(ptr) AccessChain 27(data) 38 51
1917: 21(ivec4) Load 1916
1918: 111(ivec2) VectorShuffle 1917 1917 0 1
1919: 111(ivec2) GroupNonUniformUMin 34 ExclusiveScan 1918
1920: 105(ptr) AccessChain 27(data) 1915 51 30
1921: 6(int) CompositeExtract 1919 0
Store 1920 1921
1922: 105(ptr) AccessChain 27(data) 1915 51 47
1923: 6(int) CompositeExtract 1919 1
Store 1922 1923
1924: 6(int) Load 8(invocation)
1925: 112(ptr) AccessChain 27(data) 51 51
1926: 21(ivec4) Load 1925
1927: 122(ivec3) VectorShuffle 1926 1926 0 1 2
1928: 122(ivec3) GroupNonUniformUMin 34 ExclusiveScan 1927
1929: 105(ptr) AccessChain 27(data) 1924 51 30
1930: 6(int) CompositeExtract 1928 0
Store 1929 1930
1931: 105(ptr) AccessChain 27(data) 1924 51 47
1932: 6(int) CompositeExtract 1928 1
Store 1931 1932
1933: 105(ptr) AccessChain 27(data) 1924 51 61
1934: 6(int) CompositeExtract 1928 2
Store 1933 1934
1935: 6(int) Load 8(invocation)
1936: 112(ptr) AccessChain 27(data) 65 51
1937: 21(ivec4) Load 1936
1938: 21(ivec4) GroupNonUniformUMin 34 ExclusiveScan 1937
1939: 112(ptr) AccessChain 27(data) 1935 51
Store 1939 1938
1940: 6(int) Load 8(invocation)
1941: 139(ptr) AccessChain 27(data) 29 65 30
1942:22(float64_t) Load 1941
1943:22(float64_t) GroupNonUniformFMin 34 ExclusiveScan 1942
1944: 139(ptr) AccessChain 27(data) 1940 65 30
Store 1944 1943
1945: 6(int) Load 8(invocation)
1946: 146(ptr) AccessChain 27(data) 38 65
1947: 23(f64vec4) Load 1946
1948:145(f64vec2) VectorShuffle 1947 1947 0 1
1949:145(f64vec2) GroupNonUniformFMin 34 ExclusiveScan 1948
1950: 139(ptr) AccessChain 27(data) 1945 65 30
1951:22(float64_t) CompositeExtract 1949 0
Store 1950 1951
1952: 139(ptr) AccessChain 27(data) 1945 65 47
1953:22(float64_t) CompositeExtract 1949 1
Store 1952 1953
1954: 6(int) Load 8(invocation)
1955: 146(ptr) AccessChain 27(data) 51 65
1956: 23(f64vec4) Load 1955
1957:156(f64vec3) VectorShuffle 1956 1956 0 1 2
1958:156(f64vec3) GroupNonUniformFMin 34 ExclusiveScan 1957
1959: 139(ptr) AccessChain 27(data) 1954 65 30
1960:22(float64_t) CompositeExtract 1958 0
Store 1959 1960
1961: 139(ptr) AccessChain 27(data) 1954 65 47
1962:22(float64_t) CompositeExtract 1958 1
Store 1961 1962
1963: 139(ptr) AccessChain 27(data) 1954 65 61
1964:22(float64_t) CompositeExtract 1958 2
Store 1963 1964
1965: 6(int) Load 8(invocation)
1966: 146(ptr) AccessChain 27(data) 65 65
1967: 23(f64vec4) Load 1966
1968: 23(f64vec4) GroupNonUniformFMin 34 ExclusiveScan 1967
1969: 146(ptr) AccessChain 27(data) 1965 65
Store 1969 1968
1970: 6(int) Load 8(invocation)
1971: 31(ptr) AccessChain 27(data) 29 29 30
1972: 17(float) Load 1971
1973: 17(float) GroupNonUniformFMax 34 ExclusiveScan 1972
1974: 31(ptr) AccessChain 27(data) 1970 29 30
Store 1974 1973
1975: 6(int) Load 8(invocation)
1976: 40(ptr) AccessChain 27(data) 38 29
1977: 18(fvec4) Load 1976
1978: 39(fvec2) VectorShuffle 1977 1977 0 1
1979: 39(fvec2) GroupNonUniformFMax 34 ExclusiveScan 1978
1980: 31(ptr) AccessChain 27(data) 1975 29 30
1981: 17(float) CompositeExtract 1979 0
Store 1980 1981
1982: 31(ptr) AccessChain 27(data) 1975 29 47
1983: 17(float) CompositeExtract 1979 1
Store 1982 1983
1984: 6(int) Load 8(invocation)
1985: 40(ptr) AccessChain 27(data) 51 29
1986: 18(fvec4) Load 1985
1987: 52(fvec3) VectorShuffle 1986 1986 0 1 2
1988: 52(fvec3) GroupNonUniformFMax 34 ExclusiveScan 1987
1989: 31(ptr) AccessChain 27(data) 1984 29 30
1990: 17(float) CompositeExtract 1988 0
Store 1989 1990
1991: 31(ptr) AccessChain 27(data) 1984 29 47
1992: 17(float) CompositeExtract 1988 1
Store 1991 1992
1993: 31(ptr) AccessChain 27(data) 1984 29 61
1994: 17(float) CompositeExtract 1988 2
Store 1993 1994
1995: 6(int) Load 8(invocation)
1996: 40(ptr) AccessChain 27(data) 65 29
1997: 18(fvec4) Load 1996
1998: 18(fvec4) GroupNonUniformFMax 34 ExclusiveScan 1997
1999: 40(ptr) AccessChain 27(data) 1995 29
Store 1999 1998
2000: 6(int) Load 8(invocation)
2001: 71(ptr) AccessChain 27(data) 29 38 30
2002: 19(int) Load 2001
2003: 19(int) GroupNonUniformSMax 34 ExclusiveScan 2002
2004: 71(ptr) AccessChain 27(data) 2000 38 30
Store 2004 2003
2005: 6(int) Load 8(invocation)
2006: 78(ptr) AccessChain 27(data) 38 38
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
2007: 20(ivec4) Load 2006
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
2008: 77(ivec2) VectorShuffle 2007 2007 0 1
2009: 77(ivec2) GroupNonUniformSMax 34 ExclusiveScan 2008
2010: 71(ptr) AccessChain 27(data) 2005 38 30
2011: 19(int) CompositeExtract 2009 0
Store 2010 2011
2012: 71(ptr) AccessChain 27(data) 2005 38 47
2013: 19(int) CompositeExtract 2009 1
Store 2012 2013
2014: 6(int) Load 8(invocation)
2015: 78(ptr) AccessChain 27(data) 51 38
2016: 20(ivec4) Load 2015
2017: 88(ivec3) VectorShuffle 2016 2016 0 1 2
2018: 88(ivec3) GroupNonUniformSMax 34 ExclusiveScan 2017
2019: 71(ptr) AccessChain 27(data) 2014 38 30
2020: 19(int) CompositeExtract 2018 0
Store 2019 2020
2021: 71(ptr) AccessChain 27(data) 2014 38 47
2022: 19(int) CompositeExtract 2018 1
Store 2021 2022
2023: 71(ptr) AccessChain 27(data) 2014 38 61
2024: 19(int) CompositeExtract 2018 2
Store 2023 2024
2025: 6(int) Load 8(invocation)
2026: 78(ptr) AccessChain 27(data) 65 38
2027: 20(ivec4) Load 2026
2028: 20(ivec4) GroupNonUniformSMax 34 ExclusiveScan 2027
2029: 78(ptr) AccessChain 27(data) 2025 38
Store 2029 2028
2030: 6(int) Load 8(invocation)
2031: 105(ptr) AccessChain 27(data) 29 51 30
2032: 6(int) Load 2031
2033: 6(int) GroupNonUniformUMax 34 ExclusiveScan 2032
2034: 105(ptr) AccessChain 27(data) 2030 51 30
Store 2034 2033
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
2035: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
2036: 112(ptr) AccessChain 27(data) 38 51
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
2037: 21(ivec4) Load 2036
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
2038: 111(ivec2) VectorShuffle 2037 2037 0 1
2039: 111(ivec2) GroupNonUniformUMax 34 ExclusiveScan 2038
2040: 105(ptr) AccessChain 27(data) 2035 51 30
2041: 6(int) CompositeExtract 2039 0
Store 2040 2041
2042: 105(ptr) AccessChain 27(data) 2035 51 47
2043: 6(int) CompositeExtract 2039 1
Store 2042 2043
2044: 6(int) Load 8(invocation)
2045: 112(ptr) AccessChain 27(data) 51 51
2046: 21(ivec4) Load 2045
2047: 122(ivec3) VectorShuffle 2046 2046 0 1 2
2048: 122(ivec3) GroupNonUniformUMax 34 ExclusiveScan 2047
2049: 105(ptr) AccessChain 27(data) 2044 51 30
2050: 6(int) CompositeExtract 2048 0
Store 2049 2050
2051: 105(ptr) AccessChain 27(data) 2044 51 47
2052: 6(int) CompositeExtract 2048 1
Store 2051 2052
2053: 105(ptr) AccessChain 27(data) 2044 51 61
2054: 6(int) CompositeExtract 2048 2
Store 2053 2054
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
2055: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
2056: 112(ptr) AccessChain 27(data) 65 51
2057: 21(ivec4) Load 2056
2058: 21(ivec4) GroupNonUniformUMax 34 ExclusiveScan 2057
2059: 112(ptr) AccessChain 27(data) 2055 51
Store 2059 2058
2060: 6(int) Load 8(invocation)
2061: 139(ptr) AccessChain 27(data) 29 65 30
2062:22(float64_t) Load 2061
2063:22(float64_t) GroupNonUniformFMax 34 ExclusiveScan 2062
2064: 139(ptr) AccessChain 27(data) 2060 65 30
Store 2064 2063
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
2065: 6(int) Load 8(invocation)
Generate separate stores for partially swizzled memory stores Full vector and fully specified vector swizzle stores are not affected by this change, only partial swizzles ie swizzles with fewer components than the vector being stored to. Previously the vector being stored to loaded and any components not specified in the swizzle were used to create a full store to the vector. While this change generates more SPIR-V instructions, it is necessary for correctness. Fixes #2518.
2021-07-16 21:07:16 +00:00
2066: 146(ptr) AccessChain 27(data) 38 65
2067: 23(f64vec4) Load 2066
2068:145(f64vec2) VectorShuffle 2067 2067 0 1
2069:145(f64vec2) GroupNonUniformFMax 34 ExclusiveScan 2068
2070: 139(ptr) AccessChain 27(data) 2065 65 30
2071:22(float64_t) CompositeExtract 2069 0
Store 2070 2071
2072: 139(ptr) AccessChain 27(data) 2065 65 47
2073:22(float64_t) CompositeExtract 2069 1
Store 2072 2073
2074: 6(int) Load 8(invocation)
2075: 146(ptr) AccessChain 27(data) 51 65
2076: 23(f64vec4) Load 2075
2077:156(f64vec3) VectorShuffle 2076 2076 0 1 2
2078:156(f64vec3) GroupNonUniformFMax 34 ExclusiveScan 2077
2079: 139(ptr) AccessChain 27(data) 2074 65 30
2080:22(float64_t) CompositeExtract 2078 0
Store 2079 2080
2081: 139(ptr) AccessChain 27(data) 2074 65 47
2082:22(float64_t) CompositeExtract 2078 1
Store 2081 2082
2083: 139(ptr) AccessChain 27(data) 2074 65 61
2084:22(float64_t) CompositeExtract 2078 2
Store 2083 2084
2085: 6(int) Load 8(invocation)
2086: 146(ptr) AccessChain 27(data) 65 65
2087: 23(f64vec4) Load 2086
2088: 23(f64vec4) GroupNonUniformFMax 34 ExclusiveScan 2087
2089: 146(ptr) AccessChain 27(data) 2085 65
Store 2089 2088
2090: 6(int) Load 8(invocation)
2091: 71(ptr) AccessChain 27(data) 29 38 30
2092: 19(int) Load 2091
2093: 19(int) GroupNonUniformBitwiseAnd 34 ExclusiveScan 2092
2094: 71(ptr) AccessChain 27(data) 2090 38 30
Store 2094 2093
2095: 6(int) Load 8(invocation)
2096: 78(ptr) AccessChain 27(data) 38 38
2097: 20(ivec4) Load 2096
2098: 77(ivec2) VectorShuffle 2097 2097 0 1
2099: 77(ivec2) GroupNonUniformBitwiseAnd 34 ExclusiveScan 2098
2100: 71(ptr) AccessChain 27(data) 2095 38 30
2101: 19(int) CompositeExtract 2099 0
Store 2100 2101
2102: 71(ptr) AccessChain 27(data) 2095 38 47
2103: 19(int) CompositeExtract 2099 1
Store 2102 2103
2104: 6(int) Load 8(invocation)
2105: 78(ptr) AccessChain 27(data) 51 38
2106: 20(ivec4) Load 2105
2107: 88(ivec3) VectorShuffle 2106 2106 0 1 2
2108: 88(ivec3) GroupNonUniformBitwiseAnd 34 ExclusiveScan 2107
2109: 71(ptr) AccessChain 27(data) 2104 38 30
2110: 19(int) CompositeExtract 2108 0
Store 2109 2110
2111: 71(ptr) AccessChain 27(data) 2104 38 47
2112: 19(int) CompositeExtract 2108 1
Store 2111 2112
2113: 71(ptr) AccessChain 27(data) 2104 38 61
2114: 19(int) CompositeExtract 2108 2
Store 2113 2114
2115: 6(int) Load 8(invocation)
2116: 78(ptr) AccessChain 27(data) 65 38
2117: 20(ivec4) Load 2116
2118: 20(ivec4) GroupNonUniformBitwiseAnd 34 ExclusiveScan 2117
2119: 78(ptr) AccessChain 27(data) 2115 38
Store 2119 2118
2120: 6(int) Load 8(invocation)
2121: 105(ptr) AccessChain 27(data) 29 51 30
2122: 6(int) Load 2121
2123: 6(int) GroupNonUniformBitwiseAnd 34 ExclusiveScan 2122
2124: 105(ptr) AccessChain 27(data) 2120 51 30
Store 2124 2123
2125: 6(int) Load 8(invocation)
2126: 112(ptr) AccessChain 27(data) 38 51
2127: 21(ivec4) Load 2126
2128: 111(ivec2) VectorShuffle 2127 2127 0 1
2129: 111(ivec2) GroupNonUniformBitwiseAnd 34 ExclusiveScan 2128
2130: 105(ptr) AccessChain 27(data) 2125 51 30
2131: 6(int) CompositeExtract 2129 0
Store 2130 2131
2132: 105(ptr) AccessChain 27(data) 2125 51 47
2133: 6(int) CompositeExtract 2129 1
Store 2132 2133
2134: 6(int) Load 8(invocation)
2135: 112(ptr) AccessChain 27(data) 51 51
2136: 21(ivec4) Load 2135
2137: 122(ivec3) VectorShuffle 2136 2136 0 1 2
2138: 122(ivec3) GroupNonUniformBitwiseAnd 34 ExclusiveScan 2137
2139: 105(ptr) AccessChain 27(data) 2134 51 30
2140: 6(int) CompositeExtract 2138 0
Store 2139 2140
2141: 105(ptr) AccessChain 27(data) 2134 51 47
2142: 6(int) CompositeExtract 2138 1
Store 2141 2142
2143: 105(ptr) AccessChain 27(data) 2134 51 61
2144: 6(int) CompositeExtract 2138 2
Store 2143 2144
2145: 6(int) Load 8(invocation)
2146: 112(ptr) AccessChain 27(data) 65 51
2147: 21(ivec4) Load 2146
2148: 21(ivec4) GroupNonUniformBitwiseAnd 34 ExclusiveScan 2147
2149: 112(ptr) AccessChain 27(data) 2145 51
Store 2149 2148
2150: 6(int) Load 8(invocation)
2151: 71(ptr) AccessChain 27(data) 29 38 30
2152: 19(int) Load 2151
2153: 595(bool) SLessThan 2152 29
2154: 595(bool) GroupNonUniformLogicalAnd 34 ExclusiveScan 2153
2155: 19(int) Select 2154 38 29
2156: 71(ptr) AccessChain 27(data) 2150 38 30
Store 2156 2155
2157: 6(int) Load 8(invocation)
2158: 78(ptr) AccessChain 27(data) 38 38
2159: 20(ivec4) Load 2158
2160: 77(ivec2) VectorShuffle 2159 2159 0 1
2161: 605(bvec2) SLessThan 2160 604
2162: 605(bvec2) GroupNonUniformLogicalAnd 34 ExclusiveScan 2161
2163: 77(ivec2) Select 2162 608 604
2164: 71(ptr) AccessChain 27(data) 2157 38 30
2165: 19(int) CompositeExtract 2163 0
Store 2164 2165
2166: 71(ptr) AccessChain 27(data) 2157 38 47
2167: 19(int) CompositeExtract 2163 1
Store 2166 2167
2168: 6(int) Load 8(invocation)
2169: 78(ptr) AccessChain 27(data) 38 38
2170: 20(ivec4) Load 2169
2171: 88(ivec3) VectorShuffle 2170 2170 0 1 2
2172: 619(bvec3) SLessThan 2171 618
2173: 619(bvec3) GroupNonUniformLogicalAnd 34 ExclusiveScan 2172
2174: 88(ivec3) Select 2173 622 618
2175: 71(ptr) AccessChain 27(data) 2168 38 30
2176: 19(int) CompositeExtract 2174 0
Store 2175 2176
2177: 71(ptr) AccessChain 27(data) 2168 38 47
2178: 19(int) CompositeExtract 2174 1
Store 2177 2178
2179: 71(ptr) AccessChain 27(data) 2168 38 61
2180: 19(int) CompositeExtract 2174 2
Store 2179 2180
2181: 6(int) Load 8(invocation)
2182: 78(ptr) AccessChain 27(data) 38 38
2183: 20(ivec4) Load 2182
2184: 634(bvec4) SLessThan 2183 633
2185: 634(bvec4) GroupNonUniformLogicalAnd 34 ExclusiveScan 2184
2186: 20(ivec4) Select 2185 637 633
2187: 78(ptr) AccessChain 27(data) 2181 38
Store 2187 2186
2188: 6(int) Load 8(invocation)
2189: 71(ptr) AccessChain 27(data) 29 38 30
2190: 19(int) Load 2189
2191: 19(int) GroupNonUniformBitwiseOr 34 ExclusiveScan 2190
2192: 71(ptr) AccessChain 27(data) 2188 38 30
Store 2192 2191
2193: 6(int) Load 8(invocation)
2194: 78(ptr) AccessChain 27(data) 38 38
2195: 20(ivec4) Load 2194
2196: 77(ivec2) VectorShuffle 2195 2195 0 1
2197: 77(ivec2) GroupNonUniformBitwiseOr 34 ExclusiveScan 2196
2198: 71(ptr) AccessChain 27(data) 2193 38 30
2199: 19(int) CompositeExtract 2197 0
Store 2198 2199
2200: 71(ptr) AccessChain 27(data) 2193 38 47
2201: 19(int) CompositeExtract 2197 1
Store 2200 2201
2202: 6(int) Load 8(invocation)
2203: 78(ptr) AccessChain 27(data) 51 38
2204: 20(ivec4) Load 2203
2205: 88(ivec3) VectorShuffle 2204 2204 0 1 2
2206: 88(ivec3) GroupNonUniformBitwiseOr 34 ExclusiveScan 2205
2207: 71(ptr) AccessChain 27(data) 2202 38 30
2208: 19(int) CompositeExtract 2206 0
Store 2207 2208
2209: 71(ptr) AccessChain 27(data) 2202 38 47
2210: 19(int) CompositeExtract 2206 1
Store 2209 2210
2211: 71(ptr) AccessChain 27(data) 2202 38 61
2212: 19(int) CompositeExtract 2206 2
Store 2211 2212
2213: 6(int) Load 8(invocation)
2214: 78(ptr) AccessChain 27(data) 65 38
2215: 20(ivec4) Load 2214
2216: 20(ivec4) GroupNonUniformBitwiseOr 34 ExclusiveScan 2215
2217: 78(ptr) AccessChain 27(data) 2213 38
Store 2217 2216
2218: 6(int) Load 8(invocation)
2219: 105(ptr) AccessChain 27(data) 29 51 30
2220: 6(int) Load 2219
2221: 6(int) GroupNonUniformBitwiseOr 34 ExclusiveScan 2220
2222: 105(ptr) AccessChain 27(data) 2218 51 30
Store 2222 2221
2223: 6(int) Load 8(invocation)
2224: 112(ptr) AccessChain 27(data) 38 51
2225: 21(ivec4) Load 2224
2226: 111(ivec2) VectorShuffle 2225 2225 0 1
2227: 111(ivec2) GroupNonUniformBitwiseOr 34 ExclusiveScan 2226
2228: 105(ptr) AccessChain 27(data) 2223 51 30
2229: 6(int) CompositeExtract 2227 0
Store 2228 2229
2230: 105(ptr) AccessChain 27(data) 2223 51 47
2231: 6(int) CompositeExtract 2227 1
Store 2230 2231
2232: 6(int) Load 8(invocation)
2233: 112(ptr) AccessChain 27(data) 51 51
2234: 21(ivec4) Load 2233
2235: 122(ivec3) VectorShuffle 2234 2234 0 1 2
2236: 122(ivec3) GroupNonUniformBitwiseOr 34 ExclusiveScan 2235
2237: 105(ptr) AccessChain 27(data) 2232 51 30
2238: 6(int) CompositeExtract 2236 0
Store 2237 2238
2239: 105(ptr) AccessChain 27(data) 2232 51 47
2240: 6(int) CompositeExtract 2236 1
Store 2239 2240
2241: 105(ptr) AccessChain 27(data) 2232 51 61
2242: 6(int) CompositeExtract 2236 2
Store 2241 2242
2243: 6(int) Load 8(invocation)
2244: 112(ptr) AccessChain 27(data) 65 51
2245: 21(ivec4) Load 2244
2246: 21(ivec4) GroupNonUniformBitwiseOr 34 ExclusiveScan 2245
2247: 112(ptr) AccessChain 27(data) 2243 51
Store 2247 2246
2248: 6(int) Load 8(invocation)
2249: 71(ptr) AccessChain 27(data) 29 38 30
2250: 19(int) Load 2249
2251: 595(bool) SLessThan 2250 29
2252: 595(bool) GroupNonUniformLogicalOr 34 ExclusiveScan 2251
2253: 19(int) Select 2252 38 29
2254: 71(ptr) AccessChain 27(data) 2248 38 30
Store 2254 2253
2255: 6(int) Load 8(invocation)
2256: 78(ptr) AccessChain 27(data) 38 38
2257: 20(ivec4) Load 2256
2258: 77(ivec2) VectorShuffle 2257 2257 0 1
2259: 605(bvec2) SLessThan 2258 604
2260: 605(bvec2) GroupNonUniformLogicalOr 34 ExclusiveScan 2259
2261: 77(ivec2) Select 2260 608 604
2262: 71(ptr) AccessChain 27(data) 2255 38 30
2263: 19(int) CompositeExtract 2261 0
Store 2262 2263
2264: 71(ptr) AccessChain 27(data) 2255 38 47
2265: 19(int) CompositeExtract 2261 1
Store 2264 2265
2266: 6(int) Load 8(invocation)
2267: 78(ptr) AccessChain 27(data) 38 38
2268: 20(ivec4) Load 2267
2269: 88(ivec3) VectorShuffle 2268 2268 0 1 2
2270: 619(bvec3) SLessThan 2269 618
2271: 619(bvec3) GroupNonUniformLogicalOr 34 ExclusiveScan 2270
2272: 88(ivec3) Select 2271 622 618
2273: 71(ptr) AccessChain 27(data) 2266 38 30
2274: 19(int) CompositeExtract 2272 0
Store 2273 2274
2275: 71(ptr) AccessChain 27(data) 2266 38 47
2276: 19(int) CompositeExtract 2272 1
Store 2275 2276
2277: 71(ptr) AccessChain 27(data) 2266 38 61
2278: 19(int) CompositeExtract 2272 2
Store 2277 2278
2279: 6(int) Load 8(invocation)
2280: 78(ptr) AccessChain 27(data) 38 38
2281: 20(ivec4) Load 2280
2282: 634(bvec4) SLessThan 2281 633
2283: 634(bvec4) GroupNonUniformLogicalOr 34 ExclusiveScan 2282
2284: 20(ivec4) Select 2283 637 633
2285: 78(ptr) AccessChain 27(data) 2279 38
Store 2285 2284
2286: 6(int) Load 8(invocation)
2287: 71(ptr) AccessChain 27(data) 29 38 30
2288: 19(int) Load 2287
2289: 19(int) GroupNonUniformBitwiseXor 34 ExclusiveScan 2288
2290: 71(ptr) AccessChain 27(data) 2286 38 30
Store 2290 2289
2291: 6(int) Load 8(invocation)
2292: 78(ptr) AccessChain 27(data) 38 38
2293: 20(ivec4) Load 2292
2294: 77(ivec2) VectorShuffle 2293 2293 0 1
2295: 77(ivec2) GroupNonUniformBitwiseXor 34 ExclusiveScan 2294
2296: 71(ptr) AccessChain 27(data) 2291 38 30
2297: 19(int) CompositeExtract 2295 0
Store 2296 2297
2298: 71(ptr) AccessChain 27(data) 2291 38 47
2299: 19(int) CompositeExtract 2295 1
Store 2298 2299
2300: 6(int) Load 8(invocation)
2301: 78(ptr) AccessChain 27(data) 51 38
2302: 20(ivec4) Load 2301
2303: 88(ivec3) VectorShuffle 2302 2302 0 1 2
2304: 88(ivec3) GroupNonUniformBitwiseXor 34 ExclusiveScan 2303
2305: 71(ptr) AccessChain 27(data) 2300 38 30
2306: 19(int) CompositeExtract 2304 0
Store 2305 2306
2307: 71(ptr) AccessChain 27(data) 2300 38 47
2308: 19(int) CompositeExtract 2304 1
Store 2307 2308
2309: 71(ptr) AccessChain 27(data) 2300 38 61
2310: 19(int) CompositeExtract 2304 2
Store 2309 2310
2311: 6(int) Load 8(invocation)
2312: 78(ptr) AccessChain 27(data) 65 38
2313: 20(ivec4) Load 2312
2314: 20(ivec4) GroupNonUniformBitwiseXor 34 ExclusiveScan 2313
2315: 78(ptr) AccessChain 27(data) 2311 38
Store 2315 2314
2316: 6(int) Load 8(invocation)
2317: 105(ptr) AccessChain 27(data) 29 51 30
2318: 6(int) Load 2317
2319: 6(int) GroupNonUniformBitwiseXor 34 ExclusiveScan 2318
2320: 105(ptr) AccessChain 27(data) 2316 51 30
Store 2320 2319
2321: 6(int) Load 8(invocation)
2322: 112(ptr) AccessChain 27(data) 38 51
2323: 21(ivec4) Load 2322
2324: 111(ivec2) VectorShuffle 2323 2323 0 1
2325: 111(ivec2) GroupNonUniformBitwiseXor 34 ExclusiveScan 2324
2326: 105(ptr) AccessChain 27(data) 2321 51 30
2327: 6(int) CompositeExtract 2325 0
Store 2326 2327
2328: 105(ptr) AccessChain 27(data) 2321 51 47
2329: 6(int) CompositeExtract 2325 1
Store 2328 2329
2330: 6(int) Load 8(invocation)
2331: 112(ptr) AccessChain 27(data) 51 51
2332: 21(ivec4) Load 2331
2333: 122(ivec3) VectorShuffle 2332 2332 0 1 2
2334: 122(ivec3) GroupNonUniformBitwiseXor 34 ExclusiveScan 2333
2335: 105(ptr) AccessChain 27(data) 2330 51 30
2336: 6(int) CompositeExtract 2334 0
Store 2335 2336
2337: 105(ptr) AccessChain 27(data) 2330 51 47
2338: 6(int) CompositeExtract 2334 1
Store 2337 2338
2339: 105(ptr) AccessChain 27(data) 2330 51 61
2340: 6(int) CompositeExtract 2334 2
Store 2339 2340
2341: 6(int) Load 8(invocation)
2342: 112(ptr) AccessChain 27(data) 65 51
2343: 21(ivec4) Load 2342
2344: 21(ivec4) GroupNonUniformBitwiseXor 34 ExclusiveScan 2343
2345: 112(ptr) AccessChain 27(data) 2341 51
Store 2345 2344
2346: 6(int) Load 8(invocation)
2347: 71(ptr) AccessChain 27(data) 29 38 30
2348: 19(int) Load 2347
2349: 595(bool) SLessThan 2348 29
2350: 595(bool) GroupNonUniformLogicalXor 34 ExclusiveScan 2349
2351: 19(int) Select 2350 38 29
2352: 71(ptr) AccessChain 27(data) 2346 38 30
Store 2352 2351
2353: 6(int) Load 8(invocation)
2354: 78(ptr) AccessChain 27(data) 38 38
2355: 20(ivec4) Load 2354
2356: 77(ivec2) VectorShuffle 2355 2355 0 1
2357: 605(bvec2) SLessThan 2356 604
2358: 605(bvec2) GroupNonUniformLogicalXor 34 ExclusiveScan 2357
2359: 77(ivec2) Select 2358 608 604
2360: 71(ptr) AccessChain 27(data) 2353 38 30
2361: 19(int) CompositeExtract 2359 0
Store 2360 2361
2362: 71(ptr) AccessChain 27(data) 2353 38 47
2363: 19(int) CompositeExtract 2359 1
Store 2362 2363
2364: 6(int) Load 8(invocation)
2365: 78(ptr) AccessChain 27(data) 38 38
2366: 20(ivec4) Load 2365
2367: 88(ivec3) VectorShuffle 2366 2366 0 1 2
2368: 619(bvec3) SLessThan 2367 618
2369: 619(bvec3) GroupNonUniformLogicalXor 34 ExclusiveScan 2368
2370: 88(ivec3) Select 2369 622 618
2371: 71(ptr) AccessChain 27(data) 2364 38 30
2372: 19(int) CompositeExtract 2370 0
Store 2371 2372
2373: 71(ptr) AccessChain 27(data) 2364 38 47
2374: 19(int) CompositeExtract 2370 1
Store 2373 2374
2375: 71(ptr) AccessChain 27(data) 2364 38 61
2376: 19(int) CompositeExtract 2370 2
Store 2375 2376
2377: 6(int) Load 8(invocation)
2378: 78(ptr) AccessChain 27(data) 38 38
2379: 20(ivec4) Load 2378
2380: 634(bvec4) SLessThan 2379 633
2381: 634(bvec4) GroupNonUniformLogicalXor 34 ExclusiveScan 2380
2382: 20(ivec4) Select 2381 637 633
2383: 78(ptr) AccessChain 27(data) 2377 38
Store 2383 2382
SPV: Implement Vulkan 1.1 features and extensions.
2018-03-06 23:12:04 +00:00
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FunctionEnd
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