AuroraMiddleware/qt5base-lts
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add x86 arch detection support for AVX512 and SHA instructions

Browse Source 
The flags come from GCC commit 201219:
http://gcc.gnu.org/viewcvs/gcc/branches/avx512/gcc/config/i386/i386-c.c?limit_changes=0&r1=201219&r2=201218&pathrev=201219

Clang and ICC don't seem to have support for this yet.

Change-Id: Ic941654a5c56ed110d0e754e436a92dc5deaeb17
Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@digia.com>
This commit is contained in:
Thiago Macieira 2013-08-06 16:24:57 -07:00 committed by The Qt Project
parent 065cff8311
commit 04bc63f2d6
1 changed files with 20 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
config.tests/arch/arch.cpp
View File

@ -106,6 +106,22 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:"
// AVX 2, Intel Core 4th Generation ("Haswell")
" avx2"
#endif
#ifdef __AVX512F__
// AVX512 Foundation, Intel Xeon Phi codename "Knights Landing"
" avx512f"
#endif
#ifdef __AVX512CD__
// AVX512 Conflict Detection, Intel Xeon Phi codename "Knights Landing"
" avx512cd"
#endif
#ifdef __AVX512ER__
// AVX512 Exponentiation & Reciprocal, Intel Xeon Phi codename "Knights Landing"
" avx512ef"
#endif
#ifdef __AVX512PF__
// AVX512 Prefetch, Intel Xeon Phi codename "Knights Landing"
" avx512pf"
#endif
#ifdef __BMI__
// Bit Manipulation Instructions 1, Intel Core 4th Generation ("Haswell"), AMD "Bulldozer 2"
" bmi"
@ -169,6 +185,10 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:"
// Random number generator, Intel Core 3rd Generation ("Ivy Bridge")
" rdrnd"
#endif
#ifdef __SHA__
// SHA-1 and SHA-256 instructions, Intel processor TBA
" sha"
#endif
#if defined(__SSE__) || (defined(_M_IX86_FP) && _M_IX86_FP >= 1) || defined(_M_X64)
// Streaming SIMD Extensions, Intel Pentium III, AMD Athlon
" sse"