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skia2/tests/SkVMTest.cpp

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sketch an skvm With all the thinking around a stack-based interpreter, I figured I'd sketch out some ideas for a register VM too. I kind of have the hunch that this is the direction that will actually let us replace large amounts of Skia's CPU backend with an efficient interpreter or JIT. Change-Id: Ia2b5ba4a3fc27556f5b6ba95cd1ace46d3217403 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/216665 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-05-29 17:57:54 +00:00
/*
* Copyright 2019 Google LLC
*
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#include "include/core/SkColorPriv.h"
#include "include/private/SkColorData.h"
#include "src/core/SkVM.h"
#include "tests/Test.h"
streamline SkVM test rebaselining - keep expectations in resources/ - overwrite automatically if needed so we can see the diff in Git Change-Id: I2486b127ebcc7f40332fd0462e38b1af04d3e32b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218038 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-03 21:27:46 +00:00
#include "tools/Resources.h"
centralize test/bench SkVM builders Eliminate the duplicate functionality, and better testing for the bench builders. Change-Id: If20e52107738903f854aec431416e573d7a7d640 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218041 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-03 22:10:59 +00:00
#include "tools/SkVMBuilders.h"
sketch an skvm With all the thinking around a stack-based interpreter, I figured I'd sketch out some ideas for a register VM too. I kind of have the hunch that this is the direction that will actually let us replace large amounts of Skia's CPU backend with an efficient interpreter or JIT. Change-Id: Ia2b5ba4a3fc27556f5b6ba95cd1ace46d3217403 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/216665 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-05-29 17:57:54 +00:00
centralize test/bench SkVM builders Eliminate the duplicate functionality, and better testing for the bench builders. Change-Id: If20e52107738903f854aec431416e573d7a7d640 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218041 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-03 22:10:59 +00:00
using Fmt = SrcoverBuilder_F32::Fmt;
sketch an skvm With all the thinking around a stack-based interpreter, I figured I'd sketch out some ideas for a register VM too. I kind of have the hunch that this is the direction that will actually let us replace large amounts of Skia's CPU backend with an efficient interpreter or JIT. Change-Id: Ia2b5ba4a3fc27556f5b6ba95cd1ace46d3217403 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/216665 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-05-29 17:57:54 +00:00
const char* fmt_name(Fmt fmt) {
switch (fmt) {
centralize test/bench SkVM builders Eliminate the duplicate functionality, and better testing for the bench builders. Change-Id: If20e52107738903f854aec431416e573d7a7d640 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218041 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-03 22:10:59 +00:00
case Fmt::A8: return "A8";
case Fmt::G8: return "G8";
case Fmt::RGBA_8888: return "RGBA_8888";
sketch an skvm With all the thinking around a stack-based interpreter, I figured I'd sketch out some ideas for a register VM too. I kind of have the hunch that this is the direction that will actually let us replace large amounts of Skia's CPU backend with an efficient interpreter or JIT. Change-Id: Ia2b5ba4a3fc27556f5b6ba95cd1ace46d3217403 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/216665 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-05-29 17:57:54 +00:00
}
return "";
}
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
namespace {
using namespace skvm;
struct V { Val id; };
struct R { Reg id; };
struct Shift { int bits; };
struct Splat { int bits; };
struct Hex { int bits; };
static void write(SkWStream* o, const char* s) {
o->writeText(s);
}
static void write(SkWStream* o, Arg a) {
write(o, "arg(");
o->writeDecAsText(a.ix);
write(o, ")");
}
static void write(SkWStream* o, V v) {
write(o, "v");
o->writeDecAsText(v.id);
}
static void write(SkWStream* o, R r) {
write(o, "r");
o->writeDecAsText(r.id);
}
static void write(SkWStream* o, Shift s) {
o->writeDecAsText(s.bits);
}
static void write(SkWStream* o, Splat s) {
float f;
memcpy(&f, &s.bits, 4);
o->writeHexAsText(s.bits);
write(o, " (");
o->writeScalarAsText(f);
write(o, ")");
}
static void write(SkWStream* o, Hex h) {
o->writeHexAsText(h.bits);
}
template <typename T, typename... Ts>
static void write(SkWStream* o, T first, Ts... rest) {
write(o, first);
write(o, " ");
write(o, rest...);
}
move death back into Builder::Instruction I find myself passing around parallel vectors of Builder::Instructions and deaths so often that it just makes more sense practically to store them together. It's a little awkward that the values are only useful after calling done(), but I can live with that. Get a little more careful about mutation, passing Builder::Instructions by const&. Instead of extending lifetimes of live hoisted instructions, just check for them in maybe_recycle_register() instead. Change-Id: I1cb9e25c1a7c46a250c2271334821be8535353bf Reviewed-on: https://skia-review.googlesource.com/c/skia/+/228367 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-18 15:36:45 +00:00
static void dump_builder(const Builder& builder, SkWStream* o) {
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
const std::vector<Builder::Instruction> program = builder.program();
o->writeDecAsText(program.size());
o->writeText(" values:\n");
for (Val id = 0; id < (Val)program.size(); id++) {
const Builder::Instruction& inst = program[id];
Op op = inst.op;
Val x = inst.x,
y = inst.y,
z = inst.z;
int imm = inst.imm;
move hoist analysis back into Builder Even if a JIT ultimately doesn't end up hoisting any values, it's going to want this information while it decides. Writing it in one place also ensures we only get it wrong in one place... I'm no_ extending the lifetime of hoisted instructions here in Builder. That's something to leave to the backend so they have the flexibility of which of these values to hoist, if any. If they don't hoist, they'll need to know when the value dies. Moving this information back here lets the test expectation goldens reflect the hoist bit again too. Kind of nice. Change-Id: Ib165ca898a97c1d822cb28fe24f15bae4d570a17 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229024 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-22 18:44:54 +00:00
write(o, inst.death == 0 ? "☠️ " :
inst.hoist ? "↑ " : " ");
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
switch (op) {
case Op::store8: write(o, "store8" , Arg{imm}, V{x}); break;
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
case Op::store16: write(o, "store16", Arg{imm}, V{x}); break;
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
case Op::store32: write(o, "store32", Arg{imm}, V{x}); break;
case Op::load8: write(o, V{id}, "= load8" , Arg{imm}); break;
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
case Op::load16: write(o, V{id}, "= load16", Arg{imm}); break;
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
case Op::load32: write(o, V{id}, "= load32", Arg{imm}); break;
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
case Op::gather8: write(o, V{id}, "= gather8" , Arg{imm}, V{x}); break;
case Op::gather16: write(o, V{id}, "= gather16", Arg{imm}, V{x}); break;
case Op::gather32: write(o, V{id}, "= gather32", Arg{imm}, V{x}); break;
case Op::uniform8: write(o, V{id}, "= uniform8" , Arg{imm & 0xffff}, Hex{imm>>16}); break;
case Op::uniform16: write(o, V{id}, "= uniform16", Arg{imm & 0xffff}, Hex{imm>>16}); break;
case Op::uniform32: write(o, V{id}, "= uniform32", Arg{imm & 0xffff}, Hex{imm>>16}); break;
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
case Op::splat: write(o, V{id}, "= splat", Splat{imm}); break;
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
case Op::add_f32: write(o, V{id}, "= add_f32", V{x}, V{y} ); break;
case Op::sub_f32: write(o, V{id}, "= sub_f32", V{x}, V{y} ); break;
case Op::mul_f32: write(o, V{id}, "= mul_f32", V{x}, V{y} ); break;
case Op::div_f32: write(o, V{id}, "= div_f32", V{x}, V{y} ); break;
case Op::mad_f32: write(o, V{id}, "= mad_f32", V{x}, V{y}, V{z}); break;
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
case Op:: eq_f32: write(o, V{id}, "= eq_f32", V{x}, V{y}); break;
case Op::neq_f32: write(o, V{id}, "= neq_f32", V{x}, V{y}); break;
case Op:: lt_f32: write(o, V{id}, "= lt_f32", V{x}, V{y}); break;
case Op::lte_f32: write(o, V{id}, "= lte_f32", V{x}, V{y}); break;
case Op:: gt_f32: write(o, V{id}, "= gt_f32", V{x}, V{y}); break;
case Op::gte_f32: write(o, V{id}, "= gte_f32", V{x}, V{y}); break;
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
case Op::add_i32: write(o, V{id}, "= add_i32", V{x}, V{y}); break;
case Op::sub_i32: write(o, V{id}, "= sub_i32", V{x}, V{y}); break;
case Op::mul_i32: write(o, V{id}, "= mul_i32", V{x}, V{y}); break;
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
case Op::shl_i32: write(o, V{id}, "= shl_i32", V{x}, Shift{imm}); break;
case Op::shr_i32: write(o, V{id}, "= shr_i32", V{x}, Shift{imm}); break;
case Op::sra_i32: write(o, V{id}, "= sra_i32", V{x}, Shift{imm}); break;
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
case Op:: eq_i32: write(o, V{id}, "= eq_i32", V{x}, V{y}); break;
case Op::neq_i32: write(o, V{id}, "= neq_i32", V{x}, V{y}); break;
case Op:: lt_i32: write(o, V{id}, "= lt_i32", V{x}, V{y}); break;
case Op::lte_i32: write(o, V{id}, "= lte_i32", V{x}, V{y}); break;
case Op:: gt_i32: write(o, V{id}, "= gt_i32", V{x}, V{y}); break;
case Op::gte_i32: write(o, V{id}, "= gte_i32", V{x}, V{y}); break;
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
case Op::add_i16x2: write(o, V{id}, "= add_i16x2", V{x}, V{y}); break;
case Op::sub_i16x2: write(o, V{id}, "= sub_i16x2", V{x}, V{y}); break;
case Op::mul_i16x2: write(o, V{id}, "= mul_i16x2", V{x}, V{y}); break;
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
case Op::shl_i16x2: write(o, V{id}, "= shl_i16x2", V{x}, Shift{imm}); break;
case Op::shr_i16x2: write(o, V{id}, "= shr_i16x2", V{x}, Shift{imm}); break;
case Op::sra_i16x2: write(o, V{id}, "= sra_i16x2", V{x}, Shift{imm}); break;
case Op:: eq_i16x2: write(o, V{id}, "= eq_i16x2", V{x}, V{y}); break;
case Op::neq_i16x2: write(o, V{id}, "= neq_i16x2", V{x}, V{y}); break;
case Op:: lt_i16x2: write(o, V{id}, "= lt_i16x2", V{x}, V{y}); break;
case Op::lte_i16x2: write(o, V{id}, "= lte_i16x2", V{x}, V{y}); break;
case Op:: gt_i16x2: write(o, V{id}, "= gt_i16x2", V{x}, V{y}); break;
case Op::gte_i16x2: write(o, V{id}, "= gte_i16x2", V{x}, V{y}); break;
case Op::bit_and : write(o, V{id}, "= bit_and" , V{x}, V{y} ); break;
case Op::bit_or : write(o, V{id}, "= bit_or" , V{x}, V{y} ); break;
case Op::bit_xor : write(o, V{id}, "= bit_xor" , V{x}, V{y} ); break;
case Op::bit_clear: write(o, V{id}, "= bit_clear", V{x}, V{y} ); break;
case Op::select : write(o, V{id}, "= select" , V{x}, V{y}, V{z}); break;
case Op::bytes: write(o, V{id}, "= bytes", V{x}, Hex{imm}); break;
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
case Op::extract: write(o, V{id}, "= extract", V{x}, Shift{imm}, V{y}); break;
case Op::pack: write(o, V{id}, "= pack", V{x}, V{y}, Shift{imm}); break;
case Op::to_f32: write(o, V{id}, "= to_f32", V{x}); break;
case Op::to_i32: write(o, V{id}, "= to_i32", V{x}); break;
}
write(o, "\n");
}
}
move death back into Builder::Instruction I find myself passing around parallel vectors of Builder::Instructions and deaths so often that it just makes more sense practically to store them together. It's a little awkward that the values are only useful after calling done(), but I can live with that. Get a little more careful about mutation, passing Builder::Instructions by const&. Instead of extending lifetimes of live hoisted instructions, just check for them in maybe_recycle_register() instead. Change-Id: I1cb9e25c1a7c46a250c2271334821be8535353bf Reviewed-on: https://skia-review.googlesource.com/c/skia/+/228367 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-18 15:36:45 +00:00
static void dump_program(const Program& program, SkWStream* o) {
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
const std::vector<Program::Instruction> instructions = program.instructions();
const int nregs = program.nregs();
const int loop = program.loop();
o->writeDecAsText(nregs);
o->writeText(" registers, ");
o->writeDecAsText(instructions.size());
o->writeText(" instructions:\n");
for (int i = 0; i < (int)instructions.size(); i++) {
if (i == loop) {
write(o, "loop:\n");
}
const Program::Instruction& inst = instructions[i];
Op op = inst.op;
Reg d = inst.d,
x = inst.x,
y = inst.y,
z = inst.z;
int imm = inst.imm;
switch (op) {
case Op::store8: write(o, "store8" , Arg{imm}, R{x}); break;
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
case Op::store16: write(o, "store16", Arg{imm}, R{x}); break;
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
case Op::store32: write(o, "store32", Arg{imm}, R{x}); break;
case Op::load8: write(o, R{d}, "= load8" , Arg{imm}); break;
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
case Op::load16: write(o, R{d}, "= load16", Arg{imm}); break;
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
case Op::load32: write(o, R{d}, "= load32", Arg{imm}); break;
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
case Op::gather8: write(o, R{d}, "= gather8" , Arg{imm}, R{x}); break;
case Op::gather16: write(o, R{d}, "= gather16", Arg{imm}, R{x}); break;
case Op::gather32: write(o, R{d}, "= gather32", Arg{imm}, R{x}); break;
case Op::uniform8: write(o, R{d}, "= uniform8" , Arg{imm & 0xffff}, Hex{imm>>16}); break;
case Op::uniform16: write(o, R{d}, "= uniform16", Arg{imm & 0xffff}, Hex{imm>>16}); break;
case Op::uniform32: write(o, R{d}, "= uniform32", Arg{imm & 0xffff}, Hex{imm>>16}); break;
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
case Op::splat: write(o, R{d}, "= splat", Splat{imm}); break;
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
case Op::add_f32: write(o, R{d}, "= add_f32", R{x}, R{y} ); break;
case Op::sub_f32: write(o, R{d}, "= sub_f32", R{x}, R{y} ); break;
case Op::mul_f32: write(o, R{d}, "= mul_f32", R{x}, R{y} ); break;
case Op::div_f32: write(o, R{d}, "= div_f32", R{x}, R{y} ); break;
case Op::mad_f32: write(o, R{d}, "= mad_f32", R{x}, R{y}, R{z}); break;
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
case Op:: eq_f32: write(o, R{d}, "= eq_f32", R{x}, R{y}); break;
case Op::neq_f32: write(o, R{d}, "= neq_f32", R{x}, R{y}); break;
case Op:: lt_f32: write(o, R{d}, "= lt_f32", R{x}, R{y}); break;
case Op::lte_f32: write(o, R{d}, "= lte_f32", R{x}, R{y}); break;
case Op:: gt_f32: write(o, R{d}, "= gt_f32", R{x}, R{y}); break;
case Op::gte_f32: write(o, R{d}, "= gte_f32", R{x}, R{y}); break;
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
case Op::add_i32: write(o, R{d}, "= add_i32", R{x}, R{y}); break;
case Op::sub_i32: write(o, R{d}, "= sub_i32", R{x}, R{y}); break;
case Op::mul_i32: write(o, R{d}, "= mul_i32", R{x}, R{y}); break;
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
case Op::shl_i32: write(o, R{d}, "= shl_i32", R{x}, Shift{imm}); break;
case Op::shr_i32: write(o, R{d}, "= shr_i32", R{x}, Shift{imm}); break;
case Op::sra_i32: write(o, R{d}, "= sra_i32", R{x}, Shift{imm}); break;
case Op:: eq_i32: write(o, R{d}, "= eq_i32", R{x}, R{y}); break;
case Op::neq_i32: write(o, R{d}, "= neq_i32", R{x}, R{y}); break;
case Op:: lt_i32: write(o, R{d}, "= lt_i32", R{x}, R{y}); break;
case Op::lte_i32: write(o, R{d}, "= lte_i32", R{x}, R{y}); break;
case Op:: gt_i32: write(o, R{d}, "= gt_i32", R{x}, R{y}); break;
case Op::gte_i32: write(o, R{d}, "= gte_i32", R{x}, R{y}); break;
case Op::add_i16x2: write(o, R{d}, "= add_i16x2", R{x}, R{y}); break;
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
case Op::sub_i16x2: write(o, R{d}, "= sub_i16x2", R{x}, R{y}); break;
case Op::mul_i16x2: write(o, R{d}, "= mul_i16x2", R{x}, R{y}); break;
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
case Op::shl_i16x2: write(o, R{d}, "= shl_i16x2", R{x}, Shift{imm}); break;
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
case Op::shr_i16x2: write(o, R{d}, "= shr_i16x2", R{x}, Shift{imm}); break;
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
case Op::sra_i16x2: write(o, R{d}, "= sra_i16x2", R{x}, Shift{imm}); break;
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
case Op:: eq_i16x2: write(o, R{d}, "= eq_i16x2", R{x}, R{y}); break;
case Op::neq_i16x2: write(o, R{d}, "= neq_i16x2", R{x}, R{y}); break;
case Op:: lt_i16x2: write(o, R{d}, "= lt_i16x2", R{x}, R{y}); break;
case Op::lte_i16x2: write(o, R{d}, "= lte_i16x2", R{x}, R{y}); break;
case Op:: gt_i16x2: write(o, R{d}, "= gt_i16x2", R{x}, R{y}); break;
case Op::gte_i16x2: write(o, R{d}, "= gte_i16x2", R{x}, R{y}); break;
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
case Op::bit_and : write(o, R{d}, "= bit_and" , R{x}, R{y} ); break;
case Op::bit_or : write(o, R{d}, "= bit_or" , R{x}, R{y} ); break;
case Op::bit_xor : write(o, R{d}, "= bit_xor" , R{x}, R{y} ); break;
case Op::bit_clear: write(o, R{d}, "= bit_clear", R{x}, R{y} ); break;
case Op::select : write(o, R{d}, "= select" , R{x}, R{y}, R{z}); break;
case Op::bytes: write(o, R{d}, "= bytes", R{x}, Hex{imm}); break;
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
case Op::extract: write(o, R{d}, "= extract", R{x}, Shift{imm}, R{y}); break;
case Op::pack: write(o, R{d}, "= pack", R{x}, R{y}, Shift{imm}); break;
case Op::to_f32: write(o, R{d}, "= to_f32", R{x}); break;
case Op::to_i32: write(o, R{d}, "= to_i32", R{x}); break;
}
write(o, "\n");
}
}
move death back into Builder::Instruction I find myself passing around parallel vectors of Builder::Instructions and deaths so often that it just makes more sense practically to store them together. It's a little awkward that the values are only useful after calling done(), but I can live with that. Get a little more careful about mutation, passing Builder::Instructions by const&. Instead of extending lifetimes of live hoisted instructions, just check for them in maybe_recycle_register() instead. Change-Id: I1cb9e25c1a7c46a250c2271334821be8535353bf Reviewed-on: https://skia-review.googlesource.com/c/skia/+/228367 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-18 15:36:45 +00:00
static void dump(Builder& builder, SkWStream* o) {
skvm::Program program = builder.done();
dump_builder(builder, o);
add misc. value programs to SkVMTest.expected Noticed we were only dumping the final register programs for the integer code. Might as well also track the value programs. Change-Id: I417c5c655b632691557bbbb136dcbd3f3167af9a Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225324 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-02 20:39:23 +00:00
o->writeText("\n");
move death back into Builder::Instruction I find myself passing around parallel vectors of Builder::Instructions and deaths so often that it just makes more sense practically to store them together. It's a little awkward that the values are only useful after calling done(), but I can live with that. Get a little more careful about mutation, passing Builder::Instructions by const&. Instead of extending lifetimes of live hoisted instructions, just check for them in maybe_recycle_register() instead. Change-Id: I1cb9e25c1a7c46a250c2271334821be8535353bf Reviewed-on: https://skia-review.googlesource.com/c/skia/+/228367 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-18 15:36:45 +00:00
dump_program(program, o);
add misc. value programs to SkVMTest.expected Noticed we were only dumping the final register programs for the integer code. Might as well also track the value programs. Change-Id: I417c5c655b632691557bbbb136dcbd3f3167af9a Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225324 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-02 20:39:23 +00:00
o->writeText("\n");
}
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
} // namespace
test both JIT and interpreter Add Program::dropJIT() to allow us to proactively drop any JIT code forcing fallback on the interpreter, and use it to test both on JIT-supported platforms. Other platforms will just test the interpreter twice. Change-Id: I607d00ef3c648e66a0b3a1374b11aa82dbfff70c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227424 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-15 17:22:36 +00:00
template <typename Fn>
static void test_jit_and_interpreter(skvm::Program&& program, Fn&& test) {
test((const skvm::Program&) program);
program.dropJIT();
test((const skvm::Program&) program);
}
move Builder/Program dump() This is test-only code only used by SkVMTest.cpp, so it can live there. This cuts the dependency of SkVM on SkStream and co. Change-Id: I7695e527b2d16e4485f8c5f4cd39bb8300e9221d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225321 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-02 20:21:11 +00:00
sketch an skvm With all the thinking around a stack-based interpreter, I figured I'd sketch out some ideas for a register VM too. I kind of have the hunch that this is the direction that will actually let us replace large amounts of Skia's CPU backend with an efficient interpreter or JIT. Change-Id: Ia2b5ba4a3fc27556f5b6ba95cd1ace46d3217403 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/216665 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-05-29 17:57:54 +00:00
DEF_TEST(SkVM, r) {
streamline SkVM test rebaselining - keep expectations in resources/ - overwrite automatically if needed so we can see the diff in Git Change-Id: I2486b127ebcc7f40332fd0462e38b1af04d3e32b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218038 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-03 21:27:46 +00:00
SkDynamicMemoryWStream buf;
centralize test/bench SkVM builders Eliminate the duplicate functionality, and better testing for the bench builders. Change-Id: If20e52107738903f854aec431416e573d7a7d640 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218041 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-03 22:10:59 +00:00
// Write all combinations of SrcoverBuilder_F32
sketch an skvm With all the thinking around a stack-based interpreter, I figured I'd sketch out some ideas for a register VM too. I kind of have the hunch that this is the direction that will actually let us replace large amounts of Skia's CPU backend with an efficient interpreter or JIT. Change-Id: Ia2b5ba4a3fc27556f5b6ba95cd1ace46d3217403 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/216665 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-05-29 17:57:54 +00:00
for (int s = 0; s < 3; s++)
for (int d = 0; d < 3; d++) {
auto srcFmt = (Fmt)s,
dstFmt = (Fmt)d;
add Builder::dump() I used to have a dump of the value program before it was translated to registers, but it went away a while ago. This restores it. Change-Id: I9b8bfcb124843cad4b0dc44bdf0a03e95a0c83d8 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/219757 Commit-Queue: Mike Klein <mtklein@google.com> Commit-Queue: Brian Osman <brianosman@google.com> Auto-Submit: Mike Klein <mtklein@google.com> Reviewed-by: Brian Osman <brianosman@google.com>
2019-06-10 17:05:48 +00:00
SrcoverBuilder_F32 builder{srcFmt, dstFmt};
sketch an skvm With all the thinking around a stack-based interpreter, I figured I'd sketch out some ideas for a register VM too. I kind of have the hunch that this is the direction that will actually let us replace large amounts of Skia's CPU backend with an efficient interpreter or JIT. Change-Id: Ia2b5ba4a3fc27556f5b6ba95cd1ace46d3217403 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/216665 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-05-29 17:57:54 +00:00
streamline SkVM test rebaselining - keep expectations in resources/ - overwrite automatically if needed so we can see the diff in Git Change-Id: I2486b127ebcc7f40332fd0462e38b1af04d3e32b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218038 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-03 21:27:46 +00:00
buf.writeText(fmt_name(srcFmt));
buf.writeText(" over ");
buf.writeText(fmt_name(dstFmt));
buf.writeText("\n");
move death back into Builder::Instruction I find myself passing around parallel vectors of Builder::Instructions and deaths so often that it just makes more sense practically to store them together. It's a little awkward that the values are only useful after calling done(), but I can live with that. Get a little more careful about mutation, passing Builder::Instructions by const&. Instead of extending lifetimes of live hoisted instructions, just check for them in maybe_recycle_register() instead. Change-Id: I1cb9e25c1a7c46a250c2271334821be8535353bf Reviewed-on: https://skia-review.googlesource.com/c/skia/+/228367 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-18 15:36:45 +00:00
dump(builder, &buf);
streamline SkVM test rebaselining - keep expectations in resources/ - overwrite automatically if needed so we can see the diff in Git Change-Id: I2486b127ebcc7f40332fd0462e38b1af04d3e32b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218038 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-03 21:27:46 +00:00
}
centralize test/bench SkVM builders Eliminate the duplicate functionality, and better testing for the bench builders. Change-Id: If20e52107738903f854aec431416e573d7a7d640 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218041 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-03 22:10:59 +00:00
// Write the I32 Srcovers also.
first VEX ymm vector ops - 32x8 i32 add,sub,mul - add I32_Naive bench/test builder to get better i32 mul coverage - minor refactoring all over Change-Id: I13cc19ff37a2da0bcff289ba51baac08f456d6c5 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222485 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-20 16:37:10 +00:00
{
add misc. value programs to SkVMTest.expected Noticed we were only dumping the final register programs for the integer code. Might as well also track the value programs. Change-Id: I417c5c655b632691557bbbb136dcbd3f3167af9a Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225324 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-02 20:39:23 +00:00
SrcoverBuilder_I32_Naive builder;
first VEX ymm vector ops - 32x8 i32 add,sub,mul - add I32_Naive bench/test builder to get better i32 mul coverage - minor refactoring all over Change-Id: I13cc19ff37a2da0bcff289ba51baac08f456d6c5 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222485 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-20 16:37:10 +00:00
buf.writeText("I32 (Naive) 8888 over 8888\n");
move death back into Builder::Instruction I find myself passing around parallel vectors of Builder::Instructions and deaths so often that it just makes more sense practically to store them together. It's a little awkward that the values are only useful after calling done(), but I can live with that. Get a little more careful about mutation, passing Builder::Instructions by const&. Instead of extending lifetimes of live hoisted instructions, just check for them in maybe_recycle_register() instead. Change-Id: I1cb9e25c1a7c46a250c2271334821be8535353bf Reviewed-on: https://skia-review.googlesource.com/c/skia/+/228367 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-18 15:36:45 +00:00
dump(builder, &buf);
first VEX ymm vector ops - 32x8 i32 add,sub,mul - add I32_Naive bench/test builder to get better i32 mul coverage - minor refactoring all over Change-Id: I13cc19ff37a2da0bcff289ba51baac08f456d6c5 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222485 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-20 16:37:10 +00:00
}
centralize test/bench SkVM builders Eliminate the duplicate functionality, and better testing for the bench builders. Change-Id: If20e52107738903f854aec431416e573d7a7d640 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218041 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-03 22:10:59 +00:00
{
add misc. value programs to SkVMTest.expected Noticed we were only dumping the final register programs for the integer code. Might as well also track the value programs. Change-Id: I417c5c655b632691557bbbb136dcbd3f3167af9a Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225324 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-02 20:39:23 +00:00
SrcoverBuilder_I32 builder;
centralize test/bench SkVM builders Eliminate the duplicate functionality, and better testing for the bench builders. Change-Id: If20e52107738903f854aec431416e573d7a7d640 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218041 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-03 22:10:59 +00:00
buf.writeText("I32 8888 over 8888\n");
move death back into Builder::Instruction I find myself passing around parallel vectors of Builder::Instructions and deaths so often that it just makes more sense practically to store them together. It's a little awkward that the values are only useful after calling done(), but I can live with that. Get a little more careful about mutation, passing Builder::Instructions by const&. Instead of extending lifetimes of live hoisted instructions, just check for them in maybe_recycle_register() instead. Change-Id: I1cb9e25c1a7c46a250c2271334821be8535353bf Reviewed-on: https://skia-review.googlesource.com/c/skia/+/228367 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-18 15:36:45 +00:00
dump(builder, &buf);
centralize test/bench SkVM builders Eliminate the duplicate functionality, and better testing for the bench builders. Change-Id: If20e52107738903f854aec431416e573d7a7d640 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218041 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-03 22:10:59 +00:00
}
{
add misc. value programs to SkVMTest.expected Noticed we were only dumping the final register programs for the integer code. Might as well also track the value programs. Change-Id: I417c5c655b632691557bbbb136dcbd3f3167af9a Reviewed-on: https://skia-review.googlesource.com/c/skia/+/225324 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-02 20:39:23 +00:00
SrcoverBuilder_I32_SWAR builder;
centralize test/bench SkVM builders Eliminate the duplicate functionality, and better testing for the bench builders. Change-Id: If20e52107738903f854aec431416e573d7a7d640 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218041 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-03 22:10:59 +00:00
buf.writeText("I32 (SWAR) 8888 over 8888\n");
move death back into Builder::Instruction I find myself passing around parallel vectors of Builder::Instructions and deaths so often that it just makes more sense practically to store them together. It's a little awkward that the values are only useful after calling done(), but I can live with that. Get a little more careful about mutation, passing Builder::Instructions by const&. Instead of extending lifetimes of live hoisted instructions, just check for them in maybe_recycle_register() instead. Change-Id: I1cb9e25c1a7c46a250c2271334821be8535353bf Reviewed-on: https://skia-review.googlesource.com/c/skia/+/228367 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-18 15:36:45 +00:00
dump(builder, &buf);
centralize test/bench SkVM builders Eliminate the duplicate functionality, and better testing for the bench builders. Change-Id: If20e52107738903f854aec431416e573d7a7d640 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218041 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-03 22:10:59 +00:00
}
streamline SkVM test rebaselining - keep expectations in resources/ - overwrite automatically if needed so we can see the diff in Git Change-Id: I2486b127ebcc7f40332fd0462e38b1af04d3e32b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218038 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-03 21:27:46 +00:00
sk_sp<SkData> blob = buf.detachAsData();
{
sk_sp<SkData> expected = GetResourceAsData("SkVMTest.expected");
print SKVM test failures Can sometimes be hard to know what's going on on the bots without a little bit more debug help. Change-Id: Ie556a8de88349170e9d9e44c16098223442838a2 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218316 Auto-Submit: Mike Klein <mtklein@google.com> Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-04 18:35:32 +00:00
REPORTER_ASSERT(r, expected, "Couldn't load SkVMTest.expected.");
if (expected) {
if (blob->size() != expected->size()
|| 0 != memcmp(blob->data(), expected->data(), blob->size())) {
sketch an skvm With all the thinking around a stack-based interpreter, I figured I'd sketch out some ideas for a register VM too. I kind of have the hunch that this is the direction that will actually let us replace large amounts of Skia's CPU backend with an efficient interpreter or JIT. Change-Id: Ia2b5ba4a3fc27556f5b6ba95cd1ace46d3217403 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/216665 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-05-29 17:57:54 +00:00
print SKVM test failures Can sometimes be hard to know what's going on on the bots without a little bit more debug help. Change-Id: Ie556a8de88349170e9d9e44c16098223442838a2 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218316 Auto-Submit: Mike Klein <mtklein@google.com> Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-04 18:35:32 +00:00
ERRORF(r, "SkVMTest expected\n%.*s\nbut got\n%.*s\n",
expected->size(), expected->data(),
blob->size(), blob->data());
}
SkFILEWStream out(GetResourcePath("SkVMTest.expected").c_str());
if (out.isValid()) {
out.write(blob->data(), blob->size());
}
sketch an skvm With all the thinking around a stack-based interpreter, I figured I'd sketch out some ideas for a register VM too. I kind of have the hunch that this is the direction that will actually let us replace large amounts of Skia's CPU backend with an efficient interpreter or JIT. Change-Id: Ia2b5ba4a3fc27556f5b6ba95cd1ace46d3217403 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/216665 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-05-29 17:57:54 +00:00
}
}
test both JIT and interpreter Add Program::dropJIT() to allow us to proactively drop any JIT code forcing fallback on the interpreter, and use it to test both on JIT-supported platforms. Other platforms will just test the interpreter twice. Change-Id: I607d00ef3c648e66a0b3a1374b11aa82dbfff70c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227424 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-15 17:22:36 +00:00
auto test_8888 = [&](skvm::Program&& program) {
expand unit tests, fix extract The mask-only special case for extract is wrong... it never looked it its input! This not only makes things correct-er, but oddly it also makes them faster by breaking inter-loop data dependencies. Disable tests for _I32... they're actually still broken because of a much more systemic flaw in how I've evaluated programs. The _F32 and _I32_SWAR JIT code and all interpreted code is just getting lucky. o_O While here, update the I32_SWAR code to use the same math as I32, (x*y+x)/256 for unorm8 mul. This just helps keep me sane. Change-Id: I1acc09adb84c426fca4b2be5ca8c2d46d9678dd8 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/220577 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-12 17:54:52 +00:00
uint32_t src[9];
uint32_t dst[SK_ARRAY_COUNT(src)];
centralize test/bench SkVM builders Eliminate the duplicate functionality, and better testing for the bench builders. Change-Id: If20e52107738903f854aec431416e573d7a7d640 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218041 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-03 22:10:59 +00:00
test both JIT and interpreter Add Program::dropJIT() to allow us to proactively drop any JIT code forcing fallback on the interpreter, and use it to test both on JIT-supported platforms. Other platforms will just test the interpreter twice. Change-Id: I607d00ef3c648e66a0b3a1374b11aa82dbfff70c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227424 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-15 17:22:36 +00:00
test_jit_and_interpreter(std::move(program), [&](const skvm::Program& program) {
for (int i = 0; i < (int)SK_ARRAY_COUNT(src); i++) {
src[i] = 0xbb007733;
dst[i] = 0xffaaccee;
}
centralize test/bench SkVM builders Eliminate the duplicate functionality, and better testing for the bench builders. Change-Id: If20e52107738903f854aec431416e573d7a7d640 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218041 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-03 22:10:59 +00:00
test both JIT and interpreter Add Program::dropJIT() to allow us to proactively drop any JIT code forcing fallback on the interpreter, and use it to test both on JIT-supported platforms. Other platforms will just test the interpreter twice. Change-Id: I607d00ef3c648e66a0b3a1374b11aa82dbfff70c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227424 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-15 17:22:36 +00:00
SkPMColor expected = SkPMSrcOver(src[0], dst[0]); // 0xff2dad73
centralize test/bench SkVM builders Eliminate the duplicate functionality, and better testing for the bench builders. Change-Id: If20e52107738903f854aec431416e573d7a7d640 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218041 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-03 22:10:59 +00:00
test both JIT and interpreter Add Program::dropJIT() to allow us to proactively drop any JIT code forcing fallback on the interpreter, and use it to test both on JIT-supported platforms. Other platforms will just test the interpreter twice. Change-Id: I607d00ef3c648e66a0b3a1374b11aa82dbfff70c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227424 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-15 17:22:36 +00:00
program.eval((int)SK_ARRAY_COUNT(src), src, dst);
centralize test/bench SkVM builders Eliminate the duplicate functionality, and better testing for the bench builders. Change-Id: If20e52107738903f854aec431416e573d7a7d640 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218041 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-03 22:10:59 +00:00
test both JIT and interpreter Add Program::dropJIT() to allow us to proactively drop any JIT code forcing fallback on the interpreter, and use it to test both on JIT-supported platforms. Other platforms will just test the interpreter twice. Change-Id: I607d00ef3c648e66a0b3a1374b11aa82dbfff70c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227424 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-15 17:22:36 +00:00
// dst is probably 0xff2dad72.
for (auto got : dst) {
auto want = expected;
for (int i = 0; i < 4; i++) {
uint8_t d = got & 0xff,
w = want & 0xff;
Reland "more JIT refactoring" This is a reland of 558b6392250e6dd4a92dc4a94640c7ec2cda66e7 PS2... oh, right, not everything supports AVX2. Original change's description: > more JIT refactoring > > This re-enables AVX2 JIT with simultaneous register assignment and > instruction selection. You can see it working in a very basic way in > how we choose instructions and registers for Op::mad_f32. > > Constants are still broadcast, here inside the loop instead of hoisted. > I think it'll probably end up best to use constants directly from memory > (as in vpshufb's masks), falling back to these in-loop broadcasts when > that can't work. > > Change-Id: If17d51b9960f08da3612e51ac04424e996bf83d4 > Reviewed-on: https://skia-review.googlesource.com/c/skia/+/228366 > Commit-Queue: Mike Klein <mtklein@google.com> > Reviewed-by: Mike Klein <mtklein@google.com> Cq-Include-Trybots: skia.primary:Test-Mac10.13-Clang-VMware7.1-CPU-AVX-x86_64-Debug-All-NativeFonts Change-Id: I6f99d275040abe6210a980fc544f7f22c3b85727 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/228476 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-18 15:17:28 +00:00
if (abs(d-w) >= 2) {
SkDebugf("d %02x, w %02x\n", d,w);
}
test both JIT and interpreter Add Program::dropJIT() to allow us to proactively drop any JIT code forcing fallback on the interpreter, and use it to test both on JIT-supported platforms. Other platforms will just test the interpreter twice. Change-Id: I607d00ef3c648e66a0b3a1374b11aa82dbfff70c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227424 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-15 17:22:36 +00:00
REPORTER_ASSERT(r, abs(d-w) < 2);
got >>= 8;
want >>= 8;
}
expand unit tests, fix extract The mask-only special case for extract is wrong... it never looked it its input! This not only makes things correct-er, but oddly it also makes them faster by breaking inter-loop data dependencies. Disable tests for _I32... they're actually still broken because of a much more systemic flaw in how I've evaluated programs. The _F32 and _I32_SWAR JIT code and all interpreted code is just getting lucky. o_O While here, update the I32_SWAR code to use the same math as I32, (x*y+x)/256 for unorm8 mul. This just helps keep me sane. Change-Id: I1acc09adb84c426fca4b2be5ca8c2d46d9678dd8 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/220577 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-12 17:54:52 +00:00
}
test both JIT and interpreter Add Program::dropJIT() to allow us to proactively drop any JIT code forcing fallback on the interpreter, and use it to test both on JIT-supported platforms. Other platforms will just test the interpreter twice. Change-Id: I607d00ef3c648e66a0b3a1374b11aa82dbfff70c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227424 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-15 17:22:36 +00:00
});
expand unit tests, fix extract The mask-only special case for extract is wrong... it never looked it its input! This not only makes things correct-er, but oddly it also makes them faster by breaking inter-loop data dependencies. Disable tests for _I32... they're actually still broken because of a much more systemic flaw in how I've evaluated programs. The _F32 and _I32_SWAR JIT code and all interpreted code is just getting lucky. o_O While here, update the I32_SWAR code to use the same math as I32, (x*y+x)/256 for unorm8 mul. This just helps keep me sane. Change-Id: I1acc09adb84c426fca4b2be5ca8c2d46d9678dd8 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/220577 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-12 17:54:52 +00:00
};
centralize test/bench SkVM builders Eliminate the duplicate functionality, and better testing for the bench builders. Change-Id: If20e52107738903f854aec431416e573d7a7d640 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/218041 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-03 22:10:59 +00:00
Reland "more JIT refactoring" This is a reland of 558b6392250e6dd4a92dc4a94640c7ec2cda66e7 PS2... oh, right, not everything supports AVX2. Original change's description: > more JIT refactoring > > This re-enables AVX2 JIT with simultaneous register assignment and > instruction selection. You can see it working in a very basic way in > how we choose instructions and registers for Op::mad_f32. > > Constants are still broadcast, here inside the loop instead of hoisted. > I think it'll probably end up best to use constants directly from memory > (as in vpshufb's masks), falling back to these in-loop broadcasts when > that can't work. > > Change-Id: If17d51b9960f08da3612e51ac04424e996bf83d4 > Reviewed-on: https://skia-review.googlesource.com/c/skia/+/228366 > Commit-Queue: Mike Klein <mtklein@google.com> > Reviewed-by: Mike Klein <mtklein@google.com> Cq-Include-Trybots: skia.primary:Test-Mac10.13-Clang-VMware7.1-CPU-AVX-x86_64-Debug-All-NativeFonts Change-Id: I6f99d275040abe6210a980fc544f7f22c3b85727 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/228476 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-18 15:17:28 +00:00
test_8888(SrcoverBuilder_F32{Fmt::RGBA_8888, Fmt::RGBA_8888}.done("srcover_f32"));
test_8888(SrcoverBuilder_I32_Naive{}.done("srcover_i32_naive"));
test_8888(SrcoverBuilder_I32{}.done("srcover_i32"));
test_8888(SrcoverBuilder_I32_SWAR{}.done("srcover_i32_SWAR"));
sketch an skvm With all the thinking around a stack-based interpreter, I figured I'd sketch out some ideas for a register VM too. I kind of have the hunch that this is the direction that will actually let us replace large amounts of Skia's CPU backend with an efficient interpreter or JIT. Change-Id: Ia2b5ba4a3fc27556f5b6ba95cd1ace46d3217403 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/216665 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-05-29 17:57:54 +00:00
test both JIT and interpreter Add Program::dropJIT() to allow us to proactively drop any JIT code forcing fallback on the interpreter, and use it to test both on JIT-supported platforms. Other platforms will just test the interpreter twice. Change-Id: I607d00ef3c648e66a0b3a1374b11aa82dbfff70c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227424 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-15 17:22:36 +00:00
test_jit_and_interpreter(SrcoverBuilder_F32{Fmt::RGBA_8888, Fmt::G8}.done(),
[&](const skvm::Program& program) {
expand unit tests, fix extract The mask-only special case for extract is wrong... it never looked it its input! This not only makes things correct-er, but oddly it also makes them faster by breaking inter-loop data dependencies. Disable tests for _I32... they're actually still broken because of a much more systemic flaw in how I've evaluated programs. The _F32 and _I32_SWAR JIT code and all interpreted code is just getting lucky. o_O While here, update the I32_SWAR code to use the same math as I32, (x*y+x)/256 for unorm8 mul. This just helps keep me sane. Change-Id: I1acc09adb84c426fca4b2be5ca8c2d46d9678dd8 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/220577 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-12 17:54:52 +00:00
uint32_t src[9];
uint8_t dst[SK_ARRAY_COUNT(src)];
sketch an skvm With all the thinking around a stack-based interpreter, I figured I'd sketch out some ideas for a register VM too. I kind of have the hunch that this is the direction that will actually let us replace large amounts of Skia's CPU backend with an efficient interpreter or JIT. Change-Id: Ia2b5ba4a3fc27556f5b6ba95cd1ace46d3217403 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/216665 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-05-29 17:57:54 +00:00
expand unit tests, fix extract The mask-only special case for extract is wrong... it never looked it its input! This not only makes things correct-er, but oddly it also makes them faster by breaking inter-loop data dependencies. Disable tests for _I32... they're actually still broken because of a much more systemic flaw in how I've evaluated programs. The _F32 and _I32_SWAR JIT code and all interpreted code is just getting lucky. o_O While here, update the I32_SWAR code to use the same math as I32, (x*y+x)/256 for unorm8 mul. This just helps keep me sane. Change-Id: I1acc09adb84c426fca4b2be5ca8c2d46d9678dd8 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/220577 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-12 17:54:52 +00:00
for (int i = 0; i < (int)SK_ARRAY_COUNT(src); i++) {
src[i] = 0xbb007733;
dst[i] = 0x42;
sketch an skvm With all the thinking around a stack-based interpreter, I figured I'd sketch out some ideas for a register VM too. I kind of have the hunch that this is the direction that will actually let us replace large amounts of Skia's CPU backend with an efficient interpreter or JIT. Change-Id: Ia2b5ba4a3fc27556f5b6ba95cd1ace46d3217403 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/216665 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-05-29 17:57:54 +00:00
}
expand unit tests, fix extract The mask-only special case for extract is wrong... it never looked it its input! This not only makes things correct-er, but oddly it also makes them faster by breaking inter-loop data dependencies. Disable tests for _I32... they're actually still broken because of a much more systemic flaw in how I've evaluated programs. The _F32 and _I32_SWAR JIT code and all interpreted code is just getting lucky. o_O While here, update the I32_SWAR code to use the same math as I32, (x*y+x)/256 for unorm8 mul. This just helps keep me sane. Change-Id: I1acc09adb84c426fca4b2be5ca8c2d46d9678dd8 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/220577 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-12 17:54:52 +00:00
SkPMColor over = SkPMSrcOver(SkPackARGB32(0xbb, 0x33, 0x77, 0x00),
0xff424242);
sketch an skvm With all the thinking around a stack-based interpreter, I figured I'd sketch out some ideas for a register VM too. I kind of have the hunch that this is the direction that will actually let us replace large amounts of Skia's CPU backend with an efficient interpreter or JIT. Change-Id: Ia2b5ba4a3fc27556f5b6ba95cd1ace46d3217403 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/216665 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-05-29 17:57:54 +00:00
uint8_t want = SkComputeLuminance(SkGetPackedR32(over),
SkGetPackedG32(over),
SkGetPackedB32(over));
expand unit tests, fix extract The mask-only special case for extract is wrong... it never looked it its input! This not only makes things correct-er, but oddly it also makes them faster by breaking inter-loop data dependencies. Disable tests for _I32... they're actually still broken because of a much more systemic flaw in how I've evaluated programs. The _F32 and _I32_SWAR JIT code and all interpreted code is just getting lucky. o_O While here, update the I32_SWAR code to use the same math as I32, (x*y+x)/256 for unorm8 mul. This just helps keep me sane. Change-Id: I1acc09adb84c426fca4b2be5ca8c2d46d9678dd8 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/220577 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-12 17:54:52 +00:00
program.eval((int)SK_ARRAY_COUNT(src), src, dst);
sketch an skvm With all the thinking around a stack-based interpreter, I figured I'd sketch out some ideas for a register VM too. I kind of have the hunch that this is the direction that will actually let us replace large amounts of Skia's CPU backend with an efficient interpreter or JIT. Change-Id: Ia2b5ba4a3fc27556f5b6ba95cd1ace46d3217403 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/216665 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-05-29 17:57:54 +00:00
expand unit tests, fix extract The mask-only special case for extract is wrong... it never looked it its input! This not only makes things correct-er, but oddly it also makes them faster by breaking inter-loop data dependencies. Disable tests for _I32... they're actually still broken because of a much more systemic flaw in how I've evaluated programs. The _F32 and _I32_SWAR JIT code and all interpreted code is just getting lucky. o_O While here, update the I32_SWAR code to use the same math as I32, (x*y+x)/256 for unorm8 mul. This just helps keep me sane. Change-Id: I1acc09adb84c426fca4b2be5ca8c2d46d9678dd8 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/220577 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-12 17:54:52 +00:00
for (auto got : dst) {
REPORTER_ASSERT(r, abs(got-want) < 3);
}
test both JIT and interpreter Add Program::dropJIT() to allow us to proactively drop any JIT code forcing fallback on the interpreter, and use it to test both on JIT-supported platforms. Other platforms will just test the interpreter twice. Change-Id: I607d00ef3c648e66a0b3a1374b11aa82dbfff70c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227424 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-15 17:22:36 +00:00
});
sketch an skvm With all the thinking around a stack-based interpreter, I figured I'd sketch out some ideas for a register VM too. I kind of have the hunch that this is the direction that will actually let us replace large amounts of Skia's CPU backend with an efficient interpreter or JIT. Change-Id: Ia2b5ba4a3fc27556f5b6ba95cd1ace46d3217403 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/216665 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-05-29 17:57:54 +00:00
test both JIT and interpreter Add Program::dropJIT() to allow us to proactively drop any JIT code forcing fallback on the interpreter, and use it to test both on JIT-supported platforms. Other platforms will just test the interpreter twice. Change-Id: I607d00ef3c648e66a0b3a1374b11aa82dbfff70c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227424 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-15 17:22:36 +00:00
test_jit_and_interpreter(SrcoverBuilder_F32{Fmt::A8, Fmt::A8}.done(),
[&](const skvm::Program& program) {
sketch an skvm With all the thinking around a stack-based interpreter, I figured I'd sketch out some ideas for a register VM too. I kind of have the hunch that this is the direction that will actually let us replace large amounts of Skia's CPU backend with an efficient interpreter or JIT. Change-Id: Ia2b5ba4a3fc27556f5b6ba95cd1ace46d3217403 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/216665 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-05-29 17:57:54 +00:00
uint8_t src[256],
dst[256];
for (int i = 0; i < 256; i++) {
src[i] = 255 - i;
dst[i] = i;
}
program.eval(256, src, dst);
for (int i = 0; i < 256; i++) {
uint8_t want = SkGetPackedA32(SkPMSrcOver(SkPackARGB32(src[i], 0,0,0),
SkPackARGB32( i, 0,0,0)));
REPORTER_ASSERT(r, abs(dst[i]-want) < 2);
}
test both JIT and interpreter Add Program::dropJIT() to allow us to proactively drop any JIT code forcing fallback on the interpreter, and use it to test both on JIT-supported platforms. Other platforms will just test the interpreter twice. Change-Id: I607d00ef3c648e66a0b3a1374b11aa82dbfff70c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227424 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-15 17:22:36 +00:00
});
sketch an skvm With all the thinking around a stack-based interpreter, I figured I'd sketch out some ideas for a register VM too. I kind of have the hunch that this is the direction that will actually let us replace large amounts of Skia's CPU backend with an efficient interpreter or JIT. Change-Id: Ia2b5ba4a3fc27556f5b6ba95cd1ace46d3217403 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/216665 Reviewed-by: Brian Osman <brianosman@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-05-29 17:57:54 +00:00
}
test and fix that we cover the right inputs At head we're redoing any n<8 tail from the start, not continuing from (n/8)*8 like we'd want. Change-Id: I1a3d24cdffc843bbe6f3e01a163b6e3a20fdd0ca Reviewed-on: https://skia-review.googlesource.com/c/skia/+/220556 Reviewed-by: Brian Osman <brianosman@google.com> Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-12 16:36:28 +00:00
test a (the) zero-arg program Just because a program doesn't read from or write to memory doesn't mean it's pointless. Oh wait, yes it does. It shouldn't crash though. Change-Id: I6a9c26c065831f9598afccce6e0a34a178cbd925 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/230839 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-30 17:30:13 +00:00
DEF_TEST(SkVM_Pointless, r) {
// Let's build a program with no memory arguments.
// It should all be pegged as dead code, but we should be able to "run" it.
skvm::Builder b;
{
b.add(b.splat(5.0f),
b.splat(4.0f));
}
test_jit_and_interpreter(b.done(), [&](const skvm::Program& program) {
for (int N = 0; N < 64; N++) {
program.eval(N);
}
});
for (const skvm::Builder::Instruction& inst : b.program()) {
REPORTER_ASSERT(r, inst.death == 0 && inst.hoist == true);
}
}
test and fix that we cover the right inputs At head we're redoing any n<8 tail from the start, not continuing from (n/8)*8 like we'd want. Change-Id: I1a3d24cdffc843bbe6f3e01a163b6e3a20fdd0ca Reviewed-on: https://skia-review.googlesource.com/c/skia/+/220556 Reviewed-by: Brian Osman <brianosman@google.com> Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-12 16:36:28 +00:00
DEF_TEST(SkVM_LoopCounts, r) {
// Make sure we cover all the exact N we want.
test both JIT and interpreter Add Program::dropJIT() to allow us to proactively drop any JIT code forcing fallback on the interpreter, and use it to test both on JIT-supported platforms. Other platforms will just test the interpreter twice. Change-Id: I607d00ef3c648e66a0b3a1374b11aa82dbfff70c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227424 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-15 17:22:36 +00:00
// buf[i] += 1
skvm::Builder b;
small refactors Change-Id: I58b52d3e1d05d0834be30e00d991636e227cbf0b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/230836 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-30 14:44:30 +00:00
skvm::Arg arg = b.varying<int>();
test both JIT and interpreter Add Program::dropJIT() to allow us to proactively drop any JIT code forcing fallback on the interpreter, and use it to test both on JIT-supported platforms. Other platforms will just test the interpreter twice. Change-Id: I607d00ef3c648e66a0b3a1374b11aa82dbfff70c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227424 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-15 17:22:36 +00:00
b.store32(arg,
b.add(b.splat(1),
b.load32(arg)));
restore aarch64 JIT Trying to keep most of the structural parts shared between x86_64 and aarch64. Not sure if this will stay factored like this long-term, but the last version felt like there was a bit too much redundancy, and I don't want to write things like register management more often than have to. Change-Id: Ieeb21f433715a730c41c85d657c5b33fa4702696 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/228608 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-19 16:13:42 +00:00
test_jit_and_interpreter(b.done(), [&](const skvm::Program& program) {
int buf[64];
for (int N = 0; N <= (int)SK_ARRAY_COUNT(buf); N++) {
test both JIT and interpreter Add Program::dropJIT() to allow us to proactively drop any JIT code forcing fallback on the interpreter, and use it to test both on JIT-supported platforms. Other platforms will just test the interpreter twice. Change-Id: I607d00ef3c648e66a0b3a1374b11aa82dbfff70c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227424 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-15 17:22:36 +00:00
for (int i = 0; i < (int)SK_ARRAY_COUNT(buf); i++) {
buf[i] = i;
}
program.eval(N, buf);
test and fix that we cover the right inputs At head we're redoing any n<8 tail from the start, not continuing from (n/8)*8 like we'd want. Change-Id: I1a3d24cdffc843bbe6f3e01a163b6e3a20fdd0ca Reviewed-on: https://skia-review.googlesource.com/c/skia/+/220556 Reviewed-by: Brian Osman <brianosman@google.com> Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-12 16:36:28 +00:00
test both JIT and interpreter Add Program::dropJIT() to allow us to proactively drop any JIT code forcing fallback on the interpreter, and use it to test both on JIT-supported platforms. Other platforms will just test the interpreter twice. Change-Id: I607d00ef3c648e66a0b3a1374b11aa82dbfff70c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227424 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-15 17:22:36 +00:00
for (int i = 0; i < N; i++) {
REPORTER_ASSERT(r, buf[i] == i+1);
}
for (int i = N; i < (int)SK_ARRAY_COUNT(buf); i++) {
REPORTER_ASSERT(r, buf[i] == i);
}
restore aarch64 JIT Trying to keep most of the structural parts shared between x86_64 and aarch64. Not sure if this will stay factored like this long-term, but the last version felt like there was a bit too much redundancy, and I don't want to write things like register management more often than have to. Change-Id: Ieeb21f433715a730c41c85d657c5b33fa4702696 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/228608 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-19 16:13:42 +00:00
}
});
test and fix that we cover the right inputs At head we're redoing any n<8 tail from the start, not continuing from (n/8)*8 like we'd want. Change-Id: I1a3d24cdffc843bbe6f3e01a163b6e3a20fdd0ca Reviewed-on: https://skia-review.googlesource.com/c/skia/+/220556 Reviewed-by: Brian Osman <brianosman@google.com> Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-12 16:36:28 +00:00
}
Reland "extract Assembler so it can be tested" This is a reland of a224fc1105960fe955d32fad28f502148108ecc1 Changes since original: - switch fJIT_K to less error prone fJITMask - guard fJIT Assembler Program member with SKVM_JIT Not really sure why the mips64el-Debug bot's compiler is crashing; it does at least make sense to crash where it does... the file includes SkOpts.h which includes SkVM.h. If no reasonable code transformation can get it working again I'll remove the bot. The -Release version is fine, and mips64el is one of those things I'd happily flush if it blocks progress. In this end I think all this SKVM_JIT and Xbyak stuff should go away and make things simple again, hopefully too simple to crash GCC. :| Original change's description: > extract Assembler so it can be tested > > And start documenting some structs we'll need > to replace xbyak. > > Change-Id: I21c91642799a54e10af85afc8edbe12a9b4aa062 > Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221644 > Reviewed-by: Herb Derby <herb@google.com> > Commit-Queue: Mike Klein <mtklein@google.com> Cq-Include-Trybots: skia.primary:Test-Debian9-Clang-GCE-CPU-AVX2-x86_64-Release-All-SK_CPU_LIMIT_SSE2,Build-Debian9-GCC-mips64el-Debug Change-Id: I6d7c27bc758b23c164ee67067cdfacc291e289fc Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221983 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-18 17:16:06 +00:00
more unit tests Backfill tests for some uncovered operations. Mostly functional tests, with some targeted at particular corners of code generation, and a few assembler unit tests. This doesn't get up to 100% line coverage, but I think it covers all the non-failure cases. Change-Id: Ib701df0c505aa41e3b2fe3cd429447acb294b752 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/230837 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-30 16:11:09 +00:00
DEF_TEST(SkVM_gathers, r) {
skvm::Builder b;
{
skvm::Arg img = b.uniform(),
buf32 = b.varying<int>(),
buf16 = b.varying<uint16_t>(),
buf8 = b.varying<uint8_t>();
skvm::I32 x = b.load32(buf32);
b.store32(buf32, b.gather32(img, b.bit_and(x, b.splat( 7))));
b.store16(buf16, b.gather16(img, b.bit_and(x, b.splat(15))));
b.store8 (buf8 , b.gather8 (img, b.bit_and(x, b.splat(31))));
}
test_jit_and_interpreter(b.done(), [&](const skvm::Program& program) {
const int img[] = {12,34,56,78, 90,98,76,54};
constexpr int N = 20;
int buf32[N];
uint16_t buf16[N];
uint8_t buf8 [N];
for (int i = 0; i < 20; i++) {
buf32[i] = i;
}
program.eval(N, img, buf32, buf16, buf8);
int i = 0;
REPORTER_ASSERT(r, buf32[i] == 12 && buf16[i] == 12 && buf8[i] == 12); i++;
REPORTER_ASSERT(r, buf32[i] == 34 && buf16[i] == 0 && buf8[i] == 0); i++;
REPORTER_ASSERT(r, buf32[i] == 56 && buf16[i] == 34 && buf8[i] == 0); i++;
REPORTER_ASSERT(r, buf32[i] == 78 && buf16[i] == 0 && buf8[i] == 0); i++;
REPORTER_ASSERT(r, buf32[i] == 90 && buf16[i] == 56 && buf8[i] == 34); i++;
REPORTER_ASSERT(r, buf32[i] == 98 && buf16[i] == 0 && buf8[i] == 0); i++;
REPORTER_ASSERT(r, buf32[i] == 76 && buf16[i] == 78 && buf8[i] == 0); i++;
REPORTER_ASSERT(r, buf32[i] == 54 && buf16[i] == 0 && buf8[i] == 0); i++;
REPORTER_ASSERT(r, buf32[i] == 12 && buf16[i] == 90 && buf8[i] == 56); i++;
REPORTER_ASSERT(r, buf32[i] == 34 && buf16[i] == 0 && buf8[i] == 0); i++;
REPORTER_ASSERT(r, buf32[i] == 56 && buf16[i] == 98 && buf8[i] == 0); i++;
REPORTER_ASSERT(r, buf32[i] == 78 && buf16[i] == 0 && buf8[i] == 0); i++;
REPORTER_ASSERT(r, buf32[i] == 90 && buf16[i] == 76 && buf8[i] == 78); i++;
REPORTER_ASSERT(r, buf32[i] == 98 && buf16[i] == 0 && buf8[i] == 0); i++;
REPORTER_ASSERT(r, buf32[i] == 76 && buf16[i] == 54 && buf8[i] == 0); i++;
REPORTER_ASSERT(r, buf32[i] == 54 && buf16[i] == 0 && buf8[i] == 0); i++;
REPORTER_ASSERT(r, buf32[i] == 12 && buf16[i] == 12 && buf8[i] == 90); i++;
REPORTER_ASSERT(r, buf32[i] == 34 && buf16[i] == 0 && buf8[i] == 0); i++;
REPORTER_ASSERT(r, buf32[i] == 56 && buf16[i] == 34 && buf8[i] == 0); i++;
REPORTER_ASSERT(r, buf32[i] == 78 && buf16[i] == 0 && buf8[i] == 0); i++;
});
}
DEF_TEST(SkVM_bitops, r) {
skvm::Builder b;
{
skvm::Arg ptr = b.varying<int>();
skvm::I32 x = b.load32(ptr);
x = b.bit_and (x, b.splat(0xf1)); // 0x40
x = b.bit_or (x, b.splat(0x80)); // 0xc0
x = b.bit_xor (x, b.splat(0xfe)); // 0x3e
x = b.bit_clear(x, b.splat(0x30)); // 0x0e
x = b.shl(x, 28); // 0xe000'0000
x = b.sra(x, 28); // 0xffff'fffe
x = b.shr(x, 1); // 0x7fff'ffff
b.store32(ptr, x);
}
test_jit_and_interpreter(b.done(), [&](const skvm::Program& program) {
int x = 0x42;
program.eval(1, &x);
REPORTER_ASSERT(r, x == 0x7fff'ffff);
});
}
DEF_TEST(SkVM_f32, r) {
skvm::Builder b;
{
skvm::Arg arg = b.varying<float>();
skvm::F32 x = b.bit_cast(b.load32(arg)),
y = b.add(x,x), // y = 2x
z = b.sub(y,x), // z = 2x-x = x
w = b.div(z,x); // w = x/x = 1
b.store32(arg, b.bit_cast(w));
}
test_jit_and_interpreter(b.done(), [&](const skvm::Program& program) {
float buf[] = { 1,2,3,4,5,6,7,8,9 };
program.eval(SK_ARRAY_COUNT(buf), buf);
for (float v : buf) {
REPORTER_ASSERT(r, v == 1.0f);
}
});
}
DEF_TEST(SkVM_cmp_i32, r) {
skvm::Builder b;
{
skvm::I32 x = b.load32(b.varying<int>());
auto to_bit = [&](int shift, skvm::I32 mask) {
return b.shl(b.bit_and(mask, b.splat(0x1)), shift);
};
skvm::I32 m = b.splat(0);
m = b.bit_or(m, to_bit(0, b. eq(x, b.splat(0))));
m = b.bit_or(m, to_bit(1, b.neq(x, b.splat(1))));
m = b.bit_or(m, to_bit(2, b. lt(x, b.splat(2))));
m = b.bit_or(m, to_bit(3, b.lte(x, b.splat(3))));
m = b.bit_or(m, to_bit(4, b. gt(x, b.splat(4))));
m = b.bit_or(m, to_bit(5, b.gte(x, b.splat(5))));
b.store32(b.varying<int>(), m);
}
test_jit_and_interpreter(b.done(), [&](const skvm::Program& program) {
int in[] = { 0,1,2,3,4,5,6,7,8,9 };
int out[SK_ARRAY_COUNT(in)];
program.eval(SK_ARRAY_COUNT(in), in, out);
REPORTER_ASSERT(r, out[0] == 0b001111);
REPORTER_ASSERT(r, out[1] == 0b001100);
REPORTER_ASSERT(r, out[2] == 0b001010);
REPORTER_ASSERT(r, out[3] == 0b001010);
REPORTER_ASSERT(r, out[4] == 0b000010);
for (int i = 5; i < (int)SK_ARRAY_COUNT(out); i++) {
REPORTER_ASSERT(r, out[i] == 0b110010);
}
});
}
DEF_TEST(SkVM_cmp_f32, r) {
skvm::Builder b;
{
skvm::F32 x = b.bit_cast(b.load32(b.varying<float>()));
auto to_bit = [&](int shift, skvm::I32 mask) {
return b.shl(b.bit_and(mask, b.splat(0x1)), shift);
};
skvm::I32 m = b.splat(0);
m = b.bit_or(m, to_bit(0, b. eq(x, b.splat(0.0f))));
m = b.bit_or(m, to_bit(1, b.neq(x, b.splat(1.0f))));
m = b.bit_or(m, to_bit(2, b. lt(x, b.splat(2.0f))));
m = b.bit_or(m, to_bit(3, b.lte(x, b.splat(3.0f))));
m = b.bit_or(m, to_bit(4, b. gt(x, b.splat(4.0f))));
m = b.bit_or(m, to_bit(5, b.gte(x, b.splat(5.0f))));
b.store32(b.varying<int>(), m);
}
test_jit_and_interpreter(b.done(), [&](const skvm::Program& program) {
float in[] = { 0,1,2,3,4,5,6,7,8,9 };
int out[SK_ARRAY_COUNT(in)];
program.eval(SK_ARRAY_COUNT(in), in, out);
REPORTER_ASSERT(r, out[0] == 0b001111);
REPORTER_ASSERT(r, out[1] == 0b001100);
REPORTER_ASSERT(r, out[2] == 0b001010);
REPORTER_ASSERT(r, out[3] == 0b001010);
REPORTER_ASSERT(r, out[4] == 0b000010);
for (int i = 5; i < (int)SK_ARRAY_COUNT(out); i++) {
REPORTER_ASSERT(r, out[i] == 0b110010);
}
});
}
DEF_TEST(SkVM_i16x2, r) {
skvm::Builder b;
{
skvm::Arg buf = b.varying<int>();
skvm::I32 x = b.load32(buf),
y = b.add_16x2(x,x), // y = 2x
z = b.mul_16x2(x,y), // z = 2x^2
w = b.sub_16x2(z,x), // w = x(2x-1)
v = b.shl_16x2(w,7), // These shifts will be a no-op
u = b.sra_16x2(v,7); // for all but x=12 and x=13.
b.store32(buf, u);
}
test_jit_and_interpreter(b.done(), [&](const skvm::Program& program) {
uint16_t buf[] = { 0,1,2,3,4,5,6,7,8,9,10,11,12,13 };
program.eval(SK_ARRAY_COUNT(buf)/2, buf);
for (int i = 0; i < 12; i++) {
REPORTER_ASSERT(r, buf[i] == i*(2*i-1));
}
REPORTER_ASSERT(r, buf[12] == 0xff14); // 12*23 = 0x114
REPORTER_ASSERT(r, buf[13] == 0xff45); // 13*25 = 0x145
});
}
DEF_TEST(SkVM_cmp_i16, r) {
skvm::Builder b;
{
skvm::Arg buf = b.varying<int>();
skvm::I32 x = b.load32(buf);
auto to_bit = [&](int shift, skvm::I32 mask) {
return b.shl_16x2(b.bit_and(mask, b.splat(0x0001'0001)), shift);
};
skvm::I32 m = b.splat(0);
m = b.bit_or(m, to_bit(0, b. eq_16x2(x, b.splat(0x0000'0000))));
m = b.bit_or(m, to_bit(1, b.neq_16x2(x, b.splat(0x0001'0001))));
m = b.bit_or(m, to_bit(2, b. lt_16x2(x, b.splat(0x0002'0002))));
m = b.bit_or(m, to_bit(3, b.lte_16x2(x, b.splat(0x0003'0003))));
m = b.bit_or(m, to_bit(4, b. gt_16x2(x, b.splat(0x0004'0004))));
m = b.bit_or(m, to_bit(5, b.gte_16x2(x, b.splat(0x0005'0005))));
b.store32(buf, m);
}
test_jit_and_interpreter(b.done(), [&](const skvm::Program& program) {
int16_t buf[] = { 0,1, 2,3, 4,5, 6,7, 8,9 };
program.eval(SK_ARRAY_COUNT(buf)/2, buf);
REPORTER_ASSERT(r, buf[0] == 0b001111);
REPORTER_ASSERT(r, buf[1] == 0b001100);
REPORTER_ASSERT(r, buf[2] == 0b001010);
REPORTER_ASSERT(r, buf[3] == 0b001010);
REPORTER_ASSERT(r, buf[4] == 0b000010);
for (int i = 5; i < (int)SK_ARRAY_COUNT(buf); i++) {
REPORTER_ASSERT(r, buf[i] == 0b110010);
}
});
}
always fma in mad_f32() We can always move data around so that an FMA is possible using no more registers than we would otherwise, and on x86, evne using no more instructions. The basic idea here is that if we can't reuse one of the inputs to destructively host the FMA instruction, the next best thing is to copy one of the arguments into tmp() and accumulate the FMA there. Once the FMA has happened, we just need to copy that result to dst(). We can of course skip that copy if dst() == tmp(). On x86 we never need that copy; dst() and tmp() are picked using the same logic except that dst may alias one of its inputs, and we only fall into this case after we've already found it doesn't. So we can just assert dst() == tmp() rather than check it like we do on ARM. It's subtle, but I think sound. I'm using logical-or to copy registers around. This is a little lazy, but maybe not as lazy as it looks: on ARM that is _the_ way to copy registers. There's a vmovdqa instruction I could use on x86, TBD. All paths through this new code were being exercised on ARM, but we didn't have anything hitting the tmp case on x86, so I've added a new unit test that hits the corner cases of both implementations. Change-Id: I5422414fc50c64d491b4933b4b580b784596f291 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/228630 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-19 18:56:41 +00:00
DEF_TEST(SkVM_mad, r) {
// This program is designed to exercise the tricky corners of instruction
// and register selection for Op::mad_f32.
skvm::Builder b;
{
small refactors Change-Id: I58b52d3e1d05d0834be30e00d991636e227cbf0b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/230836 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-30 14:44:30 +00:00
skvm::Arg arg = b.varying<int>();
always fma in mad_f32() We can always move data around so that an FMA is possible using no more registers than we would otherwise, and on x86, evne using no more instructions. The basic idea here is that if we can't reuse one of the inputs to destructively host the FMA instruction, the next best thing is to copy one of the arguments into tmp() and accumulate the FMA there. Once the FMA has happened, we just need to copy that result to dst(). We can of course skip that copy if dst() == tmp(). On x86 we never need that copy; dst() and tmp() are picked using the same logic except that dst may alias one of its inputs, and we only fall into this case after we've already found it doesn't. So we can just assert dst() == tmp() rather than check it like we do on ARM. It's subtle, but I think sound. I'm using logical-or to copy registers around. This is a little lazy, but maybe not as lazy as it looks: on ARM that is _the_ way to copy registers. There's a vmovdqa instruction I could use on x86, TBD. All paths through this new code were being exercised on ARM, but we didn't have anything hitting the tmp case on x86, so I've added a new unit test that hits the corner cases of both implementations. Change-Id: I5422414fc50c64d491b4933b4b580b784596f291 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/228630 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-19 18:56:41 +00:00
skvm::F32 x = b.to_f32(b.load32(arg)),
y = b.mad(x,x,x), // x is needed in the future, so r[x] != r[y].
z = b.mad(y,y,x), // y is needed in the future, but r[z] = r[x] is ok.
w = b.mad(z,z,y), // w can alias z but not y.
v = b.mad(w,y,w); // Got to stop somewhere.
b.store32(arg, b.to_i32(v));
}
test_jit_and_interpreter(b.done(), [&](const skvm::Program& program) {
int x = 2;
program.eval(1, &x);
// x = 2
// y = 2*2 + 2 = 6
// z = 6*6 + 2 = 38
// w = 38*38 + 6 = 1450
// v = 1450*6 + 1450 = 10150
REPORTER_ASSERT(r, x == 10150);
});
}
more unit tests Backfill tests for some uncovered operations. Mostly functional tests, with some targeted at particular corners of code generation, and a few assembler unit tests. This doesn't get up to 100% line coverage, but I think it covers all the non-failure cases. Change-Id: Ib701df0c505aa41e3b2fe3cd429447acb294b752 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/230837 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-30 16:11:09 +00:00
DEF_TEST(SkVM_madder, r) {
skvm::Builder b;
{
skvm::Arg arg = b.varying<float>();
skvm::F32 x = b.bit_cast(b.load32(arg)),
y = b.mad(x,x,x), // x is needed in the future, so r[x] != r[y].
z = b.mad(y,x,y), // r[x] can be reused after this instruction, but not r[y].
w = b.mad(y,y,z);
b.store32(arg, b.bit_cast(w));
}
test_jit_and_interpreter(b.done(), [&](const skvm::Program& program) {
float x = 2.0f;
// y = 2*2 + 2 = 6
// z = 6*2 + 6 = 18
// w = 6*6 + 18 = 54
program.eval(1, &x);
REPORTER_ASSERT(r, x == 54.0f);
});
}
let JIT code hoist when possible This first tries to JIT while hoisting all constants, and if that fails, tries again hoisting no constants. I figure this is one of those 80/20 deals for how to handle constant hoisting and register pressure. This probably mostly moots doing anything fancy like using memory operands with AVX or lane operands with NEON. This _doesn't_ moot hoisting the NEON tbl arguments, which is not yet done here, but probably my next CL. Change-Id: Id09d5cdddcdb45207bdfc914a5a3128a481a26f3 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229058 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-22 19:30:18 +00:00
DEF_TEST(SkVM_hoist, r) {
// This program uses enough constants that it will fail to JIT if we hoist them.
// The JIT will try again without hoisting, and that'll just need 2 registers.
skvm::Builder b;
{
small refactors Change-Id: I58b52d3e1d05d0834be30e00d991636e227cbf0b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/230836 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-30 14:44:30 +00:00
skvm::Arg arg = b.varying<int>();
let JIT code hoist when possible This first tries to JIT while hoisting all constants, and if that fails, tries again hoisting no constants. I figure this is one of those 80/20 deals for how to handle constant hoisting and register pressure. This probably mostly moots doing anything fancy like using memory operands with AVX or lane operands with NEON. This _doesn't_ moot hoisting the NEON tbl arguments, which is not yet done here, but probably my next CL. Change-Id: Id09d5cdddcdb45207bdfc914a5a3128a481a26f3 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229058 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-22 19:30:18 +00:00
skvm::I32 x = b.load32(arg);
for (int i = 0; i < 32; i++) {
x = b.add(x, b.splat(i));
}
b.store32(arg, x);
}
test_jit_and_interpreter(b.done(), [&](const skvm::Program& program) {
int x = 4;
program.eval(1, &x);
// x += 0 + 1 + 2 + 3 + ... + 30 + 31
// x += 496
REPORTER_ASSERT(r, x == 500);
});
}
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
DEF_TEST(SkVM_NewOps, r) {
// Exercise a somewhat arbitrary set of new ops.
skvm::Builder b;
{
small refactors Change-Id: I58b52d3e1d05d0834be30e00d991636e227cbf0b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/230836 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-30 14:44:30 +00:00
skvm::Arg buf = b.varying<int16_t>(),
flesh out SkVM ops a bit more Add missing comparison and selection ops, bit casts, 16-bit memory operations, gathers, uniform loads, and fill in math holes where reasonable. Update some names to be a bit more regular. I think all instructions are implemented in the interpreter, and many tested. More testing and JITs to follow. Change-Id: I8cf377e8b72a86ac950e020892ce82b39e9d7277 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/229893 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-25 19:32:19 +00:00
img = b.uniform(),
uniforms = b.uniform();
skvm::I32 x = b.load16(buf);
x = b.add(x, b.uniform32(uniforms, 0));
x = b.mul(x, b.uniform8 (uniforms, 4));
x = b.sub(x, b.uniform16(uniforms, 6));
skvm::I32 limit = b.uniform32(uniforms, 8);
x = b.select(b.lt(x, b.splat(0)), b.splat(0), x);
x = b.select(b.gt(x, limit ), limit , x);
x = b.gather8(img, x);
b.store16(buf, x);
}
if ((false)) {
SkDynamicMemoryWStream buf;
dump(b, &buf);
sk_sp<SkData> blob = buf.detachAsData();
SkDebugf("%.*s\n", blob->size(), blob->data());
}
test_jit_and_interpreter(b.done(), [&](const skvm::Program& program) {
const int N = 31;
int16_t buf[N];
for (int i = 0; i < N; i++) {
buf[i] = i;
}
const int M = 16;
uint8_t img[M];
for (int i = 0; i < M; i++) {
img[i] = i*i;
}
struct {
int add = 5;
uint8_t mul = 3;
uint16_t sub = 18;
int limit = M-1;
} uniforms;
program.eval(N, buf, img, &uniforms);
for (int i = 0; i < N; i++) {
// Our first math calculates x = (i+5)*3 - 18 a.k.a 3*(i-1).
int x = 3*(i-1);
// Then that's pinned to the limits of img.
if (i < 2) { x = 0; } // Notice i == 1 hits x == 0 exactly...
if (i > 5) { x = 15; } // ...and i == 6 hits x == 15 exactly
REPORTER_ASSERT(r, buf[i] == img[x]);
}
});
}
Reland "extract Assembler so it can be tested" This is a reland of a224fc1105960fe955d32fad28f502148108ecc1 Changes since original: - switch fJIT_K to less error prone fJITMask - guard fJIT Assembler Program member with SKVM_JIT Not really sure why the mips64el-Debug bot's compiler is crashing; it does at least make sense to crash where it does... the file includes SkOpts.h which includes SkVM.h. If no reasonable code transformation can get it working again I'll remove the bot. The -Release version is fine, and mips64el is one of those things I'd happily flush if it blocks progress. In this end I think all this SKVM_JIT and Xbyak stuff should go away and make things simple again, hopefully too simple to crash GCC. :| Original change's description: > extract Assembler so it can be tested > > And start documenting some structs we'll need > to replace xbyak. > > Change-Id: I21c91642799a54e10af85afc8edbe12a9b4aa062 > Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221644 > Reviewed-by: Herb Derby <herb@google.com> > Commit-Queue: Mike Klein <mtklein@google.com> Cq-Include-Trybots: skia.primary:Test-Debian9-Clang-GCE-CPU-AVX2-x86_64-Release-All-SK_CPU_LIMIT_SSE2,Build-Debian9-GCC-mips64el-Debug Change-Id: I6d7c27bc758b23c164ee67067cdfacc291e289fc Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221983 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-18 17:16:06 +00:00
template <typename Fn>
static void test_asm(skiatest::Reporter* r, Fn&& fn, std::initializer_list<uint8_t> expected) {
assemble directly into mmap'd memory Instead of allocating into a std::vector, we do one quick first pass to measure how much memory we need to allocate, mmap enough pages for that, then another real writing pass. This cuts a microsecond or so off the profile. There's another microsecond left to cut if we could eliminate that first measuring pass, but I'm no longer sure it's easy to come up with a good upper limit on the program size now that I'm thinking about the data part of the program as well. vpshufb is our current max instruction at 9 bytes of code, but that also implies another 32 bytes of control data. I'm not sure I feel very clever allocating 41 * |instructions| bytes to be conservatively safe... it seems like ridiculous overkill. Ultimately I found it easier to just measure twice, cut once. Change-Id: I16ccdafbc789711837b41b3d5a557808798eb1b4 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223305 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-24 19:34:02 +00:00
uint8_t buf[4096];
skvm::Assembler a{buf};
Reland "extract Assembler so it can be tested" This is a reland of a224fc1105960fe955d32fad28f502148108ecc1 Changes since original: - switch fJIT_K to less error prone fJITMask - guard fJIT Assembler Program member with SKVM_JIT Not really sure why the mips64el-Debug bot's compiler is crashing; it does at least make sense to crash where it does... the file includes SkOpts.h which includes SkVM.h. If no reasonable code transformation can get it working again I'll remove the bot. The -Release version is fine, and mips64el is one of those things I'd happily flush if it blocks progress. In this end I think all this SKVM_JIT and Xbyak stuff should go away and make things simple again, hopefully too simple to crash GCC. :| Original change's description: > extract Assembler so it can be tested > > And start documenting some structs we'll need > to replace xbyak. > > Change-Id: I21c91642799a54e10af85afc8edbe12a9b4aa062 > Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221644 > Reviewed-by: Herb Derby <herb@google.com> > Commit-Queue: Mike Klein <mtklein@google.com> Cq-Include-Trybots: skia.primary:Test-Debian9-Clang-GCE-CPU-AVX2-x86_64-Release-All-SK_CPU_LIMIT_SSE2,Build-Debian9-GCC-mips64el-Debug Change-Id: I6d7c27bc758b23c164ee67067cdfacc291e289fc Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221983 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-18 17:16:06 +00:00
fn(a);
REPORTER_ASSERT(r, a.size() == expected.size());
assemble directly into mmap'd memory Instead of allocating into a std::vector, we do one quick first pass to measure how much memory we need to allocate, mmap enough pages for that, then another real writing pass. This cuts a microsecond or so off the profile. There's another microsecond left to cut if we could eliminate that first measuring pass, but I'm no longer sure it's easy to come up with a good upper limit on the program size now that I'm thinking about the data part of the program as well. vpshufb is our current max instruction at 9 bytes of code, but that also implies another 32 bytes of control data. I'm not sure I feel very clever allocating 41 * |instructions| bytes to be conservatively safe... it seems like ridiculous overkill. Ultimately I found it easier to just measure twice, cut once. Change-Id: I16ccdafbc789711837b41b3d5a557808798eb1b4 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223305 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-24 19:34:02 +00:00
auto got = (const uint8_t*)buf,
Reland "extract Assembler so it can be tested" This is a reland of a224fc1105960fe955d32fad28f502148108ecc1 Changes since original: - switch fJIT_K to less error prone fJITMask - guard fJIT Assembler Program member with SKVM_JIT Not really sure why the mips64el-Debug bot's compiler is crashing; it does at least make sense to crash where it does... the file includes SkOpts.h which includes SkVM.h. If no reasonable code transformation can get it working again I'll remove the bot. The -Release version is fine, and mips64el is one of those things I'd happily flush if it blocks progress. In this end I think all this SKVM_JIT and Xbyak stuff should go away and make things simple again, hopefully too simple to crash GCC. :| Original change's description: > extract Assembler so it can be tested > > And start documenting some structs we'll need > to replace xbyak. > > Change-Id: I21c91642799a54e10af85afc8edbe12a9b4aa062 > Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221644 > Reviewed-by: Herb Derby <herb@google.com> > Commit-Queue: Mike Klein <mtklein@google.com> Cq-Include-Trybots: skia.primary:Test-Debian9-Clang-GCE-CPU-AVX2-x86_64-Release-All-SK_CPU_LIMIT_SSE2,Build-Debian9-GCC-mips64el-Debug Change-Id: I6d7c27bc758b23c164ee67067cdfacc291e289fc Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221983 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-18 17:16:06 +00:00
want = expected.begin();
for (int i = 0; i < (int)std::min(a.size(), expected.size()); i++) {
first interesting instruction, sub(GP64,imm) Change-Id: I89618ec826f54a24fce8ac5fa61ab27e8ec7d5c2 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221651 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-18 20:01:12 +00:00
REPORTER_ASSERT(r, got[i] == want[i],
"byte %d was %02x, want %02x", i, got[i], want[i]);
Reland "extract Assembler so it can be tested" This is a reland of a224fc1105960fe955d32fad28f502148108ecc1 Changes since original: - switch fJIT_K to less error prone fJITMask - guard fJIT Assembler Program member with SKVM_JIT Not really sure why the mips64el-Debug bot's compiler is crashing; it does at least make sense to crash where it does... the file includes SkOpts.h which includes SkVM.h. If no reasonable code transformation can get it working again I'll remove the bot. The -Release version is fine, and mips64el is one of those things I'd happily flush if it blocks progress. In this end I think all this SKVM_JIT and Xbyak stuff should go away and make things simple again, hopefully too simple to crash GCC. :| Original change's description: > extract Assembler so it can be tested > > And start documenting some structs we'll need > to replace xbyak. > > Change-Id: I21c91642799a54e10af85afc8edbe12a9b4aa062 > Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221644 > Reviewed-by: Herb Derby <herb@google.com> > Commit-Queue: Mike Klein <mtklein@google.com> Cq-Include-Trybots: skia.primary:Test-Debian9-Clang-GCE-CPU-AVX2-x86_64-Release-All-SK_CPU_LIMIT_SSE2,Build-Debian9-GCC-mips64el-Debug Change-Id: I6d7c27bc758b23c164ee67067cdfacc291e289fc Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221983 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-18 17:16:06 +00:00
}
}
DEF_TEST(SkVM_Assembler, r) {
first VEX ymm vector ops - 32x8 i32 add,sub,mul - add I32_Naive bench/test builder to get better i32 mul coverage - minor refactoring all over Change-Id: I13cc19ff37a2da0bcff289ba51baac08f456d6c5 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222485 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-20 16:37:10 +00:00
// Easiest way to generate test cases is
//
// echo '...some asm...' | llvm-mc -show-encoding -x86-asm-syntax=intel
//
// The -x86-asm-syntax=intel bit is optional, controlling the
// input syntax only; the output will always be AT&T op x,y,dst style.
// Our APIs read more like Intel op dst,x,y as op(dst,x,y), so I find
// that a bit easier to use here, despite maybe favoring AT&T overall.
using A = skvm::Assembler;
Reland "extract Assembler so it can be tested" This is a reland of a224fc1105960fe955d32fad28f502148108ecc1 Changes since original: - switch fJIT_K to less error prone fJITMask - guard fJIT Assembler Program member with SKVM_JIT Not really sure why the mips64el-Debug bot's compiler is crashing; it does at least make sense to crash where it does... the file includes SkOpts.h which includes SkVM.h. If no reasonable code transformation can get it working again I'll remove the bot. The -Release version is fine, and mips64el is one of those things I'd happily flush if it blocks progress. In this end I think all this SKVM_JIT and Xbyak stuff should go away and make things simple again, hopefully too simple to crash GCC. :| Original change's description: > extract Assembler so it can be tested > > And start documenting some structs we'll need > to replace xbyak. > > Change-Id: I21c91642799a54e10af85afc8edbe12a9b4aa062 > Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221644 > Reviewed-by: Herb Derby <herb@google.com> > Commit-Queue: Mike Klein <mtklein@google.com> Cq-Include-Trybots: skia.primary:Test-Debian9-Clang-GCE-CPU-AVX2-x86_64-Release-All-SK_CPU_LIMIT_SSE2,Build-Debian9-GCC-mips64el-Debug Change-Id: I6d7c27bc758b23c164ee67067cdfacc291e289fc Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221983 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-18 17:16:06 +00:00
// Our exit strategy from AVX code.
first VEX ymm vector ops - 32x8 i32 add,sub,mul - add I32_Naive bench/test builder to get better i32 mul coverage - minor refactoring all over Change-Id: I13cc19ff37a2da0bcff289ba51baac08f456d6c5 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222485 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-20 16:37:10 +00:00
test_asm(r, [&](A& a) {
Reland "extract Assembler so it can be tested" This is a reland of a224fc1105960fe955d32fad28f502148108ecc1 Changes since original: - switch fJIT_K to less error prone fJITMask - guard fJIT Assembler Program member with SKVM_JIT Not really sure why the mips64el-Debug bot's compiler is crashing; it does at least make sense to crash where it does... the file includes SkOpts.h which includes SkVM.h. If no reasonable code transformation can get it working again I'll remove the bot. The -Release version is fine, and mips64el is one of those things I'd happily flush if it blocks progress. In this end I think all this SKVM_JIT and Xbyak stuff should go away and make things simple again, hopefully too simple to crash GCC. :| Original change's description: > extract Assembler so it can be tested > > And start documenting some structs we'll need > to replace xbyak. > > Change-Id: I21c91642799a54e10af85afc8edbe12a9b4aa062 > Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221644 > Reviewed-by: Herb Derby <herb@google.com> > Commit-Queue: Mike Klein <mtklein@google.com> Cq-Include-Trybots: skia.primary:Test-Debian9-Clang-GCE-CPU-AVX2-x86_64-Release-All-SK_CPU_LIMIT_SSE2,Build-Debian9-GCC-mips64el-Debug Change-Id: I6d7c27bc758b23c164ee67067cdfacc291e289fc Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221983 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-18 17:16:06 +00:00
a.vzeroupper();
a.ret();
},{
0xc5, 0xf8, 0x77,
0xc3,
});
small cleanups - get rid of variadic Assembler::byte()... not used very often - rename Assembler::byte(ptr,n) to bytes() - align with 0 bytes, get rid of nop() Change-Id: I7564d3bad00e3f0d1c7a80153c445966914fccf0 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/228601 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-19 14:44:47 +00:00
// Align should pad with zero
first VEX ymm vector ops - 32x8 i32 add,sub,mul - add I32_Naive bench/test builder to get better i32 mul coverage - minor refactoring all over Change-Id: I13cc19ff37a2da0bcff289ba51baac08f456d6c5 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222485 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-20 16:37:10 +00:00
test_asm(r, [&](A& a) {
Reland "extract Assembler so it can be tested" This is a reland of a224fc1105960fe955d32fad28f502148108ecc1 Changes since original: - switch fJIT_K to less error prone fJITMask - guard fJIT Assembler Program member with SKVM_JIT Not really sure why the mips64el-Debug bot's compiler is crashing; it does at least make sense to crash where it does... the file includes SkOpts.h which includes SkVM.h. If no reasonable code transformation can get it working again I'll remove the bot. The -Release version is fine, and mips64el is one of those things I'd happily flush if it blocks progress. In this end I think all this SKVM_JIT and Xbyak stuff should go away and make things simple again, hopefully too simple to crash GCC. :| Original change's description: > extract Assembler so it can be tested > > And start documenting some structs we'll need > to replace xbyak. > > Change-Id: I21c91642799a54e10af85afc8edbe12a9b4aa062 > Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221644 > Reviewed-by: Herb Derby <herb@google.com> > Commit-Queue: Mike Klein <mtklein@google.com> Cq-Include-Trybots: skia.primary:Test-Debian9-Clang-GCE-CPU-AVX2-x86_64-Release-All-SK_CPU_LIMIT_SSE2,Build-Debian9-GCC-mips64el-Debug Change-Id: I6d7c27bc758b23c164ee67067cdfacc291e289fc Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221983 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-18 17:16:06 +00:00
a.ret();
a.align(4);
},{
0xc3,
small cleanups - get rid of variadic Assembler::byte()... not used very often - rename Assembler::byte(ptr,n) to bytes() - align with 0 bytes, get rid of nop() Change-Id: I7564d3bad00e3f0d1c7a80153c445966914fccf0 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/228601 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-19 14:44:47 +00:00
0x00, 0x00, 0x00,
Reland "extract Assembler so it can be tested" This is a reland of a224fc1105960fe955d32fad28f502148108ecc1 Changes since original: - switch fJIT_K to less error prone fJITMask - guard fJIT Assembler Program member with SKVM_JIT Not really sure why the mips64el-Debug bot's compiler is crashing; it does at least make sense to crash where it does... the file includes SkOpts.h which includes SkVM.h. If no reasonable code transformation can get it working again I'll remove the bot. The -Release version is fine, and mips64el is one of those things I'd happily flush if it blocks progress. In this end I think all this SKVM_JIT and Xbyak stuff should go away and make things simple again, hopefully too simple to crash GCC. :| Original change's description: > extract Assembler so it can be tested > > And start documenting some structs we'll need > to replace xbyak. > > Change-Id: I21c91642799a54e10af85afc8edbe12a9b4aa062 > Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221644 > Reviewed-by: Herb Derby <herb@google.com> > Commit-Queue: Mike Klein <mtklein@google.com> Cq-Include-Trybots: skia.primary:Test-Debian9-Clang-GCE-CPU-AVX2-x86_64-Release-All-SK_CPU_LIMIT_SSE2,Build-Debian9-GCC-mips64el-Debug Change-Id: I6d7c27bc758b23c164ee67067cdfacc291e289fc Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221983 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-18 17:16:06 +00:00
});
first interesting instruction, sub(GP64,imm) Change-Id: I89618ec826f54a24fce8ac5fa61ab27e8ec7d5c2 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221651 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-18 20:01:12 +00:00
first VEX ymm vector ops - 32x8 i32 add,sub,mul - add I32_Naive bench/test builder to get better i32 mul coverage - minor refactoring all over Change-Id: I13cc19ff37a2da0bcff289ba51baac08f456d6c5 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222485 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-20 16:37:10 +00:00
test_asm(r, [&](A& a) {
a.add(A::rax, 8); // Always good to test rax.
a.sub(A::rax, 32);
add(GP64 dst, int imm) Change-Id: I6aaa1dc3ff3a9529f87ff58a2ae1fc5f59bc626b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221653 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-18 20:26:08 +00:00
first VEX ymm vector ops - 32x8 i32 add,sub,mul - add I32_Naive bench/test builder to get better i32 mul coverage - minor refactoring all over Change-Id: I13cc19ff37a2da0bcff289ba51baac08f456d6c5 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222485 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-20 16:37:10 +00:00
a.add(A::rdi, 12); // Last 0x48 REX
a.sub(A::rdi, 8);
add(GP64 dst, int imm) Change-Id: I6aaa1dc3ff3a9529f87ff58a2ae1fc5f59bc626b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221653 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-18 20:26:08 +00:00
fix bug for add/sub with r8-r15 I had been setting the REX R bit to select high registers, but you actually set the B bit. Don't know how I got that wrong before... the leading byte should be 49 not 4c. $ cat test.s foo: addq $7, %r8 $ clang -c test.s && objdump -d test.o 0000000000000000 <foo>: 0: 49 83 c0 07 add $0x7,%r8 Change-Id: I039e1c4f4ea20523a1e2cc9bcf5f6d9321a6223b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227177 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-12 17:29:39 +00:00
a.add(A::r8 , 7); // First 0x49 REX
first VEX ymm vector ops - 32x8 i32 add,sub,mul - add I32_Naive bench/test builder to get better i32 mul coverage - minor refactoring all over Change-Id: I13cc19ff37a2da0bcff289ba51baac08f456d6c5 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222485 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-20 16:37:10 +00:00
a.sub(A::r8 , 4);
add(GP64 dst, int imm) Change-Id: I6aaa1dc3ff3a9529f87ff58a2ae1fc5f59bc626b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221653 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-18 20:26:08 +00:00
first VEX ymm vector ops - 32x8 i32 add,sub,mul - add I32_Naive bench/test builder to get better i32 mul coverage - minor refactoring all over Change-Id: I13cc19ff37a2da0bcff289ba51baac08f456d6c5 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222485 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-20 16:37:10 +00:00
a.add(A::rsi, 128); // Requires 4 byte immediate.
a.sub(A::r8 , 1000000);
first interesting instruction, sub(GP64,imm) Change-Id: I89618ec826f54a24fce8ac5fa61ab27e8ec7d5c2 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221651 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-18 20:01:12 +00:00
},{
add(GP64 dst, int imm) Change-Id: I6aaa1dc3ff3a9529f87ff58a2ae1fc5f59bc626b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221653 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-18 20:26:08 +00:00
0x48, 0x83, 0b11'000'000, 0x08,
first interesting instruction, sub(GP64,imm) Change-Id: I89618ec826f54a24fce8ac5fa61ab27e8ec7d5c2 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221651 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-18 20:01:12 +00:00
0x48, 0x83, 0b11'101'000, 0x20,
add(GP64 dst, int imm) Change-Id: I6aaa1dc3ff3a9529f87ff58a2ae1fc5f59bc626b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221653 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-18 20:26:08 +00:00
0x48, 0x83, 0b11'000'111, 0x0c,
first interesting instruction, sub(GP64,imm) Change-Id: I89618ec826f54a24fce8ac5fa61ab27e8ec7d5c2 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221651 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-18 20:01:12 +00:00
0x48, 0x83, 0b11'101'111, 0x08,
add(GP64 dst, int imm) Change-Id: I6aaa1dc3ff3a9529f87ff58a2ae1fc5f59bc626b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221653 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-18 20:26:08 +00:00
fix bug for add/sub with r8-r15 I had been setting the REX R bit to select high registers, but you actually set the B bit. Don't know how I got that wrong before... the leading byte should be 49 not 4c. $ cat test.s foo: addq $7, %r8 $ clang -c test.s && objdump -d test.o 0000000000000000 <foo>: 0: 49 83 c0 07 add $0x7,%r8 Change-Id: I039e1c4f4ea20523a1e2cc9bcf5f6d9321a6223b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227177 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-12 17:29:39 +00:00
0x49, 0x83, 0b11'000'000, 0x07,
0x49, 0x83, 0b11'101'000, 0x04,
add(GP64 dst, int imm) Change-Id: I6aaa1dc3ff3a9529f87ff58a2ae1fc5f59bc626b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221653 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-18 20:26:08 +00:00
0x48, 0x81, 0b11'000'110, 0x80, 0x00, 0x00, 0x00,
fix bug for add/sub with r8-r15 I had been setting the REX R bit to select high registers, but you actually set the B bit. Don't know how I got that wrong before... the leading byte should be 49 not 4c. $ cat test.s foo: addq $7, %r8 $ clang -c test.s && objdump -d test.o 0000000000000000 <foo>: 0: 49 83 c0 07 add $0x7,%r8 Change-Id: I039e1c4f4ea20523a1e2cc9bcf5f6d9321a6223b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227177 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-12 17:29:39 +00:00
0x49, 0x81, 0b11'101'000, 0x40, 0x42, 0x0f, 0x00,
first interesting instruction, sub(GP64,imm) Change-Id: I89618ec826f54a24fce8ac5fa61ab27e8ec7d5c2 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221651 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-18 20:01:12 +00:00
});
first VEX ymm vector ops - 32x8 i32 add,sub,mul - add I32_Naive bench/test builder to get better i32 mul coverage - minor refactoring all over Change-Id: I13cc19ff37a2da0bcff289ba51baac08f456d6c5 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222485 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-20 16:37:10 +00:00
test_asm(r, [&](A& a) {
a.vpaddd (A::ymm0, A::ymm1, A::ymm2); // Low registers and 0x0f map -> 2-byte VEX.
a.vpaddd (A::ymm8, A::ymm1, A::ymm2); // A high dst register is ok -> 2-byte VEX.
a.vpaddd (A::ymm0, A::ymm8, A::ymm2); // A high first argument register -> 2-byte VEX.
a.vpaddd (A::ymm0, A::ymm1, A::ymm8); // A high second argument -> 3-byte VEX.
a.vpmulld(A::ymm0, A::ymm1, A::ymm2); // Using non-0x0f map instruction -> 3-byte VEX.
a.vpsubd (A::ymm0, A::ymm1, A::ymm2); // Test vpsubd to ensure argument order is right.
},{
/* VEX */ /*op*/ /*modRM*/
0xc5, 0xf5, 0xfe, 0xc2,
0xc5, 0x75, 0xfe, 0xc2,
0xc5, 0xbd, 0xfe, 0xc2,
0xc4, 0xc1, 0x75, 0xfe, 0xc0,
0xc4, 0xe2, 0x75, 0x40, 0xc2,
0xc5, 0xf5, 0xfa, 0xc2,
});
two register + immediate ops The encoding kind of all goes through the same paths, as the three argument instructions, but like the nursery rhyme when there are only two they kind of all roll over and the op-extension hops into the bed. vpermq is the first place we need to set the W bit to indicate a 64-bit lane operation, so a little minimal plumbing for that. It takes its arguments a little differently too, passing dst where you'd expect, the source where we'd pass y, and requiring us to pass literal 0000 for the vvvv bits in VEX (inverted as normal to literal 1111). Change-Id: I91a4cd1b316eb908992631ce8b2cb3c62078e8c6 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222565 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-20 20:03:44 +00:00
test_asm(r, [&](A& a) {
a.vpsrld(A::ymm15, A::ymm2, 8);
a.vpsrld(A::ymm0 , A::ymm8, 5);
},{
0xc5, 0x85, 0x72,0xd2, 0x08,
0xc4,0xc1,0x7d, 0x72,0xd0, 0x05,
});
test_asm(r, [&](A& a) {
a.vpermq(A::ymm1, A::ymm2, 5);
},{
0xc4,0xe3,0xfd, 0x00,0xca, 0x05,
});
vbroadcastss This shows off a little how easy backwards-only labels are. The rip == rbp + Mod::Indirect convention isn't something you'd be able to guess without just looking at the docs. I'm not actually sure if you can only use rbp or also r13, but LLVM seems to always do the equivalent of rbp... might just be that high bit in VEX is ignored: they're registers 5 and 13, 8 apart, only distinguished by that bit. Convenienly RIP addressing is always 32-bit, so there's no benefit to spending time checking whether the offset fits in a byte, though most of our offsets would. Change-Id: I01b7fb1500667e1bf98490d5144459f92e1b375d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222857 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-21 17:37:22 +00:00
test_asm(r, [&](A& a) {
A::Label l = a.here();
a.byte(1);
a.byte(2);
a.byte(3);
a.byte(4);
vpshufb Change-Id: If23681e7a34a091cb78e5bd469d71c56b9cf5dc8 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222858 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-21 19:19:21 +00:00
make all instructions take two-way labels This turned out to be quite an easy transformation with yesterday's work already done. No codegen changes. Change-Id: Ife19ab7731514c54cfed963a6d2e9b1ec2246997 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227137 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-12 14:22:21 +00:00
a.vbroadcastss(A::ymm0 , &l);
a.vbroadcastss(A::ymm1 , &l);
a.vbroadcastss(A::ymm8 , &l);
a.vbroadcastss(A::ymm15, &l);
vpshufb Change-Id: If23681e7a34a091cb78e5bd469d71c56b9cf5dc8 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222858 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-21 19:19:21 +00:00
make all instructions take two-way labels This turned out to be quite an easy transformation with yesterday's work already done. No codegen changes. Change-Id: Ife19ab7731514c54cfed963a6d2e9b1ec2246997 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227137 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-12 14:22:21 +00:00
a.vpshufb(A::ymm4, A::ymm3, &l);
vbroadcastss This shows off a little how easy backwards-only labels are. The rip == rbp + Mod::Indirect convention isn't something you'd be able to guess without just looking at the docs. I'm not actually sure if you can only use rbp or also r13, but LLVM seems to always do the equivalent of rbp... might just be that high bit in VEX is ignored: they're registers 5 and 13, 8 apart, only distinguished by that bit. Convenienly RIP addressing is always 32-bit, so there's no benefit to spending time checking whether the offset fits in a byte, though most of our offsets would. Change-Id: I01b7fb1500667e1bf98490d5144459f92e1b375d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222857 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-21 17:37:22 +00:00
},{
0x01, 0x02, 0x03, 0x4,
vpshufb Change-Id: If23681e7a34a091cb78e5bd469d71c56b9cf5dc8 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222858 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-21 19:19:21 +00:00
vbroadcastss This shows off a little how easy backwards-only labels are. The rip == rbp + Mod::Indirect convention isn't something you'd be able to guess without just looking at the docs. I'm not actually sure if you can only use rbp or also r13, but LLVM seems to always do the equivalent of rbp... might just be that high bit in VEX is ignored: they're registers 5 and 13, 8 apart, only distinguished by that bit. Convenienly RIP addressing is always 32-bit, so there's no benefit to spending time checking whether the offset fits in a byte, though most of our offsets would. Change-Id: I01b7fb1500667e1bf98490d5144459f92e1b375d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222857 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-21 17:37:22 +00:00
/* VEX */ /*op*/ /* ModRM */ /* offset */
0xc4, 0xe2, 0x7d, 0x18, 0b00'000'101, 0xf3,0xff,0xff,0xff, // 0xfffffff3 == -13
0xc4, 0xe2, 0x7d, 0x18, 0b00'001'101, 0xea,0xff,0xff,0xff, // 0xffffffea == -22
0xc4, 0x62, 0x7d, 0x18, 0b00'000'101, 0xe1,0xff,0xff,0xff, // 0xffffffe1 == -31
0xc4, 0x62, 0x7d, 0x18, 0b00'111'101, 0xd8,0xff,0xff,0xff, // 0xffffffd8 == -40
vpshufb Change-Id: If23681e7a34a091cb78e5bd469d71c56b9cf5dc8 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222858 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-21 19:19:21 +00:00
0xc4, 0xe2, 0x65, 0x00, 0b00'100'101, 0xcf,0xff,0xff,0xff, // 0xffffffcf == -49
vbroadcastss This shows off a little how easy backwards-only labels are. The rip == rbp + Mod::Indirect convention isn't something you'd be able to guess without just looking at the docs. I'm not actually sure if you can only use rbp or also r13, but LLVM seems to always do the equivalent of rbp... might just be that high bit in VEX is ignored: they're registers 5 and 13, 8 apart, only distinguished by that bit. Convenienly RIP addressing is always 32-bit, so there's no benefit to spending time checking whether the offset fits in a byte, though most of our offsets would. Change-Id: I01b7fb1500667e1bf98490d5144459f92e1b375d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222857 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-21 17:37:22 +00:00
});
jne Change-Id: Ie6b033367e24ae92f6e246963f1f014c4d7cf013 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222859 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-21 19:42:09 +00:00
add vbroadcastss(Ymm, GP64, int) vbroadcastss with a register argument and immediate offset implements uniform32. And this turns on the JIT for some new SkVMBlitter paths that pass more arguments that I'd previously wired up, so add a few more. Change-Id: I66db1286dcdb2c4a4ba7c43f2dc2cd13564d4d34 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/232056 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-08-02 15:15:51 +00:00
test_asm(r, [&](A& a) {
a.vbroadcastss(A::ymm0, A::rdi, 0);
a.vbroadcastss(A::ymm13, A::r14, 7);
a.vbroadcastss(A::ymm8, A::rdx, -12);
a.vbroadcastss(A::ymm8, A::rdx, 400);
x86 uniform8 Add vbroadcastss(Ymm, Xmm) and expand movzbl() to support an offset. The sequence movzbl (load a byte, zero-extend to 4 byte) vmovd (move that 4 byte value to an xmm) vbroadcastss (broadcast low 4 bytes of xmm to all lanes of ymm) implements uniform8. Change-Id: I1d3125920d19dcb3cad5980495310bc95b9dffee Reviewed-on: https://skia-review.googlesource.com/c/skia/+/232057 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-08-02 15:54:23 +00:00
a.vbroadcastss(A::ymm8, A::xmm0);
a.vbroadcastss(A::ymm0, A::xmm13);
add vbroadcastss(Ymm, GP64, int) vbroadcastss with a register argument and immediate offset implements uniform32. And this turns on the JIT for some new SkVMBlitter paths that pass more arguments that I'd previously wired up, so add a few more. Change-Id: I66db1286dcdb2c4a4ba7c43f2dc2cd13564d4d34 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/232056 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-08-02 15:15:51 +00:00
},{
/* VEX */ /*op*/ /*ModRM*/ /*offset*/
0xc4,0xe2,0x7d, 0x18, 0b00'000'111,
0xc4,0x42,0x7d, 0x18, 0b01'101'110, 0x07,
0xc4,0x62,0x7d, 0x18, 0b01'000'010, 0xf4,
0xc4,0x62,0x7d, 0x18, 0b10'000'010, 0x90,0x01,0x00,0x00,
x86 uniform8 Add vbroadcastss(Ymm, Xmm) and expand movzbl() to support an offset. The sequence movzbl (load a byte, zero-extend to 4 byte) vmovd (move that 4 byte value to an xmm) vbroadcastss (broadcast low 4 bytes of xmm to all lanes of ymm) implements uniform8. Change-Id: I1d3125920d19dcb3cad5980495310bc95b9dffee Reviewed-on: https://skia-review.googlesource.com/c/skia/+/232057 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-08-02 15:54:23 +00:00
0xc4,0x62,0x7d, 0x18, 0b11'000'000,
0xc4,0xc2,0x7d, 0x18, 0b11'000'101,
add vbroadcastss(Ymm, GP64, int) vbroadcastss with a register argument and immediate offset implements uniform32. And this turns on the JIT for some new SkVMBlitter paths that pass more arguments that I'd previously wired up, so add a few more. Change-Id: I66db1286dcdb2c4a4ba7c43f2dc2cd13564d4d34 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/232056 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-08-02 15:15:51 +00:00
});
jne Change-Id: Ie6b033367e24ae92f6e246963f1f014c4d7cf013 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222859 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-21 19:42:09 +00:00
test_asm(r, [&](A& a) {
A::Label l = a.here();
make all instructions take two-way labels This turned out to be quite an easy transformation with yesterday's work already done. No codegen changes. Change-Id: Ife19ab7731514c54cfed963a6d2e9b1ec2246997 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227137 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-12 14:22:21 +00:00
a.jne(&l);
a.jne(&l);
handle x86 tail in JIT code too Basically the same deal as aarch64: - a bunch of instructions to rewrite control flow to be two loops, body and tail - a bunch of instructions to support scalar loads and stores in the tail We can now remove the JIT::mask field. I've removed the SkUNREACHABLE I'd put in for the ARM code... as written the interpreter is still reachable by the loser if two threads race to JIT the program. Medium term I plan to move JIT compilation to a more proactive time, eliminating the need for the lock and letting the interpreter become truly unreachable. I had a little bit of a false start with what instructions to use for scalar load8 and store8, first starting with instructions that loaded via GP registers, then remembering vpinsrb and vpextrb can take a memory argument, loading into xmm directly. I've left the first instructions I used in the file, still implemented but only used from the unit tests. They're pretty common and will probably be useful some day. Change-Id: I471b13026af4b1c6e861a53159f9df5f0285447c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227178 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-12 17:32:45 +00:00
a.je (&l);
a.jmp(&l);
a.jl (&l);
a.cmp(A::rdx, 0);
a.cmp(A::rax, 12);
a.cmp(A::r14, 2000000000);
jne Change-Id: Ie6b033367e24ae92f6e246963f1f014c4d7cf013 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222859 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-21 19:42:09 +00:00
},{
handle x86 tail in JIT code too Basically the same deal as aarch64: - a bunch of instructions to rewrite control flow to be two loops, body and tail - a bunch of instructions to support scalar loads and stores in the tail We can now remove the JIT::mask field. I've removed the SkUNREACHABLE I'd put in for the ARM code... as written the interpreter is still reachable by the loser if two threads race to JIT the program. Medium term I plan to move JIT compilation to a more proactive time, eliminating the need for the lock and letting the interpreter become truly unreachable. I had a little bit of a false start with what instructions to use for scalar load8 and store8, first starting with instructions that loaded via GP registers, then remembering vpinsrb and vpextrb can take a memory argument, loading into xmm directly. I've left the first instructions I used in the file, still implemented but only used from the unit tests. They're pretty common and will probably be useful some day. Change-Id: I471b13026af4b1c6e861a53159f9df5f0285447c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227178 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-12 17:32:45 +00:00
0x0f,0x85, 0xfa,0xff,0xff,0xff, // near jne -6 bytes
0x0f,0x85, 0xf4,0xff,0xff,0xff, // near jne -12 bytes
0x0f,0x84, 0xee,0xff,0xff,0xff, // near je -18 bytes
0xe9, 0xe9,0xff,0xff,0xff, // near jmp -23 bytes
0x0f,0x8c, 0xe3,0xff,0xff,0xff, // near jl -29 bytes
0x48,0x83,0xfa,0x00,
0x48,0x83,0xf8,0x0c,
0x49,0x81,0xfe,0x00,0x94,0x35,0x77,
jne Change-Id: Ie6b033367e24ae92f6e246963f1f014c4d7cf013 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222859 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-21 19:42:09 +00:00
});
vmovups, both ways Change-Id: I6790b59df1e4b4ee9b36b24819586411eff6324d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222623 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-21 20:52:55 +00:00
test_asm(r, [&](A& a) {
a.vmovups(A::ymm5, A::rsi);
a.vmovups(A::rsi, A::ymm5);
vpmovzxbd Change-Id: I3ae8b3a6a109f6286dfc28a1c2b8e9aea913bcae Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222626 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-21 21:06:03 +00:00
x86 store16 Nothing particularly tricky. Very much like store8, but with one fewer shuffle. This lets some of the 565 blitters JIT! Change-Id: I853905bda30a0cda89f3fcb5fef1dfe62725063b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/232059 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-08-02 16:43:43 +00:00
a.vmovups(A::rsi, A::xmm5);
x86, load16 Very similar to load8. The only interesting thing is how different vpinsrw is from vpinsrb (and vpinsrd and vpinsrq)... different map of instructions entirely. Change-Id: Ia413b83604dd2d277d59495c5f693f505c35be9f Reviewed-on: https://skia-review.googlesource.com/c/skia/+/232058 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-08-02 16:18:00 +00:00
a.vpmovzxwd(A::ymm4, A::rsi);
vpmovzxbd Change-Id: I3ae8b3a6a109f6286dfc28a1c2b8e9aea913bcae Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222626 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-21 21:06:03 +00:00
a.vpmovzxbd(A::ymm4, A::rsi);
vmovq Change-Id: Id83573bb7e66c0a6316917ae17abe7f56a172941 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222629 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-21 21:20:24 +00:00
a.vmovq(A::rdx, A::xmm15);
vmovups, both ways Change-Id: I6790b59df1e4b4ee9b36b24819586411eff6324d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222623 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-21 20:52:55 +00:00
},{
vpmovzxbd Change-Id: I3ae8b3a6a109f6286dfc28a1c2b8e9aea913bcae Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222626 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-21 21:06:03 +00:00
/* VEX */ /*Op*/ /* ModRM */
0xc5, 0xfc, 0x10, 0b00'101'110,
0xc5, 0xfc, 0x11, 0b00'101'110,
x86 store16 Nothing particularly tricky. Very much like store8, but with one fewer shuffle. This lets some of the 565 blitters JIT! Change-Id: I853905bda30a0cda89f3fcb5fef1dfe62725063b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/232059 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-08-02 16:43:43 +00:00
0xc5, 0xf8, 0x11, 0b00'101'110,
x86, load16 Very similar to load8. The only interesting thing is how different vpinsrw is from vpinsrb (and vpinsrd and vpinsrq)... different map of instructions entirely. Change-Id: Ia413b83604dd2d277d59495c5f693f505c35be9f Reviewed-on: https://skia-review.googlesource.com/c/skia/+/232058 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-08-02 16:18:00 +00:00
0xc4,0xe2,0x7d, 0x33, 0b00'100'110,
vpmovzxbd Change-Id: I3ae8b3a6a109f6286dfc28a1c2b8e9aea913bcae Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222626 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-21 21:06:03 +00:00
0xc4,0xe2,0x7d, 0x31, 0b00'100'110,
vmovq Change-Id: Id83573bb7e66c0a6316917ae17abe7f56a172941 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222629 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-21 21:20:24 +00:00
0xc5, 0x79, 0xd6, 0b00'111'010,
vmovups, both ways Change-Id: I6790b59df1e4b4ee9b36b24819586411eff6324d Reviewed-on: https://skia-review.googlesource.com/c/skia/+/222623 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-21 20:52:55 +00:00
});
add bit_clear I was just reading the ARM docs and realized that their BIC ("BIt Clear") is the same as SSE's ANDN ("AND Not") instruction. It's kind of a neat little tool to have laying around... comes up more than you'd think, and it's sometimes the clearest way to express what you're doing, as in the changed program here where the comment is "mask away the low bits". That's a bit_clear with a mask for what you want to clear away! And the real reason to write this up is that I want to have a CL to point to that shows how to add an instruction top to bottom. Change-Id: I99690ed9c1009427b3986955e7ae6264de4d215c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223120 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com> Reviewed-by: Mike Reed <reed@google.com>
2019-06-24 00:35:28 +00:00
handle x86 tail in JIT code too Basically the same deal as aarch64: - a bunch of instructions to rewrite control flow to be two loops, body and tail - a bunch of instructions to support scalar loads and stores in the tail We can now remove the JIT::mask field. I've removed the SkUNREACHABLE I'd put in for the ARM code... as written the interpreter is still reachable by the loser if two threads race to JIT the program. Medium term I plan to move JIT compilation to a more proactive time, eliminating the need for the lock and letting the interpreter become truly unreachable. I had a little bit of a false start with what instructions to use for scalar load8 and store8, first starting with instructions that loaded via GP registers, then remembering vpinsrb and vpextrb can take a memory argument, loading into xmm directly. I've left the first instructions I used in the file, still implemented but only used from the unit tests. They're pretty common and will probably be useful some day. Change-Id: I471b13026af4b1c6e861a53159f9df5f0285447c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227178 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-12 17:32:45 +00:00
test_asm(r, [&](A& a) {
x86 uniform8 Add vbroadcastss(Ymm, Xmm) and expand movzbl() to support an offset. The sequence movzbl (load a byte, zero-extend to 4 byte) vmovd (move that 4 byte value to an xmm) vbroadcastss (broadcast low 4 bytes of xmm to all lanes of ymm) implements uniform8. Change-Id: I1d3125920d19dcb3cad5980495310bc95b9dffee Reviewed-on: https://skia-review.googlesource.com/c/skia/+/232057 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-08-02 15:54:23 +00:00
a.movzbl(A::rax, A::rsi, 0); // Low registers for src and dst.
a.movzbl(A::rax, A::r8, 0); // High src register.
a.movzbl(A::r8 , A::rsi, 0); // High dst register.
a.movzbl(A::r8, A::rsi, 12);
a.movzbl(A::r8, A::rsi, 400);
handle x86 tail in JIT code too Basically the same deal as aarch64: - a bunch of instructions to rewrite control flow to be two loops, body and tail - a bunch of instructions to support scalar loads and stores in the tail We can now remove the JIT::mask field. I've removed the SkUNREACHABLE I'd put in for the ARM code... as written the interpreter is still reachable by the loser if two threads race to JIT the program. Medium term I plan to move JIT compilation to a more proactive time, eliminating the need for the lock and letting the interpreter become truly unreachable. I had a little bit of a false start with what instructions to use for scalar load8 and store8, first starting with instructions that loaded via GP registers, then remembering vpinsrb and vpextrb can take a memory argument, loading into xmm directly. I've left the first instructions I used in the file, still implemented but only used from the unit tests. They're pretty common and will probably be useful some day. Change-Id: I471b13026af4b1c6e861a53159f9df5f0285447c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227178 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-12 17:32:45 +00:00
a.vmovd(A::rax, A::xmm0);
a.vmovd(A::rax, A::xmm8);
a.vmovd(A::r8, A::xmm0);
a.vmovd(A::xmm0, A::rax);
a.vmovd(A::xmm8, A::rax);
a.vmovd(A::xmm0, A::r8);
a.vmovd_direct(A::rax, A::xmm0);
a.vmovd_direct(A::rax, A::xmm8);
a.vmovd_direct(A::r8, A::xmm0);
a.vmovd_direct(A::xmm0, A::rax);
a.vmovd_direct(A::xmm8, A::rax);
a.vmovd_direct(A::xmm0, A::r8);
a.movb(A::rdx, A::rax);
a.movb(A::rdx, A::r8);
a.movb(A::r8 , A::rax);
},{
0x0f,0xb6,0x06,
0x41,0x0f,0xb6,0x00,
0x44,0x0f,0xb6,0x06,
x86 uniform8 Add vbroadcastss(Ymm, Xmm) and expand movzbl() to support an offset. The sequence movzbl (load a byte, zero-extend to 4 byte) vmovd (move that 4 byte value to an xmm) vbroadcastss (broadcast low 4 bytes of xmm to all lanes of ymm) implements uniform8. Change-Id: I1d3125920d19dcb3cad5980495310bc95b9dffee Reviewed-on: https://skia-review.googlesource.com/c/skia/+/232057 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-08-02 15:54:23 +00:00
0x44,0x0f,0xb6,0x46, 12,
0x44,0x0f,0xb6,0x86, 0x90,0x01,0x00,0x00,
handle x86 tail in JIT code too Basically the same deal as aarch64: - a bunch of instructions to rewrite control flow to be two loops, body and tail - a bunch of instructions to support scalar loads and stores in the tail We can now remove the JIT::mask field. I've removed the SkUNREACHABLE I'd put in for the ARM code... as written the interpreter is still reachable by the loser if two threads race to JIT the program. Medium term I plan to move JIT compilation to a more proactive time, eliminating the need for the lock and letting the interpreter become truly unreachable. I had a little bit of a false start with what instructions to use for scalar load8 and store8, first starting with instructions that loaded via GP registers, then remembering vpinsrb and vpextrb can take a memory argument, loading into xmm directly. I've left the first instructions I used in the file, still implemented but only used from the unit tests. They're pretty common and will probably be useful some day. Change-Id: I471b13026af4b1c6e861a53159f9df5f0285447c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227178 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-12 17:32:45 +00:00
0xc5,0xf9,0x7e,0x00,
0xc5,0x79,0x7e,0x00,
0xc4,0xc1,0x79,0x7e,0x00,
0xc5,0xf9,0x6e,0x00,
0xc5,0x79,0x6e,0x00,
0xc4,0xc1,0x79,0x6e,0x00,
0xc5,0xf9,0x7e,0xc0,
0xc5,0x79,0x7e,0xc0,
0xc4,0xc1,0x79,0x7e,0xc0,
0xc5,0xf9,0x6e,0xc0,
0xc5,0x79,0x6e,0xc0,
0xc4,0xc1,0x79,0x6e,0xc0,
0x88, 0x02,
0x44, 0x88, 0x02,
0x41, 0x88, 0x00,
});
test_asm(r, [&](A& a) {
x86, load16 Very similar to load8. The only interesting thing is how different vpinsrw is from vpinsrb (and vpinsrd and vpinsrq)... different map of instructions entirely. Change-Id: Ia413b83604dd2d277d59495c5f693f505c35be9f Reviewed-on: https://skia-review.googlesource.com/c/skia/+/232058 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-08-02 16:18:00 +00:00
a.vpinsrw(A::xmm1, A::xmm8, A::rsi, 4);
a.vpinsrw(A::xmm8, A::xmm1, A::r8, 12);
handle x86 tail in JIT code too Basically the same deal as aarch64: - a bunch of instructions to rewrite control flow to be two loops, body and tail - a bunch of instructions to support scalar loads and stores in the tail We can now remove the JIT::mask field. I've removed the SkUNREACHABLE I'd put in for the ARM code... as written the interpreter is still reachable by the loser if two threads race to JIT the program. Medium term I plan to move JIT compilation to a more proactive time, eliminating the need for the lock and letting the interpreter become truly unreachable. I had a little bit of a false start with what instructions to use for scalar load8 and store8, first starting with instructions that loaded via GP registers, then remembering vpinsrb and vpextrb can take a memory argument, loading into xmm directly. I've left the first instructions I used in the file, still implemented but only used from the unit tests. They're pretty common and will probably be useful some day. Change-Id: I471b13026af4b1c6e861a53159f9df5f0285447c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227178 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-12 17:32:45 +00:00
a.vpinsrb(A::xmm1, A::xmm8, A::rsi, 4);
a.vpinsrb(A::xmm8, A::xmm1, A::r8, 12);
x86 store16 Nothing particularly tricky. Very much like store8, but with one fewer shuffle. This lets some of the 565 blitters JIT! Change-Id: I853905bda30a0cda89f3fcb5fef1dfe62725063b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/232059 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-08-02 16:43:43 +00:00
a.vpextrw(A::rsi, A::xmm8, 7);
a.vpextrw(A::r8, A::xmm1, 15);
handle x86 tail in JIT code too Basically the same deal as aarch64: - a bunch of instructions to rewrite control flow to be two loops, body and tail - a bunch of instructions to support scalar loads and stores in the tail We can now remove the JIT::mask field. I've removed the SkUNREACHABLE I'd put in for the ARM code... as written the interpreter is still reachable by the loser if two threads race to JIT the program. Medium term I plan to move JIT compilation to a more proactive time, eliminating the need for the lock and letting the interpreter become truly unreachable. I had a little bit of a false start with what instructions to use for scalar load8 and store8, first starting with instructions that loaded via GP registers, then remembering vpinsrb and vpextrb can take a memory argument, loading into xmm directly. I've left the first instructions I used in the file, still implemented but only used from the unit tests. They're pretty common and will probably be useful some day. Change-Id: I471b13026af4b1c6e861a53159f9df5f0285447c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227178 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-12 17:32:45 +00:00
a.vpextrb(A::rsi, A::xmm8, 7);
a.vpextrb(A::r8, A::xmm1, 15);
},{
x86, load16 Very similar to load8. The only interesting thing is how different vpinsrw is from vpinsrb (and vpinsrd and vpinsrq)... different map of instructions entirely. Change-Id: Ia413b83604dd2d277d59495c5f693f505c35be9f Reviewed-on: https://skia-review.googlesource.com/c/skia/+/232058 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-08-02 16:18:00 +00:00
0xc5,0xb9, 0xc4, 0x0e, 4,
0xc4,0x41,0x71, 0xc4, 0x00, 12,
handle x86 tail in JIT code too Basically the same deal as aarch64: - a bunch of instructions to rewrite control flow to be two loops, body and tail - a bunch of instructions to support scalar loads and stores in the tail We can now remove the JIT::mask field. I've removed the SkUNREACHABLE I'd put in for the ARM code... as written the interpreter is still reachable by the loser if two threads race to JIT the program. Medium term I plan to move JIT compilation to a more proactive time, eliminating the need for the lock and letting the interpreter become truly unreachable. I had a little bit of a false start with what instructions to use for scalar load8 and store8, first starting with instructions that loaded via GP registers, then remembering vpinsrb and vpextrb can take a memory argument, loading into xmm directly. I've left the first instructions I used in the file, still implemented but only used from the unit tests. They're pretty common and will probably be useful some day. Change-Id: I471b13026af4b1c6e861a53159f9df5f0285447c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227178 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-12 17:32:45 +00:00
0xc4,0xe3,0x39, 0x20, 0x0e, 4,
0xc4,0x43,0x71, 0x20, 0x00, 12,
x86 store16 Nothing particularly tricky. Very much like store8, but with one fewer shuffle. This lets some of the 565 blitters JIT! Change-Id: I853905bda30a0cda89f3fcb5fef1dfe62725063b Reviewed-on: https://skia-review.googlesource.com/c/skia/+/232059 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-08-02 16:43:43 +00:00
0xc4,0x63,0x79, 0x15, 0x06, 7,
0xc4,0xc3,0x79, 0x15, 0x08, 15,
handle x86 tail in JIT code too Basically the same deal as aarch64: - a bunch of instructions to rewrite control flow to be two loops, body and tail - a bunch of instructions to support scalar loads and stores in the tail We can now remove the JIT::mask field. I've removed the SkUNREACHABLE I'd put in for the ARM code... as written the interpreter is still reachable by the loser if two threads race to JIT the program. Medium term I plan to move JIT compilation to a more proactive time, eliminating the need for the lock and letting the interpreter become truly unreachable. I had a little bit of a false start with what instructions to use for scalar load8 and store8, first starting with instructions that loaded via GP registers, then remembering vpinsrb and vpextrb can take a memory argument, loading into xmm directly. I've left the first instructions I used in the file, still implemented but only used from the unit tests. They're pretty common and will probably be useful some day. Change-Id: I471b13026af4b1c6e861a53159f9df5f0285447c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227178 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-12 17:32:45 +00:00
0xc4,0x63,0x79, 0x14, 0x06, 7,
0xc4,0xc3,0x79, 0x14, 0x08, 15,
});
add bit_clear I was just reading the ARM docs and realized that their BIC ("BIt Clear") is the same as SSE's ANDN ("AND Not") instruction. It's kind of a neat little tool to have laying around... comes up more than you'd think, and it's sometimes the clearest way to express what you're doing, as in the changed program here where the comment is "mask away the low bits". That's a bit_clear with a mask for what you want to clear away! And the real reason to write this up is that I want to have a CL to point to that shows how to add an instruction top to bottom. Change-Id: I99690ed9c1009427b3986955e7ae6264de4d215c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223120 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com> Reviewed-by: Mike Reed <reed@google.com>
2019-06-24 00:35:28 +00:00
test_asm(r, [&](A& a) {
a.vpandn(A::ymm3, A::ymm12, A::ymm2);
},{
0xc5, 0x9d, 0xdf, 0xda,
});
baby steps for aarch64 support So far this is just as easy as I had hoped. Change-Id: I5f69a900b32d9bf70156b55e334233d7376b820f Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223340 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-24 22:47:16 +00:00
add vmovdqa(ymm,ymm) Fills in a little TODO. Also add assembler unit tests for similar float->int and int->float. Tested by SkVM_mad, SkVM_madder. Change-Id: I5334029927fdecb0ff7f5a3b081cf2ce7b23995c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/230838 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-30 17:15:40 +00:00
test_asm(r, [&](A& a) {
a.vmovdqa (A::ymm3, A::ymm2);
a.vcvttps2dq(A::ymm3, A::ymm2);
a.vcvtdq2ps (A::ymm3, A::ymm2);
},{
0xc5,0xfd,0x6f,0xda,
0xc5,0xfe,0x5b,0xda,
0xc5,0xfc,0x5b,0xda,
});
baby steps for aarch64 support So far this is just as easy as I had hoped. Change-Id: I5f69a900b32d9bf70156b55e334233d7376b820f Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223340 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-24 22:47:16 +00:00
// echo "fmul v4.4s, v3.4s, v1.4s" | llvm-mc -show-encoding -arch arm64
test_asm(r, [&](A& a) {
more aarch64 instructions Change-Id: Iabb9a2357b9279ab6e5a3ee899c5d029d35499e5 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223697 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-25 13:44:02 +00:00
a.and16b(A::v4, A::v3, A::v1);
a.orr16b(A::v4, A::v3, A::v1);
a.eor16b(A::v4, A::v3, A::v1);
a.bic16b(A::v4, A::v3, A::v1);
a.add4s(A::v4, A::v3, A::v1);
a.sub4s(A::v4, A::v3, A::v1);
a.mul4s(A::v4, A::v3, A::v1);
a.sub8h(A::v4, A::v3, A::v1);
a.mul8h(A::v4, A::v3, A::v1);
baby steps for aarch64 support So far this is just as easy as I had hoped. Change-Id: I5f69a900b32d9bf70156b55e334233d7376b820f Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223340 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-24 22:47:16 +00:00
a.fadd4s(A::v4, A::v3, A::v1);
a.fsub4s(A::v4, A::v3, A::v1);
a.fmul4s(A::v4, A::v3, A::v1);
a.fdiv4s(A::v4, A::v3, A::v1);
more aarch64 instructions Change-Id: Iabb9a2357b9279ab6e5a3ee899c5d029d35499e5 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223697 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-25 13:44:02 +00:00
a.fmla4s(A::v4, A::v3, A::v1);
baby steps for aarch64 support So far this is just as easy as I had hoped. Change-Id: I5f69a900b32d9bf70156b55e334233d7376b820f Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223340 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-24 22:47:16 +00:00
},{
more aarch64 instructions Change-Id: Iabb9a2357b9279ab6e5a3ee899c5d029d35499e5 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223697 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-25 13:44:02 +00:00
0x64,0x1c,0x21,0x4e,
0x64,0x1c,0xa1,0x4e,
0x64,0x1c,0x21,0x6e,
0x64,0x1c,0x61,0x4e,
0x64,0x84,0xa1,0x4e,
0x64,0x84,0xa1,0x6e,
0x64,0x9c,0xa1,0x4e,
0x64,0x84,0x61,0x6e,
0x64,0x9c,0x61,0x4e,
baby steps for aarch64 support So far this is just as easy as I had hoped. Change-Id: I5f69a900b32d9bf70156b55e334233d7376b820f Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223340 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-24 22:47:16 +00:00
0x64,0xd4,0x21,0x4e,
0x64,0xd4,0xa1,0x4e,
0x64,0xdc,0x21,0x6e,
0x64,0xfc,0x21,0x6e,
more aarch64 instructions Change-Id: Iabb9a2357b9279ab6e5a3ee899c5d029d35499e5 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223697 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-25 13:44:02 +00:00
0x64,0xcc,0x21,0x4e,
});
test_asm(r, [&](A& a) {
a.shl4s(A::v4, A::v3, 0);
a.shl4s(A::v4, A::v3, 1);
a.shl4s(A::v4, A::v3, 8);
a.shl4s(A::v4, A::v3, 16);
a.shl4s(A::v4, A::v3, 31);
a.sshr4s(A::v4, A::v3, 1);
a.sshr4s(A::v4, A::v3, 8);
a.sshr4s(A::v4, A::v3, 31);
a.ushr4s(A::v4, A::v3, 1);
a.ushr4s(A::v4, A::v3, 8);
a.ushr4s(A::v4, A::v3, 31);
a.ushr8h(A::v4, A::v3, 1);
a.ushr8h(A::v4, A::v3, 8);
a.ushr8h(A::v4, A::v3, 15);
},{
0x64,0x54,0x20,0x4f,
0x64,0x54,0x21,0x4f,
0x64,0x54,0x28,0x4f,
0x64,0x54,0x30,0x4f,
0x64,0x54,0x3f,0x4f,
0x64,0x04,0x3f,0x4f,
0x64,0x04,0x38,0x4f,
0x64,0x04,0x21,0x4f,
0x64,0x04,0x3f,0x6f,
0x64,0x04,0x38,0x6f,
0x64,0x04,0x21,0x6f,
0x64,0x04,0x1f,0x6f,
0x64,0x04,0x18,0x6f,
0x64,0x04,0x11,0x6f,
});
add sli.4s, use it in pack sometimes We have pack(x,y,imm) = x | (y<<imm) assuming (x & (y<<imm)) == 0. If we can destroy x, sli (shift-left-insert) lets us implement that as x |= y << imm. This happens quite often, so you'll see sequences of pack that used to look like this shl v4.4s, v2.4s, #8 orr v1.16b, v4.16b, v1.16b shl v2.4s, v0.4s, #8 orr v0.16b, v2.16b, v3.16b shl v2.4s, v0.4s, #16 orr v0.16b, v2.16b, v1.16b now look like this sli v1.4s, v2.4s, #8 sli v3.4s, v0.4s, #8 sli v1.4s, v3.4s, #16 We can do this thanks to the new simultaneous register assignment and instruction selection I added. We used to never hit this case. Change-Id: I75fa3defc1afd38779b3993887ca302a0885c5b1 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/228611 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-19 17:21:19 +00:00
test_asm(r, [&](A& a) {
a.sli4s(A::v4, A::v3, 0);
a.sli4s(A::v4, A::v3, 1);
a.sli4s(A::v4, A::v3, 8);
a.sli4s(A::v4, A::v3, 16);
a.sli4s(A::v4, A::v3, 31);
},{
0x64,0x54,0x20,0x6f,
0x64,0x54,0x21,0x6f,
0x64,0x54,0x28,0x6f,
0x64,0x54,0x30,0x6f,
0x64,0x54,0x3f,0x6f,
});
more aarch64 instructions Change-Id: Iabb9a2357b9279ab6e5a3ee899c5d029d35499e5 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223697 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-25 13:44:02 +00:00
test_asm(r, [&](A& a) {
a.scvtf4s (A::v4, A::v3);
a.fcvtzs4s(A::v4, A::v3);
},{
0x64,0xd8,0x21,0x4e,
0x64,0xb8,0xa1,0x4e,
baby steps for aarch64 support So far this is just as easy as I had hoped. Change-Id: I5f69a900b32d9bf70156b55e334233d7376b820f Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223340 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-24 22:47:16 +00:00
});
some scalar ops Change-Id: I1603f89603755914ed91645a2e5eeb9c87f63bbe Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223929 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-26 14:21:12 +00:00
test_asm(r, [&](A& a) {
a.ret(A::x30); // Conventional ret using link register.
a.ret(A::x13); // Can really return using any register if we like.
a.add(A::x2, A::x2, 4);
a.add(A::x3, A::x2, 32);
instructions for JIT tail support on ARM This adds a bunch of instructions we'll need to handle the N < 4 tail within the JIT code on ARM. - ldrb/strb are 1-byte load and stores - sub subtracts without setting flags - cmp just sets flags (actually just subs with an xzr destination) - add b and b.lt, just like b.ne - cbz and cbnz... we only need cbz but I accidentally did cbnz first Once I add support for forward jumps, we'll be able to use these instructions to restructure the loop to entry: hoisted setup loop: if N < 4, jump tail (cmp N,#4; b.lt tail) ... handle 4 values ... jump loop (b loop) tail: if N == 0, jump end (cbz N, end) ... handle 1 value ... jump tail (b tail) end: ret Change-Id: I62d2d190f670f758197a25d99dfde13362189993 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/226828 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-11 16:25:37 +00:00
a.sub(A::x2, A::x2, 4);
a.sub(A::x3, A::x2, 32);
some scalar ops Change-Id: I1603f89603755914ed91645a2e5eeb9c87f63bbe Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223929 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-26 14:21:12 +00:00
a.subs(A::x2, A::x2, 4);
a.subs(A::x3, A::x2, 32);
instructions for JIT tail support on ARM This adds a bunch of instructions we'll need to handle the N < 4 tail within the JIT code on ARM. - ldrb/strb are 1-byte load and stores - sub subtracts without setting flags - cmp just sets flags (actually just subs with an xzr destination) - add b and b.lt, just like b.ne - cbz and cbnz... we only need cbz but I accidentally did cbnz first Once I add support for forward jumps, we'll be able to use these instructions to restructure the loop to entry: hoisted setup loop: if N < 4, jump tail (cmp N,#4; b.lt tail) ... handle 4 values ... jump loop (b loop) tail: if N == 0, jump end (cbz N, end) ... handle 1 value ... jump tail (b tail) end: ret Change-Id: I62d2d190f670f758197a25d99dfde13362189993 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/226828 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-11 16:25:37 +00:00
a.subs(A::xzr, A::x2, 4); // These are actually the same instruction!
a.cmp(A::x2, 4);
some scalar ops Change-Id: I1603f89603755914ed91645a2e5eeb9c87f63bbe Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223929 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-26 14:21:12 +00:00
A::Label l = a.here();
make all instructions take two-way labels This turned out to be quite an easy transformation with yesterday's work already done. No codegen changes. Change-Id: Ife19ab7731514c54cfed963a6d2e9b1ec2246997 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/227137 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-12 14:22:21 +00:00
a.bne(&l);
a.bne(&l);
a.blt(&l);
a.b(&l);
a.cbnz(A::x2, &l);
bidirectional Labels Support forward references in Label. In addition to tracking the current Label offset (used for backward references essentially just the same as before this CL) we also store a list of instructions that refer to each Label. When a Label moves, each instruction gets a new displacement. To make this a little easier, remove the 8-bit jump form on x86... this way all x86 displacements are 32-bit and and all ARM 19-bit. For now only cbz() supports this, just to start somewhere. More to do but it's worth an early design review. Change-Id: I23d2bcd7742965ab694ae4828f53409cb9fc807f Reviewed-on: https://skia-review.googlesource.com/c/skia/+/226937 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-11 19:06:40 +00:00
a.cbz(A::x2, &l);
some scalar ops Change-Id: I1603f89603755914ed91645a2e5eeb9c87f63bbe Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223929 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-26 14:21:12 +00:00
},{
0xc0,0x03,0x5f,0xd6,
0xa0,0x01,0x5f,0xd6,
0x42,0x10,0x00,0x91,
0x43,0x80,0x00,0x91,
instructions for JIT tail support on ARM This adds a bunch of instructions we'll need to handle the N < 4 tail within the JIT code on ARM. - ldrb/strb are 1-byte load and stores - sub subtracts without setting flags - cmp just sets flags (actually just subs with an xzr destination) - add b and b.lt, just like b.ne - cbz and cbnz... we only need cbz but I accidentally did cbnz first Once I add support for forward jumps, we'll be able to use these instructions to restructure the loop to entry: hoisted setup loop: if N < 4, jump tail (cmp N,#4; b.lt tail) ... handle 4 values ... jump loop (b loop) tail: if N == 0, jump end (cbz N, end) ... handle 1 value ... jump tail (b tail) end: ret Change-Id: I62d2d190f670f758197a25d99dfde13362189993 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/226828 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-11 16:25:37 +00:00
0x42,0x10,0x00,0xd1,
0x43,0x80,0x00,0xd1,
some scalar ops Change-Id: I1603f89603755914ed91645a2e5eeb9c87f63bbe Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223929 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-26 14:21:12 +00:00
0x42,0x10,0x00,0xf1,
0x43,0x80,0x00,0xf1,
instructions for JIT tail support on ARM This adds a bunch of instructions we'll need to handle the N < 4 tail within the JIT code on ARM. - ldrb/strb are 1-byte load and stores - sub subtracts without setting flags - cmp just sets flags (actually just subs with an xzr destination) - add b and b.lt, just like b.ne - cbz and cbnz... we only need cbz but I accidentally did cbnz first Once I add support for forward jumps, we'll be able to use these instructions to restructure the loop to entry: hoisted setup loop: if N < 4, jump tail (cmp N,#4; b.lt tail) ... handle 4 values ... jump loop (b loop) tail: if N == 0, jump end (cbz N, end) ... handle 1 value ... jump tail (b tail) end: ret Change-Id: I62d2d190f670f758197a25d99dfde13362189993 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/226828 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-11 16:25:37 +00:00
0x5f,0x10,0x00,0xf1,
0x5f,0x10,0x00,0xf1,
0x01,0x00,0x00,0x54, // b.ne #0
0xe1,0xff,0xff,0x54, // b.ne #-4
0xcb,0xff,0xff,0x54, // b.lt #-8
0xae,0xff,0xff,0x54, // b.al #-12
0x82,0xff,0xff,0xb5, // cbnz x2, #-16
0x62,0xff,0xff,0xb4, // cbz x2, #-20
some scalar ops Change-Id: I1603f89603755914ed91645a2e5eeb9c87f63bbe Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223929 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-26 14:21:12 +00:00
});
128-bit load / store Change-Id: I665f43279ac7bfd3dffbf38a10a571b959a3425c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223977 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-26 18:47:43 +00:00
bidirectional Labels Support forward references in Label. In addition to tracking the current Label offset (used for backward references essentially just the same as before this CL) we also store a list of instructions that refer to each Label. When a Label moves, each instruction gets a new displacement. To make this a little easier, remove the 8-bit jump form on x86... this way all x86 displacements are 32-bit and and all ARM 19-bit. For now only cbz() supports this, just to start somewhere. More to do but it's worth an early design review. Change-Id: I23d2bcd7742965ab694ae4828f53409cb9fc807f Reviewed-on: https://skia-review.googlesource.com/c/skia/+/226937 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-07-11 19:06:40 +00:00
// Can we cbz() to a not-yet-defined label?
test_asm(r, [&](A& a) {
A::Label l;
a.cbz(A::x2, &l);
a.add(A::x3, A::x2, 32);
a.label(&l);
a.ret(A::x30);
},{
0x42,0x00,0x00,0xb4, // cbz x2, #8
0x43,0x80,0x00,0x91, // add x3, x2, #32
0xc0,0x03,0x5f,0xd6, // ret
});
// If we start a label as a backward label,
// can we redefine it to be a future label?
// (Not sure this is useful... just want to test it works.)
test_asm(r, [&](A& a) {
A::Label l1 = a.here();
a.add(A::x3, A::x2, 32);
a.cbz(A::x2, &l1); // This will jump backward... nothing sneaky.
A::Label l2 = a.here(); // Start off the same...
a.add(A::x3, A::x2, 32);
a.cbz(A::x2, &l2); // Looks like this will go backward...
a.add(A::x2, A::x2, 4);
a.add(A::x3, A::x2, 32);
a.label(&l2); // But no... actually forward! What a switcheroo!
},{
0x43,0x80,0x00,0x91, // add x3, x2, #32
0xe2,0xff,0xff,0xb4, // cbz x2, #-4
0x43,0x80,0x00,0x91, // add x3, x2, #32
0x62,0x00,0x00,0xb4, // cbz x2, #12
0x42,0x10,0x00,0x91, // add x2, x2, #4
0x43,0x80,0x00,0x91, // add x3, x2, #32
});
more unit tests Backfill tests for some uncovered operations. Mostly functional tests, with some targeted at particular corners of code generation, and a few assembler unit tests. This doesn't get up to 100% line coverage, but I think it covers all the non-failure cases. Change-Id: Ib701df0c505aa41e3b2fe3cd429447acb294b752 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/230837 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-30 16:11:09 +00:00
// Loading from a label on ARM.
test_asm(r, [&](A& a) {
A::Label fore,aft;
a.label(&fore);
a.word(0x01234567);
a.ldrq(A::v1, &fore);
a.ldrq(A::v2, &aft);
a.label(&aft);
a.word(0x76543210);
},{
0x67,0x45,0x23,0x01,
0xe1,0xff,0xff,0x9c, // ldr q1, #-4
0x22,0x00,0x00,0x9c, // ldr q2, #4
0x10,0x32,0x54,0x76,
});
128-bit load / store Change-Id: I665f43279ac7bfd3dffbf38a10a571b959a3425c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223977 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-26 18:47:43 +00:00
test_asm(r, [&](A& a) {
a.ldrq(A::v0, A::x8);
a.strq(A::v0, A::x8);
},{
instructions for JIT tail support on ARM This adds a bunch of instructions we'll need to handle the N < 4 tail within the JIT code on ARM. - ldrb/strb are 1-byte load and stores - sub subtracts without setting flags - cmp just sets flags (actually just subs with an xzr destination) - add b and b.lt, just like b.ne - cbz and cbnz... we only need cbz but I accidentally did cbnz first Once I add support for forward jumps, we'll be able to use these instructions to restructure the loop to entry: hoisted setup loop: if N < 4, jump tail (cmp N,#4; b.lt tail) ... handle 4 values ... jump loop (b loop) tail: if N == 0, jump end (cbz N, end) ... handle 1 value ... jump tail (b tail) end: ret Change-Id: I62d2d190f670f758197a25d99dfde13362189993 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/226828 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-11 16:25:37 +00:00
0x00,0x01,0xc0,0x3d,
0x00,0x01,0x80,0x3d,
128-bit load / store Change-Id: I665f43279ac7bfd3dffbf38a10a571b959a3425c Reviewed-on: https://skia-review.googlesource.com/c/skia/+/223977 Commit-Queue: Mike Klein <mtklein@google.com> Reviewed-by: Herb Derby <herb@google.com>
2019-06-26 18:47:43 +00:00
});
finish up arm64 ops Some small refactoring to common up redundant opcode building. Oddly, I think I've got better codegen than what Clang would do here. Clang doesn't generate uxtl-based code to unpack 8-bit to 32-bit, instead preferring to load each byte one at a time and insert them one at a time. Me: ldr s0, [x0] uxtl v0.8h, v0.8b uxtl v0.4s, v0.8h Clang: ldrb w8, [x0] ldrb w9, [x0, #1] ldrb w10, [x0, #2] ldrb w11, [x0, #3] fmov s0, w8 mov v0.s[1], w9 mov v0.s[2], w10 mov v0.s[3], w11 Change-Id: I0fdf5c6cdcde6a4eb9290936284fd3ffcb2159f6 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/224821 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-01 16:18:08 +00:00
test_asm(r, [&](A& a) {
a.xtns2h(A::v0, A::v0);
a.xtnh2b(A::v0, A::v0);
a.strs (A::v0, A::x0);
a.ldrs (A::v0, A::x0);
a.uxtlb2h(A::v0, A::v0);
a.uxtlh2s(A::v0, A::v0);
},{
0x00,0x28,0x61,0x0e,
0x00,0x28,0x21,0x0e,
0x00,0x00,0x00,0xbd,
0x00,0x00,0x40,0xbd,
0x00,0xa4,0x08,0x2f,
0x00,0xa4,0x10,0x2f,
});
instructions for JIT tail support on ARM This adds a bunch of instructions we'll need to handle the N < 4 tail within the JIT code on ARM. - ldrb/strb are 1-byte load and stores - sub subtracts without setting flags - cmp just sets flags (actually just subs with an xzr destination) - add b and b.lt, just like b.ne - cbz and cbnz... we only need cbz but I accidentally did cbnz first Once I add support for forward jumps, we'll be able to use these instructions to restructure the loop to entry: hoisted setup loop: if N < 4, jump tail (cmp N,#4; b.lt tail) ... handle 4 values ... jump loop (b loop) tail: if N == 0, jump end (cbz N, end) ... handle 1 value ... jump tail (b tail) end: ret Change-Id: I62d2d190f670f758197a25d99dfde13362189993 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/226828 Reviewed-by: Herb Derby <herb@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-11 16:25:37 +00:00
test_asm(r, [&](A& a) {
a.ldrb(A::v0, A::x8);
a.strb(A::v0, A::x8);
},{
0x00,0x01,0x40,0x3d,
0x00,0x01,0x00,0x3d,
});
more unit tests Backfill tests for some uncovered operations. Mostly functional tests, with some targeted at particular corners of code generation, and a few assembler unit tests. This doesn't get up to 100% line coverage, but I think it covers all the non-failure cases. Change-Id: Ib701df0c505aa41e3b2fe3cd429447acb294b752 Reviewed-on: https://skia-review.googlesource.com/c/skia/+/230837 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-07-30 16:11:09 +00:00
test_asm(r, [&](A& a) {
a.tbl(A::v0, A::v1, A::v2);
},{
0x20,0x00,0x02,0x4e,
});
Reland "extract Assembler so it can be tested" This is a reland of a224fc1105960fe955d32fad28f502148108ecc1 Changes since original: - switch fJIT_K to less error prone fJITMask - guard fJIT Assembler Program member with SKVM_JIT Not really sure why the mips64el-Debug bot's compiler is crashing; it does at least make sense to crash where it does... the file includes SkOpts.h which includes SkVM.h. If no reasonable code transformation can get it working again I'll remove the bot. The -Release version is fine, and mips64el is one of those things I'd happily flush if it blocks progress. In this end I think all this SKVM_JIT and Xbyak stuff should go away and make things simple again, hopefully too simple to crash GCC. :| Original change's description: > extract Assembler so it can be tested > > And start documenting some structs we'll need > to replace xbyak. > > Change-Id: I21c91642799a54e10af85afc8edbe12a9b4aa062 > Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221644 > Reviewed-by: Herb Derby <herb@google.com> > Commit-Queue: Mike Klein <mtklein@google.com> Cq-Include-Trybots: skia.primary:Test-Debian9-Clang-GCE-CPU-AVX2-x86_64-Release-All-SK_CPU_LIMIT_SSE2,Build-Debian9-GCC-mips64el-Debug Change-Id: I6d7c27bc758b23c164ee67067cdfacc291e289fc Reviewed-on: https://skia-review.googlesource.com/c/skia/+/221983 Reviewed-by: Mike Klein <mtklein@google.com> Commit-Queue: Mike Klein <mtklein@google.com>
2019-06-18 17:16:06 +00:00
}
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