2011-05-09 14:28:09 +00:00
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// Copyright 2011 the V8 project authors. All rights reserved.
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2010-02-04 20:36:58 +00:00
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include <stdlib.h>
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2011-03-28 13:05:36 +00:00
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#include <math.h>
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#include <limits.h>
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2010-02-04 20:36:58 +00:00
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#include <cstdarg>
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#include "v8.h"
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2010-05-17 15:41:35 +00:00
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#if defined(V8_TARGET_ARCH_MIPS)
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2011-09-13 12:12:25 +00:00
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#include "cpu.h"
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2010-02-04 20:36:58 +00:00
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#include "disasm.h"
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#include "assembler.h"
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2011-05-09 14:28:09 +00:00
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#include "globals.h" // Need the BitCast.
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2010-02-04 20:36:58 +00:00
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#include "mips/constants-mips.h"
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#include "mips/simulator-mips.h"
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// Only build the simulator if not compiling for real MIPS hardware.
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2011-03-28 13:05:36 +00:00
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#if defined(USE_SIMULATOR)
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2010-02-04 20:36:58 +00:00
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2011-03-28 13:05:36 +00:00
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namespace v8 {
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namespace internal {
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2010-02-04 20:36:58 +00:00
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2011-05-09 14:28:09 +00:00
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// Utils functions.
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2010-02-04 20:36:58 +00:00
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bool HaveSameSign(int32_t a, int32_t b) {
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2011-03-28 13:05:36 +00:00
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return ((a ^ b) >= 0);
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}
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uint32_t get_fcsr_condition_bit(uint32_t cc) {
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if (cc == 0) {
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return 23;
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} else {
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return 24 + cc;
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}
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2010-02-04 20:36:58 +00:00
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}
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// This macro provides a platform independent use of sscanf. The reason for
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// SScanF not being implemented in a platform independent was through
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// ::v8::internal::OS in the same way as SNPrintF is that the Windows C Run-Time
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// Library does not provide vsscanf.
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#define SScanF sscanf // NOLINT
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2011-03-28 13:05:36 +00:00
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// The MipsDebugger class is used by the simulator while debugging simulated
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2010-02-04 20:36:58 +00:00
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// code.
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2011-03-28 13:05:36 +00:00
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class MipsDebugger {
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public:
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2011-11-10 08:01:23 +00:00
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explicit MipsDebugger(Simulator* sim) : sim_(sim) { }
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2011-03-28 13:05:36 +00:00
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~MipsDebugger();
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2010-02-04 20:36:58 +00:00
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void Stop(Instruction* instr);
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void Debug();
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2011-03-28 13:05:36 +00:00
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// Print all registers with a nice formatting.
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void PrintAllRegs();
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void PrintAllRegsIncludingFPU();
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2010-02-04 20:36:58 +00:00
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private:
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// We set the breakpoint code to 0xfffff to easily recognize it.
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static const Instr kBreakpointInstr = SPECIAL | BREAK | 0xfffff << 6;
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static const Instr kNopInstr = 0x0;
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Simulator* sim_;
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int32_t GetRegisterValue(int regnum);
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2011-03-28 13:05:36 +00:00
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int32_t GetFPURegisterValueInt(int regnum);
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int64_t GetFPURegisterValueLong(int regnum);
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float GetFPURegisterValueFloat(int regnum);
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double GetFPURegisterValueDouble(int regnum);
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2010-02-04 20:36:58 +00:00
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bool GetValue(const char* desc, int32_t* value);
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// Set or delete a breakpoint. Returns true if successful.
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bool SetBreakpoint(Instruction* breakpc);
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bool DeleteBreakpoint(Instruction* breakpc);
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// Undo and redo all breakpoints. This is needed to bracket disassembly and
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// execution to skip past breakpoints when run from the debugger.
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void UndoBreakpoints();
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void RedoBreakpoints();
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};
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2011-03-28 13:05:36 +00:00
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MipsDebugger::~MipsDebugger() {
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2010-02-04 20:36:58 +00:00
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}
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2011-03-28 13:05:36 +00:00
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2010-02-04 20:36:58 +00:00
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#ifdef GENERATED_CODE_COVERAGE
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static FILE* coverage_log = NULL;
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static void InitializeCoverage() {
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char* file_name = getenv("V8_GENERATED_CODE_COVERAGE_LOG");
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if (file_name != NULL) {
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coverage_log = fopen(file_name, "aw+");
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}
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}
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2011-03-28 13:05:36 +00:00
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void MipsDebugger::Stop(Instruction* instr) {
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2011-05-26 07:46:18 +00:00
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// Get the stop code.
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uint32_t code = instr->Bits(25, 6);
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// Retrieve the encoded address, which comes just after this stop.
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char** msg_address =
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reinterpret_cast<char**>(sim_->get_pc() + Instr::kInstrSize);
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char* msg = *msg_address;
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ASSERT(msg != NULL);
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// Update this stop description.
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2013-04-02 12:36:16 +00:00
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if (!watched_stops_[code].desc) {
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watched_stops_[code].desc = msg;
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2011-05-26 07:46:18 +00:00
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}
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if (strlen(msg) > 0) {
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2010-02-04 20:36:58 +00:00
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if (coverage_log != NULL) {
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fprintf(coverage_log, "%s\n", str);
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fflush(coverage_log);
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}
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2011-05-26 07:46:18 +00:00
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// Overwrite the instruction and address with nops.
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instr->SetInstructionBits(kNopInstr);
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reinterpret_cast<Instr*>(msg_address)->SetInstructionBits(kNopInstr);
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2010-02-04 20:36:58 +00:00
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}
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2011-05-26 07:46:18 +00:00
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sim_->set_pc(sim_->get_pc() + 2 * Instruction::kInstructionSize);
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2010-02-04 20:36:58 +00:00
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}
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2011-03-28 13:05:36 +00:00
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2011-05-09 14:28:09 +00:00
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#else // GENERATED_CODE_COVERAGE
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2010-02-04 20:36:58 +00:00
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#define UNSUPPORTED() printf("Unsupported instruction.\n");
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static void InitializeCoverage() {}
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2011-03-28 13:05:36 +00:00
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void MipsDebugger::Stop(Instruction* instr) {
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2011-05-26 07:46:18 +00:00
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// Get the stop code.
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uint32_t code = instr->Bits(25, 6);
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// Retrieve the encoded address, which comes just after this stop.
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char* msg = *reinterpret_cast<char**>(sim_->get_pc() +
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Instruction::kInstrSize);
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// Update this stop description.
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2013-04-02 12:36:16 +00:00
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if (!sim_->watched_stops_[code].desc) {
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sim_->watched_stops_[code].desc = msg;
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2011-05-26 07:46:18 +00:00
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}
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PrintF("Simulator hit %s (%u)\n", msg, code);
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sim_->set_pc(sim_->get_pc() + 2 * Instruction::kInstrSize);
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2010-02-04 20:36:58 +00:00
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Debug();
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}
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2010-04-19 19:30:11 +00:00
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#endif // GENERATED_CODE_COVERAGE
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2010-02-04 20:36:58 +00:00
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2011-03-28 13:05:36 +00:00
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int32_t MipsDebugger::GetRegisterValue(int regnum) {
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2010-02-04 20:36:58 +00:00
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if (regnum == kNumSimuRegisters) {
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return sim_->get_pc();
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} else {
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return sim_->get_register(regnum);
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}
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}
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2011-03-28 13:05:36 +00:00
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int32_t MipsDebugger::GetFPURegisterValueInt(int regnum) {
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if (regnum == kNumFPURegisters) {
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return sim_->get_pc();
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} else {
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return sim_->get_fpu_register(regnum);
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}
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}
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int64_t MipsDebugger::GetFPURegisterValueLong(int regnum) {
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if (regnum == kNumFPURegisters) {
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return sim_->get_pc();
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} else {
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return sim_->get_fpu_register_long(regnum);
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}
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}
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float MipsDebugger::GetFPURegisterValueFloat(int regnum) {
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if (regnum == kNumFPURegisters) {
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return sim_->get_pc();
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} else {
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return sim_->get_fpu_register_float(regnum);
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}
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}
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double MipsDebugger::GetFPURegisterValueDouble(int regnum) {
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if (regnum == kNumFPURegisters) {
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return sim_->get_pc();
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} else {
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return sim_->get_fpu_register_double(regnum);
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}
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}
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bool MipsDebugger::GetValue(const char* desc, int32_t* value) {
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int regnum = Registers::Number(desc);
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2011-03-28 13:05:36 +00:00
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int fpuregnum = FPURegisters::Number(desc);
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2010-02-04 20:36:58 +00:00
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if (regnum != kInvalidRegister) {
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*value = GetRegisterValue(regnum);
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return true;
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2011-03-28 13:05:36 +00:00
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} else if (fpuregnum != kInvalidFPURegister) {
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*value = GetFPURegisterValueInt(fpuregnum);
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return true;
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} else if (strncmp(desc, "0x", 2) == 0) {
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return SScanF(desc, "%x", reinterpret_cast<uint32_t*>(value)) == 1;
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2010-02-04 20:36:58 +00:00
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} else {
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return SScanF(desc, "%i", value) == 1;
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}
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return false;
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}
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2011-03-28 13:05:36 +00:00
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bool MipsDebugger::SetBreakpoint(Instruction* breakpc) {
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2010-02-04 20:36:58 +00:00
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// Check if a breakpoint can be set. If not return without any side-effects.
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if (sim_->break_pc_ != NULL) {
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return false;
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}
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// Set the breakpoint.
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sim_->break_pc_ = breakpc;
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sim_->break_instr_ = breakpc->InstructionBits();
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// Not setting the breakpoint instruction in the code itself. It will be set
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// when the debugger shell continues.
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return true;
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}
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2011-03-28 13:05:36 +00:00
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bool MipsDebugger::DeleteBreakpoint(Instruction* breakpc) {
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2010-02-04 20:36:58 +00:00
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if (sim_->break_pc_ != NULL) {
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sim_->break_pc_->SetInstructionBits(sim_->break_instr_);
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}
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sim_->break_pc_ = NULL;
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sim_->break_instr_ = 0;
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return true;
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}
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2011-03-28 13:05:36 +00:00
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void MipsDebugger::UndoBreakpoints() {
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2010-02-04 20:36:58 +00:00
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if (sim_->break_pc_ != NULL) {
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sim_->break_pc_->SetInstructionBits(sim_->break_instr_);
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}
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}
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2011-03-28 13:05:36 +00:00
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void MipsDebugger::RedoBreakpoints() {
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2010-02-04 20:36:58 +00:00
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if (sim_->break_pc_ != NULL) {
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sim_->break_pc_->SetInstructionBits(kBreakpointInstr);
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}
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}
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2011-03-28 13:05:36 +00:00
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void MipsDebugger::PrintAllRegs() {
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2010-02-04 20:36:58 +00:00
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#define REG_INFO(n) Registers::Name(n), GetRegisterValue(n), GetRegisterValue(n)
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PrintF("\n");
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2011-05-09 14:28:09 +00:00
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// at, v0, a0.
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2010-02-04 20:36:58 +00:00
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PrintF("%3s: 0x%08x %10d\t%3s: 0x%08x %10d\t%3s: 0x%08x %10d\n",
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REG_INFO(1), REG_INFO(2), REG_INFO(4));
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2011-05-09 14:28:09 +00:00
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// v1, a1.
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2010-02-04 20:36:58 +00:00
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PrintF("%26s\t%3s: 0x%08x %10d\t%3s: 0x%08x %10d\n",
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"", REG_INFO(3), REG_INFO(5));
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2011-05-09 14:28:09 +00:00
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// a2.
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2010-02-04 20:36:58 +00:00
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PrintF("%26s\t%26s\t%3s: 0x%08x %10d\n", "", "", REG_INFO(6));
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2011-05-09 14:28:09 +00:00
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// a3.
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2010-02-04 20:36:58 +00:00
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PrintF("%26s\t%26s\t%3s: 0x%08x %10d\n", "", "", REG_INFO(7));
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PrintF("\n");
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// t0-t7, s0-s7
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for (int i = 0; i < 8; i++) {
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PrintF("%3s: 0x%08x %10d\t%3s: 0x%08x %10d\n",
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REG_INFO(8+i), REG_INFO(16+i));
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}
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PrintF("\n");
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2011-05-09 14:28:09 +00:00
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// t8, k0, LO.
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2010-02-04 20:36:58 +00:00
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PrintF("%3s: 0x%08x %10d\t%3s: 0x%08x %10d\t%3s: 0x%08x %10d\n",
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REG_INFO(24), REG_INFO(26), REG_INFO(32));
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2011-05-09 14:28:09 +00:00
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// t9, k1, HI.
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2010-02-04 20:36:58 +00:00
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PrintF("%3s: 0x%08x %10d\t%3s: 0x%08x %10d\t%3s: 0x%08x %10d\n",
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REG_INFO(25), REG_INFO(27), REG_INFO(33));
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2011-05-09 14:28:09 +00:00
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// sp, fp, gp.
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2010-02-04 20:36:58 +00:00
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|
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PrintF("%3s: 0x%08x %10d\t%3s: 0x%08x %10d\t%3s: 0x%08x %10d\n",
|
|
|
|
REG_INFO(29), REG_INFO(30), REG_INFO(28));
|
2011-05-09 14:28:09 +00:00
|
|
|
// pc.
|
2010-02-04 20:36:58 +00:00
|
|
|
PrintF("%3s: 0x%08x %10d\t%3s: 0x%08x %10d\n",
|
|
|
|
REG_INFO(31), REG_INFO(34));
|
2011-03-28 13:05:36 +00:00
|
|
|
|
|
|
|
#undef REG_INFO
|
|
|
|
#undef FPU_REG_INFO
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void MipsDebugger::PrintAllRegsIncludingFPU() {
|
|
|
|
#define FPU_REG_INFO(n) FPURegisters::Name(n), FPURegisters::Name(n+1), \
|
|
|
|
GetFPURegisterValueInt(n+1), \
|
|
|
|
GetFPURegisterValueInt(n), \
|
|
|
|
GetFPURegisterValueDouble(n)
|
|
|
|
|
|
|
|
PrintAllRegs();
|
|
|
|
|
|
|
|
PrintF("\n\n");
|
2011-05-09 14:28:09 +00:00
|
|
|
// f0, f1, f2, ... f31.
|
2011-03-28 13:05:36 +00:00
|
|
|
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(0) );
|
|
|
|
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(2) );
|
|
|
|
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(4) );
|
|
|
|
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(6) );
|
|
|
|
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(8) );
|
|
|
|
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(10));
|
|
|
|
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(12));
|
|
|
|
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(14));
|
|
|
|
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(16));
|
|
|
|
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(18));
|
|
|
|
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(20));
|
|
|
|
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(22));
|
|
|
|
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(24));
|
|
|
|
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(26));
|
|
|
|
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(28));
|
|
|
|
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n", FPU_REG_INFO(30));
|
|
|
|
|
2010-02-04 20:36:58 +00:00
|
|
|
#undef REG_INFO
|
2011-03-28 13:05:36 +00:00
|
|
|
#undef FPU_REG_INFO
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
|
|
|
|
void MipsDebugger::Debug() {
|
2010-02-04 20:36:58 +00:00
|
|
|
intptr_t last_pc = -1;
|
|
|
|
bool done = false;
|
|
|
|
|
|
|
|
#define COMMAND_SIZE 63
|
|
|
|
#define ARG_SIZE 255
|
|
|
|
|
|
|
|
#define STR(a) #a
|
|
|
|
#define XSTR(a) STR(a)
|
|
|
|
|
|
|
|
char cmd[COMMAND_SIZE + 1];
|
|
|
|
char arg1[ARG_SIZE + 1];
|
|
|
|
char arg2[ARG_SIZE + 1];
|
2011-03-28 13:05:36 +00:00
|
|
|
char* argv[3] = { cmd, arg1, arg2 };
|
2010-02-04 20:36:58 +00:00
|
|
|
|
2011-05-09 14:28:09 +00:00
|
|
|
// Make sure to have a proper terminating character if reaching the limit.
|
2010-02-04 20:36:58 +00:00
|
|
|
cmd[COMMAND_SIZE] = 0;
|
|
|
|
arg1[ARG_SIZE] = 0;
|
|
|
|
arg2[ARG_SIZE] = 0;
|
|
|
|
|
|
|
|
// Undo all set breakpoints while running in the debugger shell. This will
|
|
|
|
// make them invisible to all commands.
|
|
|
|
UndoBreakpoints();
|
|
|
|
|
|
|
|
while (!done && (sim_->get_pc() != Simulator::end_sim_pc)) {
|
|
|
|
if (last_pc != sim_->get_pc()) {
|
|
|
|
disasm::NameConverter converter;
|
|
|
|
disasm::Disassembler dasm(converter);
|
2011-05-09 14:28:09 +00:00
|
|
|
// Use a reasonably large buffer.
|
2010-02-04 20:36:58 +00:00
|
|
|
v8::internal::EmbeddedVector<char, 256> buffer;
|
|
|
|
dasm.InstructionDecode(buffer,
|
2011-05-09 14:28:09 +00:00
|
|
|
reinterpret_cast<byte*>(sim_->get_pc()));
|
2010-02-04 20:36:58 +00:00
|
|
|
PrintF(" 0x%08x %s\n", sim_->get_pc(), buffer.start());
|
|
|
|
last_pc = sim_->get_pc();
|
|
|
|
}
|
|
|
|
char* line = ReadLine("sim> ");
|
|
|
|
if (line == NULL) {
|
|
|
|
break;
|
|
|
|
} else {
|
2011-11-10 08:01:23 +00:00
|
|
|
char* last_input = sim_->last_debugger_input();
|
|
|
|
if (strcmp(line, "\n") == 0 && last_input != NULL) {
|
|
|
|
line = last_input;
|
|
|
|
} else {
|
|
|
|
// Ownership is transferred to sim_;
|
|
|
|
sim_->set_last_debugger_input(line);
|
|
|
|
}
|
2010-02-04 20:36:58 +00:00
|
|
|
// Use sscanf to parse the individual parts of the command line. At the
|
|
|
|
// moment no command expects more than two parameters.
|
2011-03-28 13:05:36 +00:00
|
|
|
int argc = SScanF(line,
|
2010-02-04 20:36:58 +00:00
|
|
|
"%" XSTR(COMMAND_SIZE) "s "
|
|
|
|
"%" XSTR(ARG_SIZE) "s "
|
|
|
|
"%" XSTR(ARG_SIZE) "s",
|
|
|
|
cmd, arg1, arg2);
|
|
|
|
if ((strcmp(cmd, "si") == 0) || (strcmp(cmd, "stepi") == 0)) {
|
2011-03-28 13:05:36 +00:00
|
|
|
Instruction* instr = reinterpret_cast<Instruction*>(sim_->get_pc());
|
|
|
|
if (!(instr->IsTrap()) ||
|
|
|
|
instr->InstructionBits() == rtCallRedirInstr) {
|
2010-02-04 20:36:58 +00:00
|
|
|
sim_->InstructionDecode(
|
2011-03-28 13:05:36 +00:00
|
|
|
reinterpret_cast<Instruction*>(sim_->get_pc()));
|
2010-02-04 20:36:58 +00:00
|
|
|
} else {
|
|
|
|
// Allow si to jump over generated breakpoints.
|
|
|
|
PrintF("/!\\ Jumping over generated breakpoint.\n");
|
2011-03-28 13:05:36 +00:00
|
|
|
sim_->set_pc(sim_->get_pc() + Instruction::kInstrSize);
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
} else if ((strcmp(cmd, "c") == 0) || (strcmp(cmd, "cont") == 0)) {
|
|
|
|
// Execute the one instruction we broke at with breakpoints disabled.
|
|
|
|
sim_->InstructionDecode(reinterpret_cast<Instruction*>(sim_->get_pc()));
|
|
|
|
// Leave the debugger shell.
|
|
|
|
done = true;
|
|
|
|
} else if ((strcmp(cmd, "p") == 0) || (strcmp(cmd, "print") == 0)) {
|
2011-03-28 13:05:36 +00:00
|
|
|
if (argc == 2) {
|
2010-02-04 20:36:58 +00:00
|
|
|
int32_t value;
|
2011-03-28 13:05:36 +00:00
|
|
|
float fvalue;
|
2010-02-04 20:36:58 +00:00
|
|
|
if (strcmp(arg1, "all") == 0) {
|
|
|
|
PrintAllRegs();
|
2011-03-28 13:05:36 +00:00
|
|
|
} else if (strcmp(arg1, "allf") == 0) {
|
|
|
|
PrintAllRegsIncludingFPU();
|
2010-02-04 20:36:58 +00:00
|
|
|
} else {
|
2011-03-28 13:05:36 +00:00
|
|
|
int regnum = Registers::Number(arg1);
|
|
|
|
int fpuregnum = FPURegisters::Number(arg1);
|
|
|
|
|
|
|
|
if (regnum != kInvalidRegister) {
|
|
|
|
value = GetRegisterValue(regnum);
|
2010-02-04 20:36:58 +00:00
|
|
|
PrintF("%s: 0x%08x %d \n", arg1, value, value);
|
2011-03-28 13:05:36 +00:00
|
|
|
} else if (fpuregnum != kInvalidFPURegister) {
|
|
|
|
if (fpuregnum % 2 == 1) {
|
|
|
|
value = GetFPURegisterValueInt(fpuregnum);
|
|
|
|
fvalue = GetFPURegisterValueFloat(fpuregnum);
|
|
|
|
PrintF("%s: 0x%08x %11.4e\n", arg1, value, fvalue);
|
|
|
|
} else {
|
|
|
|
double dfvalue;
|
|
|
|
int32_t lvalue1 = GetFPURegisterValueInt(fpuregnum);
|
|
|
|
int32_t lvalue2 = GetFPURegisterValueInt(fpuregnum + 1);
|
|
|
|
dfvalue = GetFPURegisterValueDouble(fpuregnum);
|
|
|
|
PrintF("%3s,%3s: 0x%08x%08x %16.4e\n",
|
|
|
|
FPURegisters::Name(fpuregnum+1),
|
|
|
|
FPURegisters::Name(fpuregnum),
|
|
|
|
lvalue1,
|
|
|
|
lvalue2,
|
|
|
|
dfvalue);
|
|
|
|
}
|
2010-02-04 20:36:58 +00:00
|
|
|
} else {
|
|
|
|
PrintF("%s unrecognized\n", arg1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
2011-03-28 13:05:36 +00:00
|
|
|
if (argc == 3) {
|
|
|
|
if (strcmp(arg2, "single") == 0) {
|
|
|
|
int32_t value;
|
|
|
|
float fvalue;
|
|
|
|
int fpuregnum = FPURegisters::Number(arg1);
|
|
|
|
|
|
|
|
if (fpuregnum != kInvalidFPURegister) {
|
|
|
|
value = GetFPURegisterValueInt(fpuregnum);
|
|
|
|
fvalue = GetFPURegisterValueFloat(fpuregnum);
|
|
|
|
PrintF("%s: 0x%08x %11.4e\n", arg1, value, fvalue);
|
|
|
|
} else {
|
|
|
|
PrintF("%s unrecognized\n", arg1);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
PrintF("print <fpu register> single\n");
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
PrintF("print <register> or print <fpu register> single\n");
|
|
|
|
}
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
} else if ((strcmp(cmd, "po") == 0)
|
|
|
|
|| (strcmp(cmd, "printobject") == 0)) {
|
2011-03-28 13:05:36 +00:00
|
|
|
if (argc == 2) {
|
2010-02-04 20:36:58 +00:00
|
|
|
int32_t value;
|
|
|
|
if (GetValue(arg1, &value)) {
|
|
|
|
Object* obj = reinterpret_cast<Object*>(value);
|
|
|
|
PrintF("%s: \n", arg1);
|
|
|
|
#ifdef DEBUG
|
|
|
|
obj->PrintLn();
|
|
|
|
#else
|
|
|
|
obj->ShortPrint();
|
|
|
|
PrintF("\n");
|
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
PrintF("%s unrecognized\n", arg1);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
PrintF("printobject <value>\n");
|
|
|
|
}
|
2011-03-28 13:05:36 +00:00
|
|
|
} else if (strcmp(cmd, "stack") == 0 || strcmp(cmd, "mem") == 0) {
|
|
|
|
int32_t* cur = NULL;
|
|
|
|
int32_t* end = NULL;
|
|
|
|
int next_arg = 1;
|
|
|
|
|
|
|
|
if (strcmp(cmd, "stack") == 0) {
|
|
|
|
cur = reinterpret_cast<int32_t*>(sim_->get_register(Simulator::sp));
|
2011-05-09 14:28:09 +00:00
|
|
|
} else { // Command "mem".
|
2011-03-28 13:05:36 +00:00
|
|
|
int32_t value;
|
|
|
|
if (!GetValue(arg1, &value)) {
|
|
|
|
PrintF("%s unrecognized\n", arg1);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
cur = reinterpret_cast<int32_t*>(value);
|
|
|
|
next_arg++;
|
|
|
|
}
|
|
|
|
|
|
|
|
int32_t words;
|
|
|
|
if (argc == next_arg) {
|
|
|
|
words = 10;
|
2013-03-30 15:54:12 +00:00
|
|
|
} else {
|
2011-03-28 13:05:36 +00:00
|
|
|
if (!GetValue(argv[next_arg], &words)) {
|
|
|
|
words = 10;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
end = cur + words;
|
|
|
|
|
|
|
|
while (cur < end) {
|
2011-05-24 07:23:32 +00:00
|
|
|
PrintF(" 0x%08x: 0x%08x %10d",
|
2011-03-28 13:05:36 +00:00
|
|
|
reinterpret_cast<intptr_t>(cur), *cur, *cur);
|
2011-05-24 07:23:32 +00:00
|
|
|
HeapObject* obj = reinterpret_cast<HeapObject*>(*cur);
|
|
|
|
int value = *cur;
|
|
|
|
Heap* current_heap = v8::internal::Isolate::Current()->heap();
|
|
|
|
if (current_heap->Contains(obj) || ((value & 1) == 0)) {
|
|
|
|
PrintF(" (");
|
|
|
|
if ((value & 1) == 0) {
|
|
|
|
PrintF("smi %d", value / 2);
|
|
|
|
} else {
|
|
|
|
obj->ShortPrint();
|
|
|
|
}
|
|
|
|
PrintF(")");
|
|
|
|
}
|
|
|
|
PrintF("\n");
|
2011-03-28 13:05:36 +00:00
|
|
|
cur++;
|
|
|
|
}
|
|
|
|
|
2011-05-24 07:23:32 +00:00
|
|
|
} else if ((strcmp(cmd, "disasm") == 0) ||
|
|
|
|
(strcmp(cmd, "dpc") == 0) ||
|
|
|
|
(strcmp(cmd, "di") == 0)) {
|
2010-02-04 20:36:58 +00:00
|
|
|
disasm::NameConverter converter;
|
|
|
|
disasm::Disassembler dasm(converter);
|
2011-05-09 14:28:09 +00:00
|
|
|
// Use a reasonably large buffer.
|
2010-02-04 20:36:58 +00:00
|
|
|
v8::internal::EmbeddedVector<char, 256> buffer;
|
|
|
|
|
2011-05-09 14:28:09 +00:00
|
|
|
byte* cur = NULL;
|
|
|
|
byte* end = NULL;
|
2010-02-04 20:36:58 +00:00
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
if (argc == 1) {
|
2011-05-09 14:28:09 +00:00
|
|
|
cur = reinterpret_cast<byte*>(sim_->get_pc());
|
2011-03-28 13:05:36 +00:00
|
|
|
end = cur + (10 * Instruction::kInstrSize);
|
|
|
|
} else if (argc == 2) {
|
2011-05-24 07:23:32 +00:00
|
|
|
int regnum = Registers::Number(arg1);
|
|
|
|
if (regnum != kInvalidRegister || strncmp(arg1, "0x", 2) == 0) {
|
|
|
|
// The argument is an address or a register name.
|
|
|
|
int32_t value;
|
|
|
|
if (GetValue(arg1, &value)) {
|
|
|
|
cur = reinterpret_cast<byte*>(value);
|
|
|
|
// Disassemble 10 instructions at <arg1>.
|
|
|
|
end = cur + (10 * Instruction::kInstrSize);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// The argument is the number of instructions.
|
|
|
|
int32_t value;
|
|
|
|
if (GetValue(arg1, &value)) {
|
|
|
|
cur = reinterpret_cast<byte*>(sim_->get_pc());
|
|
|
|
// Disassemble <arg1> instructions.
|
|
|
|
end = cur + (value * Instruction::kInstrSize);
|
|
|
|
}
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
int32_t value1;
|
|
|
|
int32_t value2;
|
|
|
|
if (GetValue(arg1, &value1) && GetValue(arg2, &value2)) {
|
2011-05-09 14:28:09 +00:00
|
|
|
cur = reinterpret_cast<byte*>(value1);
|
2011-03-28 13:05:36 +00:00
|
|
|
end = cur + (value2 * Instruction::kInstrSize);
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
while (cur < end) {
|
|
|
|
dasm.InstructionDecode(buffer, cur);
|
2011-03-28 13:05:36 +00:00
|
|
|
PrintF(" 0x%08x %s\n",
|
|
|
|
reinterpret_cast<intptr_t>(cur), buffer.start());
|
|
|
|
cur += Instruction::kInstrSize;
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
} else if (strcmp(cmd, "gdb") == 0) {
|
|
|
|
PrintF("relinquishing control to gdb\n");
|
|
|
|
v8::internal::OS::DebugBreak();
|
|
|
|
PrintF("regaining control from gdb\n");
|
|
|
|
} else if (strcmp(cmd, "break") == 0) {
|
2011-03-28 13:05:36 +00:00
|
|
|
if (argc == 2) {
|
2010-02-04 20:36:58 +00:00
|
|
|
int32_t value;
|
|
|
|
if (GetValue(arg1, &value)) {
|
|
|
|
if (!SetBreakpoint(reinterpret_cast<Instruction*>(value))) {
|
|
|
|
PrintF("setting breakpoint failed\n");
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
PrintF("%s unrecognized\n", arg1);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
PrintF("break <address>\n");
|
|
|
|
}
|
|
|
|
} else if (strcmp(cmd, "del") == 0) {
|
|
|
|
if (!DeleteBreakpoint(NULL)) {
|
|
|
|
PrintF("deleting breakpoint failed\n");
|
|
|
|
}
|
|
|
|
} else if (strcmp(cmd, "flags") == 0) {
|
|
|
|
PrintF("No flags on MIPS !\n");
|
2011-05-26 07:46:18 +00:00
|
|
|
} else if (strcmp(cmd, "stop") == 0) {
|
|
|
|
int32_t value;
|
|
|
|
intptr_t stop_pc = sim_->get_pc() -
|
|
|
|
2 * Instruction::kInstrSize;
|
|
|
|
Instruction* stop_instr = reinterpret_cast<Instruction*>(stop_pc);
|
|
|
|
Instruction* msg_address =
|
|
|
|
reinterpret_cast<Instruction*>(stop_pc +
|
|
|
|
Instruction::kInstrSize);
|
|
|
|
if ((argc == 2) && (strcmp(arg1, "unstop") == 0)) {
|
|
|
|
// Remove the current stop.
|
|
|
|
if (sim_->IsStopInstruction(stop_instr)) {
|
|
|
|
stop_instr->SetInstructionBits(kNopInstr);
|
|
|
|
msg_address->SetInstructionBits(kNopInstr);
|
|
|
|
} else {
|
|
|
|
PrintF("Not at debugger stop.\n");
|
|
|
|
}
|
|
|
|
} else if (argc == 3) {
|
|
|
|
// Print information about all/the specified breakpoint(s).
|
|
|
|
if (strcmp(arg1, "info") == 0) {
|
|
|
|
if (strcmp(arg2, "all") == 0) {
|
|
|
|
PrintF("Stop information:\n");
|
|
|
|
for (uint32_t i = kMaxWatchpointCode + 1;
|
|
|
|
i <= kMaxStopCode;
|
|
|
|
i++) {
|
|
|
|
sim_->PrintStopInfo(i);
|
|
|
|
}
|
|
|
|
} else if (GetValue(arg2, &value)) {
|
|
|
|
sim_->PrintStopInfo(value);
|
|
|
|
} else {
|
|
|
|
PrintF("Unrecognized argument.\n");
|
|
|
|
}
|
|
|
|
} else if (strcmp(arg1, "enable") == 0) {
|
|
|
|
// Enable all/the specified breakpoint(s).
|
|
|
|
if (strcmp(arg2, "all") == 0) {
|
|
|
|
for (uint32_t i = kMaxWatchpointCode + 1;
|
|
|
|
i <= kMaxStopCode;
|
|
|
|
i++) {
|
|
|
|
sim_->EnableStop(i);
|
|
|
|
}
|
|
|
|
} else if (GetValue(arg2, &value)) {
|
|
|
|
sim_->EnableStop(value);
|
|
|
|
} else {
|
|
|
|
PrintF("Unrecognized argument.\n");
|
|
|
|
}
|
|
|
|
} else if (strcmp(arg1, "disable") == 0) {
|
|
|
|
// Disable all/the specified breakpoint(s).
|
|
|
|
if (strcmp(arg2, "all") == 0) {
|
|
|
|
for (uint32_t i = kMaxWatchpointCode + 1;
|
|
|
|
i <= kMaxStopCode;
|
|
|
|
i++) {
|
|
|
|
sim_->DisableStop(i);
|
|
|
|
}
|
|
|
|
} else if (GetValue(arg2, &value)) {
|
|
|
|
sim_->DisableStop(value);
|
|
|
|
} else {
|
|
|
|
PrintF("Unrecognized argument.\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
PrintF("Wrong usage. Use help command for more information.\n");
|
|
|
|
}
|
2010-02-04 20:36:58 +00:00
|
|
|
} else if ((strcmp(cmd, "stat") == 0) || (strcmp(cmd, "st") == 0)) {
|
2011-05-09 14:28:09 +00:00
|
|
|
// Print registers and disassemble.
|
2010-02-04 20:36:58 +00:00
|
|
|
PrintAllRegs();
|
|
|
|
PrintF("\n");
|
|
|
|
|
|
|
|
disasm::NameConverter converter;
|
|
|
|
disasm::Disassembler dasm(converter);
|
2011-05-09 14:28:09 +00:00
|
|
|
// Use a reasonably large buffer.
|
2010-02-04 20:36:58 +00:00
|
|
|
v8::internal::EmbeddedVector<char, 256> buffer;
|
|
|
|
|
2011-05-09 14:28:09 +00:00
|
|
|
byte* cur = NULL;
|
|
|
|
byte* end = NULL;
|
2010-02-04 20:36:58 +00:00
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
if (argc == 1) {
|
2011-05-09 14:28:09 +00:00
|
|
|
cur = reinterpret_cast<byte*>(sim_->get_pc());
|
2011-03-28 13:05:36 +00:00
|
|
|
end = cur + (10 * Instruction::kInstrSize);
|
|
|
|
} else if (argc == 2) {
|
2010-02-04 20:36:58 +00:00
|
|
|
int32_t value;
|
|
|
|
if (GetValue(arg1, &value)) {
|
2011-05-09 14:28:09 +00:00
|
|
|
cur = reinterpret_cast<byte*>(value);
|
2010-02-04 20:36:58 +00:00
|
|
|
// no length parameter passed, assume 10 instructions
|
2011-03-28 13:05:36 +00:00
|
|
|
end = cur + (10 * Instruction::kInstrSize);
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
int32_t value1;
|
|
|
|
int32_t value2;
|
|
|
|
if (GetValue(arg1, &value1) && GetValue(arg2, &value2)) {
|
2011-05-09 14:28:09 +00:00
|
|
|
cur = reinterpret_cast<byte*>(value1);
|
2011-03-28 13:05:36 +00:00
|
|
|
end = cur + (value2 * Instruction::kInstrSize);
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
while (cur < end) {
|
|
|
|
dasm.InstructionDecode(buffer, cur);
|
2011-03-28 13:05:36 +00:00
|
|
|
PrintF(" 0x%08x %s\n",
|
|
|
|
reinterpret_cast<intptr_t>(cur), buffer.start());
|
|
|
|
cur += Instruction::kInstrSize;
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
} else if ((strcmp(cmd, "h") == 0) || (strcmp(cmd, "help") == 0)) {
|
|
|
|
PrintF("cont\n");
|
|
|
|
PrintF(" continue execution (alias 'c')\n");
|
|
|
|
PrintF("stepi\n");
|
|
|
|
PrintF(" step one instruction (alias 'si')\n");
|
|
|
|
PrintF("print <register>\n");
|
|
|
|
PrintF(" print register content (alias 'p')\n");
|
|
|
|
PrintF(" use register name 'all' to print all registers\n");
|
|
|
|
PrintF("printobject <register>\n");
|
|
|
|
PrintF(" print an object from a register (alias 'po')\n");
|
2011-03-28 13:05:36 +00:00
|
|
|
PrintF("stack [<words>]\n");
|
|
|
|
PrintF(" dump stack content, default dump 10 words)\n");
|
|
|
|
PrintF("mem <address> [<words>]\n");
|
|
|
|
PrintF(" dump memory content, default dump 10 words)\n");
|
2010-02-04 20:36:58 +00:00
|
|
|
PrintF("flags\n");
|
|
|
|
PrintF(" print flags\n");
|
|
|
|
PrintF("disasm [<instructions>]\n");
|
2011-05-24 07:23:32 +00:00
|
|
|
PrintF("disasm [<address/register>]\n");
|
|
|
|
PrintF("disasm [[<address/register>] <instructions>]\n");
|
|
|
|
PrintF(" disassemble code, default is 10 instructions\n");
|
|
|
|
PrintF(" from pc (alias 'di')\n");
|
2010-02-04 20:36:58 +00:00
|
|
|
PrintF("gdb\n");
|
|
|
|
PrintF(" enter gdb\n");
|
|
|
|
PrintF("break <address>\n");
|
|
|
|
PrintF(" set a break point on the address\n");
|
|
|
|
PrintF("del\n");
|
|
|
|
PrintF(" delete the breakpoint\n");
|
2011-05-26 07:46:18 +00:00
|
|
|
PrintF("stop feature:\n");
|
|
|
|
PrintF(" Description:\n");
|
|
|
|
PrintF(" Stops are debug instructions inserted by\n");
|
|
|
|
PrintF(" the Assembler::stop() function.\n");
|
|
|
|
PrintF(" When hitting a stop, the Simulator will\n");
|
|
|
|
PrintF(" stop and and give control to the Debugger.\n");
|
|
|
|
PrintF(" All stop codes are watched:\n");
|
|
|
|
PrintF(" - They can be enabled / disabled: the Simulator\n");
|
|
|
|
PrintF(" will / won't stop when hitting them.\n");
|
|
|
|
PrintF(" - The Simulator keeps track of how many times they \n");
|
|
|
|
PrintF(" are met. (See the info command.) Going over a\n");
|
|
|
|
PrintF(" disabled stop still increases its counter. \n");
|
|
|
|
PrintF(" Commands:\n");
|
|
|
|
PrintF(" stop info all/<code> : print infos about number <code>\n");
|
|
|
|
PrintF(" or all stop(s).\n");
|
|
|
|
PrintF(" stop enable/disable all/<code> : enables / disables\n");
|
|
|
|
PrintF(" all or number <code> stop(s)\n");
|
|
|
|
PrintF(" stop unstop\n");
|
|
|
|
PrintF(" ignore the stop instruction at the current location\n");
|
|
|
|
PrintF(" from now on\n");
|
2010-02-04 20:36:58 +00:00
|
|
|
} else {
|
|
|
|
PrintF("Unknown command: %s\n", cmd);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Add all the breakpoints back to stop execution and enter the debugger
|
|
|
|
// shell when hit.
|
|
|
|
RedoBreakpoints();
|
|
|
|
|
|
|
|
#undef COMMAND_SIZE
|
|
|
|
#undef ARG_SIZE
|
|
|
|
|
|
|
|
#undef STR
|
|
|
|
#undef XSTR
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
static bool ICacheMatch(void* one, void* two) {
|
|
|
|
ASSERT((reinterpret_cast<intptr_t>(one) & CachePage::kPageMask) == 0);
|
|
|
|
ASSERT((reinterpret_cast<intptr_t>(two) & CachePage::kPageMask) == 0);
|
|
|
|
return one == two;
|
|
|
|
}
|
|
|
|
|
2010-02-04 20:36:58 +00:00
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
static uint32_t ICacheHash(void* key) {
|
|
|
|
return static_cast<uint32_t>(reinterpret_cast<uintptr_t>(key)) >> 2;
|
|
|
|
}
|
2010-02-04 20:36:58 +00:00
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
|
|
|
|
static bool AllOnOnePage(uintptr_t start, int size) {
|
|
|
|
intptr_t start_page = (start & ~CachePage::kPageMask);
|
|
|
|
intptr_t end_page = ((start + size) & ~CachePage::kPageMask);
|
|
|
|
return start_page == end_page;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2011-11-10 08:01:23 +00:00
|
|
|
void Simulator::set_last_debugger_input(char* input) {
|
|
|
|
DeleteArray(last_debugger_input_);
|
|
|
|
last_debugger_input_ = input;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
void Simulator::FlushICache(v8::internal::HashMap* i_cache,
|
|
|
|
void* start_addr,
|
|
|
|
size_t size) {
|
|
|
|
intptr_t start = reinterpret_cast<intptr_t>(start_addr);
|
|
|
|
int intra_line = (start & CachePage::kLineMask);
|
|
|
|
start -= intra_line;
|
|
|
|
size += intra_line;
|
|
|
|
size = ((size - 1) | CachePage::kLineMask) + 1;
|
|
|
|
int offset = (start & CachePage::kPageMask);
|
|
|
|
while (!AllOnOnePage(start, size - 1)) {
|
|
|
|
int bytes_to_flush = CachePage::kPageSize - offset;
|
|
|
|
FlushOnePage(i_cache, start, bytes_to_flush);
|
|
|
|
start += bytes_to_flush;
|
|
|
|
size -= bytes_to_flush;
|
|
|
|
ASSERT_EQ(0, start & CachePage::kPageMask);
|
|
|
|
offset = 0;
|
|
|
|
}
|
|
|
|
if (size != 0) {
|
|
|
|
FlushOnePage(i_cache, start, size);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
CachePage* Simulator::GetCachePage(v8::internal::HashMap* i_cache, void* page) {
|
|
|
|
v8::internal::HashMap::Entry* entry = i_cache->Lookup(page,
|
2011-05-09 14:28:09 +00:00
|
|
|
ICacheHash(page),
|
|
|
|
true);
|
2011-03-28 13:05:36 +00:00
|
|
|
if (entry->value == NULL) {
|
|
|
|
CachePage* new_page = new CachePage();
|
|
|
|
entry->value = new_page;
|
|
|
|
}
|
|
|
|
return reinterpret_cast<CachePage*>(entry->value);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// Flush from start up to and not including start + size.
|
|
|
|
void Simulator::FlushOnePage(v8::internal::HashMap* i_cache,
|
|
|
|
intptr_t start,
|
|
|
|
int size) {
|
|
|
|
ASSERT(size <= CachePage::kPageSize);
|
|
|
|
ASSERT(AllOnOnePage(start, size - 1));
|
|
|
|
ASSERT((start & CachePage::kLineMask) == 0);
|
|
|
|
ASSERT((size & CachePage::kLineMask) == 0);
|
|
|
|
void* page = reinterpret_cast<void*>(start & (~CachePage::kPageMask));
|
|
|
|
int offset = (start & CachePage::kPageMask);
|
|
|
|
CachePage* cache_page = GetCachePage(i_cache, page);
|
|
|
|
char* valid_bytemap = cache_page->ValidityByte(offset);
|
|
|
|
memset(valid_bytemap, CachePage::LINE_INVALID, size >> CachePage::kLineShift);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Simulator::CheckICache(v8::internal::HashMap* i_cache,
|
|
|
|
Instruction* instr) {
|
|
|
|
intptr_t address = reinterpret_cast<intptr_t>(instr);
|
|
|
|
void* page = reinterpret_cast<void*>(address & (~CachePage::kPageMask));
|
|
|
|
void* line = reinterpret_cast<void*>(address & (~CachePage::kLineMask));
|
|
|
|
int offset = (address & CachePage::kPageMask);
|
|
|
|
CachePage* cache_page = GetCachePage(i_cache, page);
|
|
|
|
char* cache_valid_byte = cache_page->ValidityByte(offset);
|
|
|
|
bool cache_hit = (*cache_valid_byte == CachePage::LINE_VALID);
|
|
|
|
char* cached_line = cache_page->CachedData(offset & ~CachePage::kLineMask);
|
|
|
|
if (cache_hit) {
|
|
|
|
// Check that the data in memory matches the contents of the I-cache.
|
|
|
|
CHECK(memcmp(reinterpret_cast<void*>(instr),
|
|
|
|
cache_page->CachedData(offset),
|
|
|
|
Instruction::kInstrSize) == 0);
|
|
|
|
} else {
|
|
|
|
// Cache miss. Load memory into the cache.
|
2013-04-16 12:30:51 +00:00
|
|
|
OS::MemCopy(cached_line, line, CachePage::kLineLength);
|
2011-03-28 13:05:36 +00:00
|
|
|
*cache_valid_byte = CachePage::LINE_VALID;
|
|
|
|
}
|
|
|
|
}
|
2010-02-04 20:36:58 +00:00
|
|
|
|
|
|
|
|
2011-05-05 18:55:31 +00:00
|
|
|
void Simulator::Initialize(Isolate* isolate) {
|
|
|
|
if (isolate->simulator_initialized()) return;
|
|
|
|
isolate->set_simulator_initialized(true);
|
|
|
|
::v8::internal::ExternalReference::set_redirector(isolate,
|
|
|
|
&RedirectExternalReference);
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2011-05-05 18:55:31 +00:00
|
|
|
Simulator::Simulator(Isolate* isolate) : isolate_(isolate) {
|
2011-03-28 13:05:36 +00:00
|
|
|
i_cache_ = isolate_->simulator_i_cache();
|
|
|
|
if (i_cache_ == NULL) {
|
|
|
|
i_cache_ = new v8::internal::HashMap(&ICacheMatch);
|
|
|
|
isolate_->set_simulator_i_cache(i_cache_);
|
|
|
|
}
|
2011-05-05 18:55:31 +00:00
|
|
|
Initialize(isolate);
|
2012-01-13 13:09:52 +00:00
|
|
|
// Set up simulator support first. Some of this information is needed to
|
2010-02-04 20:36:58 +00:00
|
|
|
// setup the architecture state.
|
2011-03-28 13:05:36 +00:00
|
|
|
stack_ = reinterpret_cast<char*>(malloc(stack_size_));
|
2010-02-04 20:36:58 +00:00
|
|
|
pc_modified_ = false;
|
|
|
|
icount_ = 0;
|
2011-03-28 13:05:36 +00:00
|
|
|
break_count_ = 0;
|
2010-02-04 20:36:58 +00:00
|
|
|
break_pc_ = NULL;
|
|
|
|
break_instr_ = 0;
|
|
|
|
|
2012-01-13 13:09:52 +00:00
|
|
|
// Set up architecture state.
|
2010-02-04 20:36:58 +00:00
|
|
|
// All registers are initialized to zero to start with.
|
|
|
|
for (int i = 0; i < kNumSimuRegisters; i++) {
|
|
|
|
registers_[i] = 0;
|
|
|
|
}
|
2011-03-28 13:05:36 +00:00
|
|
|
for (int i = 0; i < kNumFPURegisters; i++) {
|
|
|
|
FPUregisters_[i] = 0;
|
|
|
|
}
|
|
|
|
FCSR_ = 0;
|
2010-02-04 20:36:58 +00:00
|
|
|
|
|
|
|
// The sp is initialized to point to the bottom (high address) of the
|
|
|
|
// allocated stack area. To be safe in potential stack underflows we leave
|
|
|
|
// some buffer below.
|
2011-03-28 13:05:36 +00:00
|
|
|
registers_[sp] = reinterpret_cast<int32_t>(stack_) + stack_size_ - 64;
|
2010-02-04 20:36:58 +00:00
|
|
|
// The ra and pc are initialized to a known bad value that will cause an
|
|
|
|
// access violation if the simulator ever tries to execute it.
|
|
|
|
registers_[pc] = bad_ra;
|
|
|
|
registers_[ra] = bad_ra;
|
|
|
|
InitializeCoverage();
|
2011-03-28 13:05:36 +00:00
|
|
|
for (int i = 0; i < kNumExceptions; i++) {
|
|
|
|
exceptions[i] = 0;
|
|
|
|
}
|
2011-11-10 08:01:23 +00:00
|
|
|
|
|
|
|
last_debugger_input_ = NULL;
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// When the generated code calls an external reference we need to catch that in
|
|
|
|
// the simulator. The external reference will be a function compiled for the
|
|
|
|
// host architecture. We need to call that function instead of trying to
|
|
|
|
// execute it with the simulator. We do that by redirecting the external
|
|
|
|
// reference to a swi (software-interrupt) instruction that is handled by
|
|
|
|
// the simulator. We write the original destination of the jump just at a known
|
|
|
|
// offset from the swi instruction so the simulator knows what to call.
|
|
|
|
class Redirection {
|
|
|
|
public:
|
2011-03-28 13:05:36 +00:00
|
|
|
Redirection(void* external_function, ExternalReference::Type type)
|
2010-02-04 20:36:58 +00:00
|
|
|
: external_function_(external_function),
|
|
|
|
swi_instruction_(rtCallRedirInstr),
|
2011-03-28 13:05:36 +00:00
|
|
|
type_(type),
|
|
|
|
next_(NULL) {
|
|
|
|
Isolate* isolate = Isolate::Current();
|
|
|
|
next_ = isolate->simulator_redirection();
|
|
|
|
Simulator::current(isolate)->
|
|
|
|
FlushICache(isolate->simulator_i_cache(),
|
|
|
|
reinterpret_cast<void*>(&swi_instruction_),
|
|
|
|
Instruction::kInstrSize);
|
|
|
|
isolate->set_simulator_redirection(this);
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void* address_of_swi_instruction() {
|
|
|
|
return reinterpret_cast<void*>(&swi_instruction_);
|
|
|
|
}
|
|
|
|
|
|
|
|
void* external_function() { return external_function_; }
|
2011-03-28 13:05:36 +00:00
|
|
|
ExternalReference::Type type() { return type_; }
|
2010-02-04 20:36:58 +00:00
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
static Redirection* Get(void* external_function,
|
|
|
|
ExternalReference::Type type) {
|
|
|
|
Isolate* isolate = Isolate::Current();
|
|
|
|
Redirection* current = isolate->simulator_redirection();
|
|
|
|
for (; current != NULL; current = current->next_) {
|
2010-02-04 20:36:58 +00:00
|
|
|
if (current->external_function_ == external_function) return current;
|
|
|
|
}
|
2011-03-28 13:05:36 +00:00
|
|
|
return new Redirection(external_function, type);
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static Redirection* FromSwiInstruction(Instruction* swi_instruction) {
|
|
|
|
char* addr_of_swi = reinterpret_cast<char*>(swi_instruction);
|
|
|
|
char* addr_of_redirection =
|
|
|
|
addr_of_swi - OFFSET_OF(Redirection, swi_instruction_);
|
|
|
|
return reinterpret_cast<Redirection*>(addr_of_redirection);
|
|
|
|
}
|
|
|
|
|
|
|
|
private:
|
|
|
|
void* external_function_;
|
|
|
|
uint32_t swi_instruction_;
|
2011-03-28 13:05:36 +00:00
|
|
|
ExternalReference::Type type_;
|
2010-02-04 20:36:58 +00:00
|
|
|
Redirection* next_;
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
void* Simulator::RedirectExternalReference(void* external_function,
|
2011-03-28 13:05:36 +00:00
|
|
|
ExternalReference::Type type) {
|
|
|
|
Redirection* redirection = Redirection::Get(external_function, type);
|
2010-02-04 20:36:58 +00:00
|
|
|
return redirection->address_of_swi_instruction();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// Get the active Simulator for the current thread.
|
2011-03-28 13:05:36 +00:00
|
|
|
Simulator* Simulator::current(Isolate* isolate) {
|
|
|
|
v8::internal::Isolate::PerIsolateThreadData* isolate_data =
|
2011-05-05 18:55:31 +00:00
|
|
|
isolate->FindOrAllocatePerThreadDataForThisThread();
|
|
|
|
ASSERT(isolate_data != NULL);
|
2011-03-28 13:05:36 +00:00
|
|
|
ASSERT(isolate_data != NULL);
|
|
|
|
|
|
|
|
Simulator* sim = isolate_data->simulator();
|
2010-02-04 20:36:58 +00:00
|
|
|
if (sim == NULL) {
|
2011-03-28 13:05:36 +00:00
|
|
|
// TODO(146): delete the simulator object when a thread/isolate goes away.
|
2011-05-05 18:55:31 +00:00
|
|
|
sim = new Simulator(isolate);
|
2011-03-28 13:05:36 +00:00
|
|
|
isolate_data->set_simulator(sim);
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
return sim;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// Sets the register in the architecture state. It will also deal with updating
|
|
|
|
// Simulator internal state for special registers such as PC.
|
|
|
|
void Simulator::set_register(int reg, int32_t value) {
|
|
|
|
ASSERT((reg >= 0) && (reg < kNumSimuRegisters));
|
|
|
|
if (reg == pc) {
|
|
|
|
pc_modified_ = true;
|
|
|
|
}
|
|
|
|
|
2011-05-09 14:28:09 +00:00
|
|
|
// Zero register always holds 0.
|
2010-02-04 20:36:58 +00:00
|
|
|
registers_[reg] = (reg == 0) ? 0 : value;
|
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
|
2012-11-29 09:22:08 +00:00
|
|
|
void Simulator::set_dw_register(int reg, const int* dbl) {
|
|
|
|
ASSERT((reg >= 0) && (reg < kNumSimuRegisters));
|
|
|
|
registers_[reg] = dbl[0];
|
|
|
|
registers_[reg + 1] = dbl[1];
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-02-04 20:36:58 +00:00
|
|
|
void Simulator::set_fpu_register(int fpureg, int32_t value) {
|
|
|
|
ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
|
|
|
|
FPUregisters_[fpureg] = value;
|
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
|
|
|
|
void Simulator::set_fpu_register_float(int fpureg, float value) {
|
|
|
|
ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
|
|
|
|
*BitCast<float*>(&FPUregisters_[fpureg]) = value;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-02-04 20:36:58 +00:00
|
|
|
void Simulator::set_fpu_register_double(int fpureg, double value) {
|
|
|
|
ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0));
|
2011-03-28 13:05:36 +00:00
|
|
|
*BitCast<double*>(&FPUregisters_[fpureg]) = value;
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// Get the register from the architecture state. This function does handle
|
|
|
|
// the special case of accessing the PC register.
|
|
|
|
int32_t Simulator::get_register(int reg) const {
|
|
|
|
ASSERT((reg >= 0) && (reg < kNumSimuRegisters));
|
|
|
|
if (reg == 0)
|
|
|
|
return 0;
|
|
|
|
else
|
|
|
|
return registers_[reg] + ((reg == pc) ? Instruction::kPCReadOffset : 0);
|
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
|
2012-11-29 09:22:08 +00:00
|
|
|
double Simulator::get_double_from_register_pair(int reg) {
|
|
|
|
ASSERT((reg >= 0) && (reg < kNumSimuRegisters) && ((reg % 2) == 0));
|
|
|
|
|
|
|
|
double dm_val = 0.0;
|
|
|
|
// Read the bits from the unsigned integer register_[] array
|
|
|
|
// into the double precision floating point value and return it.
|
|
|
|
char buffer[2 * sizeof(registers_[0])];
|
2013-04-16 12:30:51 +00:00
|
|
|
OS::MemCopy(buffer, ®isters_[reg], 2 * sizeof(registers_[0]));
|
|
|
|
OS::MemCopy(&dm_val, buffer, 2 * sizeof(registers_[0]));
|
2012-11-29 09:22:08 +00:00
|
|
|
return(dm_val);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-02-04 20:36:58 +00:00
|
|
|
int32_t Simulator::get_fpu_register(int fpureg) const {
|
|
|
|
ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
|
|
|
|
return FPUregisters_[fpureg];
|
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
|
|
|
|
int64_t Simulator::get_fpu_register_long(int fpureg) const {
|
|
|
|
ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0));
|
|
|
|
return *BitCast<int64_t*>(
|
|
|
|
const_cast<int32_t*>(&FPUregisters_[fpureg]));
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
float Simulator::get_fpu_register_float(int fpureg) const {
|
|
|
|
ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters));
|
|
|
|
return *BitCast<float*>(
|
|
|
|
const_cast<int32_t*>(&FPUregisters_[fpureg]));
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-02-04 20:36:58 +00:00
|
|
|
double Simulator::get_fpu_register_double(int fpureg) const {
|
|
|
|
ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0));
|
2011-03-28 13:05:36 +00:00
|
|
|
return *BitCast<double*>(const_cast<int32_t*>(&FPUregisters_[fpureg]));
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2013-04-12 02:01:52 +00:00
|
|
|
// Runtime FP routines take up to two double arguments and zero
|
|
|
|
// or one integer arguments. All are constructed here,
|
2011-05-24 07:23:32 +00:00
|
|
|
// from a0-a3 or f12 and f14.
|
2013-04-12 02:01:52 +00:00
|
|
|
void Simulator::GetFpArgs(double* x, double* y, int32_t* z) {
|
2011-05-24 07:23:32 +00:00
|
|
|
if (!IsMipsSoftFloatABI) {
|
|
|
|
*x = get_fpu_register_double(12);
|
|
|
|
*y = get_fpu_register_double(14);
|
2013-04-12 09:25:04 +00:00
|
|
|
*z = get_register(a2);
|
2011-05-24 07:23:32 +00:00
|
|
|
} else {
|
|
|
|
// We use a char buffer to get around the strict-aliasing rules which
|
|
|
|
// otherwise allow the compiler to optimize away the copy.
|
|
|
|
char buffer[sizeof(*x)];
|
|
|
|
int32_t* reg_buffer = reinterpret_cast<int32_t*>(buffer);
|
|
|
|
|
|
|
|
// Registers a0 and a1 -> x.
|
|
|
|
reg_buffer[0] = get_register(a0);
|
|
|
|
reg_buffer[1] = get_register(a1);
|
2013-04-16 12:30:51 +00:00
|
|
|
OS::MemCopy(x, buffer, sizeof(buffer));
|
2011-05-24 07:23:32 +00:00
|
|
|
// Registers a2 and a3 -> y.
|
|
|
|
reg_buffer[0] = get_register(a2);
|
|
|
|
reg_buffer[1] = get_register(a3);
|
2013-04-16 12:30:51 +00:00
|
|
|
OS::MemCopy(y, buffer, sizeof(buffer));
|
2013-04-12 02:01:52 +00:00
|
|
|
// Register 2 -> z.
|
2011-05-24 07:23:32 +00:00
|
|
|
reg_buffer[0] = get_register(a2);
|
2013-04-16 12:30:51 +00:00
|
|
|
OS::MemCopy(z, buffer, sizeof(*z));
|
2011-05-24 07:23:32 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// The return value is either in v0/v1 or f0.
|
|
|
|
void Simulator::SetFpResult(const double& result) {
|
|
|
|
if (!IsMipsSoftFloatABI) {
|
|
|
|
set_fpu_register_double(0, result);
|
|
|
|
} else {
|
|
|
|
char buffer[2 * sizeof(registers_[0])];
|
|
|
|
int32_t* reg_buffer = reinterpret_cast<int32_t*>(buffer);
|
2013-04-16 12:30:51 +00:00
|
|
|
OS::MemCopy(buffer, &result, sizeof(buffer));
|
2011-05-24 07:23:32 +00:00
|
|
|
// Copy result to v0 and v1.
|
|
|
|
set_register(v0, reg_buffer[0]);
|
|
|
|
set_register(v1, reg_buffer[1]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
// Helper functions for setting and testing the FCSR register's bits.
|
|
|
|
void Simulator::set_fcsr_bit(uint32_t cc, bool value) {
|
|
|
|
if (value) {
|
|
|
|
FCSR_ |= (1 << cc);
|
|
|
|
} else {
|
|
|
|
FCSR_ &= ~(1 << cc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
bool Simulator::test_fcsr_bit(uint32_t cc) {
|
|
|
|
return FCSR_ & (1 << cc);
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
|
|
|
|
// Sets the rounding error codes in FCSR based on the result of the rounding.
|
|
|
|
// Returns true if the operation was invalid.
|
|
|
|
bool Simulator::set_fcsr_round_error(double original, double rounded) {
|
2011-06-06 08:43:15 +00:00
|
|
|
bool ret = false;
|
|
|
|
|
|
|
|
if (!isfinite(original) || !isfinite(rounded)) {
|
|
|
|
set_fcsr_bit(kFCSRInvalidOpFlagBit, true);
|
|
|
|
ret = true;
|
2011-03-28 13:05:36 +00:00
|
|
|
}
|
2011-06-06 08:43:15 +00:00
|
|
|
|
|
|
|
if (original != rounded) {
|
|
|
|
set_fcsr_bit(kFCSRInexactFlagBit, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (rounded < DBL_MIN && rounded > -DBL_MIN && rounded != 0) {
|
|
|
|
set_fcsr_bit(kFCSRUnderflowFlagBit, true);
|
|
|
|
ret = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (rounded > INT_MAX || rounded < INT_MIN) {
|
|
|
|
set_fcsr_bit(kFCSROverflowFlagBit, true);
|
|
|
|
// The reference is not really clear but it seems this is required:
|
|
|
|
set_fcsr_bit(kFCSRInvalidOpFlagBit, true);
|
|
|
|
ret = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
2011-03-28 13:05:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-02-04 20:36:58 +00:00
|
|
|
// Raw access to the PC register.
|
|
|
|
void Simulator::set_pc(int32_t value) {
|
|
|
|
pc_modified_ = true;
|
|
|
|
registers_[pc] = value;
|
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
|
|
|
|
bool Simulator::has_bad_pc() const {
|
|
|
|
return ((registers_[pc] == bad_ra) || (registers_[pc] == end_sim_pc));
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-02-04 20:36:58 +00:00
|
|
|
// Raw access to the PC register without the special adjustment when reading.
|
|
|
|
int32_t Simulator::get_pc() const {
|
|
|
|
return registers_[pc];
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// The MIPS cannot do unaligned reads and writes. On some MIPS platforms an
|
|
|
|
// interrupt is caused. On others it does a funky rotation thing. For now we
|
|
|
|
// simply disallow unaligned reads, but at some point we may want to move to
|
|
|
|
// emulating the rotate behaviour. Note that simulator runs have the runtime
|
|
|
|
// system running directly on the host system and only generated code is
|
|
|
|
// executed in the simulator. Since the host is typically IA32 we will not
|
|
|
|
// get the correct MIPS-like behaviour on unaligned accesses.
|
|
|
|
|
|
|
|
int Simulator::ReadW(int32_t addr, Instruction* instr) {
|
2011-03-28 13:05:36 +00:00
|
|
|
if (addr >=0 && addr < 0x400) {
|
2011-05-09 14:28:09 +00:00
|
|
|
// This has to be a NULL-dereference, drop into debugger.
|
2011-09-13 12:12:25 +00:00
|
|
|
PrintF("Memory read from bad address: 0x%08x, pc=0x%08x\n",
|
|
|
|
addr, reinterpret_cast<intptr_t>(instr));
|
2011-03-28 13:05:36 +00:00
|
|
|
MipsDebugger dbg(this);
|
|
|
|
dbg.Debug();
|
|
|
|
}
|
|
|
|
if ((addr & kPointerAlignmentMask) == 0) {
|
2010-02-04 20:36:58 +00:00
|
|
|
intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
|
|
|
|
return *ptr;
|
|
|
|
}
|
2011-05-09 14:28:09 +00:00
|
|
|
PrintF("Unaligned read at 0x%08x, pc=0x%08" V8PRIxPTR "\n",
|
|
|
|
addr,
|
|
|
|
reinterpret_cast<intptr_t>(instr));
|
2011-03-28 13:05:36 +00:00
|
|
|
MipsDebugger dbg(this);
|
|
|
|
dbg.Debug();
|
2010-02-04 20:36:58 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Simulator::WriteW(int32_t addr, int value, Instruction* instr) {
|
2011-03-28 13:05:36 +00:00
|
|
|
if (addr >= 0 && addr < 0x400) {
|
2011-05-09 14:28:09 +00:00
|
|
|
// This has to be a NULL-dereference, drop into debugger.
|
2011-09-13 12:12:25 +00:00
|
|
|
PrintF("Memory write to bad address: 0x%08x, pc=0x%08x\n",
|
|
|
|
addr, reinterpret_cast<intptr_t>(instr));
|
2011-03-28 13:05:36 +00:00
|
|
|
MipsDebugger dbg(this);
|
|
|
|
dbg.Debug();
|
|
|
|
}
|
|
|
|
if ((addr & kPointerAlignmentMask) == 0) {
|
2010-02-04 20:36:58 +00:00
|
|
|
intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
|
|
|
|
*ptr = value;
|
|
|
|
return;
|
|
|
|
}
|
2011-05-09 14:28:09 +00:00
|
|
|
PrintF("Unaligned write at 0x%08x, pc=0x%08" V8PRIxPTR "\n",
|
|
|
|
addr,
|
|
|
|
reinterpret_cast<intptr_t>(instr));
|
2011-03-28 13:05:36 +00:00
|
|
|
MipsDebugger dbg(this);
|
|
|
|
dbg.Debug();
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
double Simulator::ReadD(int32_t addr, Instruction* instr) {
|
|
|
|
if ((addr & kDoubleAlignmentMask) == 0) {
|
|
|
|
double* ptr = reinterpret_cast<double*>(addr);
|
|
|
|
return *ptr;
|
|
|
|
}
|
2011-05-09 14:28:09 +00:00
|
|
|
PrintF("Unaligned (double) read at 0x%08x, pc=0x%08" V8PRIxPTR "\n",
|
|
|
|
addr,
|
|
|
|
reinterpret_cast<intptr_t>(instr));
|
2010-02-04 20:36:58 +00:00
|
|
|
OS::Abort();
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Simulator::WriteD(int32_t addr, double value, Instruction* instr) {
|
|
|
|
if ((addr & kDoubleAlignmentMask) == 0) {
|
|
|
|
double* ptr = reinterpret_cast<double*>(addr);
|
|
|
|
*ptr = value;
|
|
|
|
return;
|
|
|
|
}
|
2011-05-09 14:28:09 +00:00
|
|
|
PrintF("Unaligned (double) write at 0x%08x, pc=0x%08" V8PRIxPTR "\n",
|
|
|
|
addr,
|
|
|
|
reinterpret_cast<intptr_t>(instr));
|
2010-02-04 20:36:58 +00:00
|
|
|
OS::Abort();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
uint16_t Simulator::ReadHU(int32_t addr, Instruction* instr) {
|
|
|
|
if ((addr & 1) == 0) {
|
|
|
|
uint16_t* ptr = reinterpret_cast<uint16_t*>(addr);
|
|
|
|
return *ptr;
|
|
|
|
}
|
2011-05-09 14:28:09 +00:00
|
|
|
PrintF("Unaligned unsigned halfword read at 0x%08x, pc=0x%08" V8PRIxPTR "\n",
|
|
|
|
addr,
|
|
|
|
reinterpret_cast<intptr_t>(instr));
|
2010-02-04 20:36:58 +00:00
|
|
|
OS::Abort();
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
int16_t Simulator::ReadH(int32_t addr, Instruction* instr) {
|
|
|
|
if ((addr & 1) == 0) {
|
|
|
|
int16_t* ptr = reinterpret_cast<int16_t*>(addr);
|
|
|
|
return *ptr;
|
|
|
|
}
|
2011-05-09 14:28:09 +00:00
|
|
|
PrintF("Unaligned signed halfword read at 0x%08x, pc=0x%08" V8PRIxPTR "\n",
|
|
|
|
addr,
|
|
|
|
reinterpret_cast<intptr_t>(instr));
|
2010-02-04 20:36:58 +00:00
|
|
|
OS::Abort();
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Simulator::WriteH(int32_t addr, uint16_t value, Instruction* instr) {
|
|
|
|
if ((addr & 1) == 0) {
|
|
|
|
uint16_t* ptr = reinterpret_cast<uint16_t*>(addr);
|
|
|
|
*ptr = value;
|
|
|
|
return;
|
|
|
|
}
|
2011-05-09 14:28:09 +00:00
|
|
|
PrintF("Unaligned unsigned halfword write at 0x%08x, pc=0x%08" V8PRIxPTR "\n",
|
|
|
|
addr,
|
|
|
|
reinterpret_cast<intptr_t>(instr));
|
2010-02-04 20:36:58 +00:00
|
|
|
OS::Abort();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Simulator::WriteH(int32_t addr, int16_t value, Instruction* instr) {
|
|
|
|
if ((addr & 1) == 0) {
|
|
|
|
int16_t* ptr = reinterpret_cast<int16_t*>(addr);
|
|
|
|
*ptr = value;
|
|
|
|
return;
|
|
|
|
}
|
2011-05-09 14:28:09 +00:00
|
|
|
PrintF("Unaligned halfword write at 0x%08x, pc=0x%08" V8PRIxPTR "\n",
|
|
|
|
addr,
|
|
|
|
reinterpret_cast<intptr_t>(instr));
|
2010-02-04 20:36:58 +00:00
|
|
|
OS::Abort();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
uint32_t Simulator::ReadBU(int32_t addr) {
|
|
|
|
uint8_t* ptr = reinterpret_cast<uint8_t*>(addr);
|
|
|
|
return *ptr & 0xff;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
int32_t Simulator::ReadB(int32_t addr) {
|
|
|
|
int8_t* ptr = reinterpret_cast<int8_t*>(addr);
|
2011-03-28 13:05:36 +00:00
|
|
|
return *ptr;
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Simulator::WriteB(int32_t addr, uint8_t value) {
|
|
|
|
uint8_t* ptr = reinterpret_cast<uint8_t*>(addr);
|
|
|
|
*ptr = value;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Simulator::WriteB(int32_t addr, int8_t value) {
|
|
|
|
int8_t* ptr = reinterpret_cast<int8_t*>(addr);
|
|
|
|
*ptr = value;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// Returns the limit of the stack area to enable checking for stack overflows.
|
|
|
|
uintptr_t Simulator::StackLimit() const {
|
2012-02-16 14:16:12 +00:00
|
|
|
// Leave a safety margin of 1024 bytes to prevent overrunning the stack when
|
2010-02-04 20:36:58 +00:00
|
|
|
// pushing values.
|
2012-02-16 14:16:12 +00:00
|
|
|
return reinterpret_cast<uintptr_t>(stack_) + 1024;
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// Unsupported instructions use Format to print an error and stop execution.
|
|
|
|
void Simulator::Format(Instruction* instr, const char* format) {
|
|
|
|
PrintF("Simulator found unsupported instruction:\n 0x%08x: %s\n",
|
2011-03-28 13:05:36 +00:00
|
|
|
reinterpret_cast<intptr_t>(instr), format);
|
2010-02-04 20:36:58 +00:00
|
|
|
UNIMPLEMENTED_MIPS();
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// Calls into the V8 runtime are based on this very simple interface.
|
|
|
|
// Note: To be able to return two values from some calls the code in runtime.cc
|
|
|
|
// uses the ObjectPair which is essentially two 32-bit values stuffed into a
|
|
|
|
// 64-bit value. With the code below we assume that all runtime calls return
|
2011-03-28 13:05:36 +00:00
|
|
|
// 64 bits of result. If they don't, the v1 result register contains a bogus
|
2010-02-04 20:36:58 +00:00
|
|
|
// value, which is fine because it is caller-saved.
|
|
|
|
typedef int64_t (*SimulatorRuntimeCall)(int32_t arg0,
|
|
|
|
int32_t arg1,
|
|
|
|
int32_t arg2,
|
2011-03-28 13:05:36 +00:00
|
|
|
int32_t arg3,
|
|
|
|
int32_t arg4,
|
|
|
|
int32_t arg5);
|
2013-04-12 02:01:52 +00:00
|
|
|
|
|
|
|
// These prototypes handle the four types of FP calls.
|
|
|
|
typedef int64_t (*SimulatorRuntimeCompareCall)(double darg0, double darg1);
|
|
|
|
typedef double (*SimulatorRuntimeFPFPCall)(double darg0, double darg1);
|
|
|
|
typedef double (*SimulatorRuntimeFPCall)(double darg0);
|
|
|
|
typedef double (*SimulatorRuntimeFPIntCall)(double darg0, int32_t arg0);
|
2010-02-04 20:36:58 +00:00
|
|
|
|
2011-05-09 14:28:09 +00:00
|
|
|
// This signature supports direct call in to API function native callback
|
|
|
|
// (refer to InvocationCallback in v8.h).
|
2011-05-23 07:12:58 +00:00
|
|
|
typedef v8::Handle<v8::Value> (*SimulatorRuntimeDirectApiCall)(int32_t arg0);
|
|
|
|
|
|
|
|
// This signature supports direct call to accessor getter callback.
|
|
|
|
typedef v8::Handle<v8::Value> (*SimulatorRuntimeDirectGetterCall)(int32_t arg0,
|
|
|
|
int32_t arg1);
|
2011-05-09 14:28:09 +00:00
|
|
|
|
2010-02-04 20:36:58 +00:00
|
|
|
// Software interrupt instructions are used by the simulator to call into the
|
2011-03-28 13:05:36 +00:00
|
|
|
// C-based V8 runtime. They are also used for debugging with simulator.
|
2010-02-04 20:36:58 +00:00
|
|
|
void Simulator::SoftwareInterrupt(Instruction* instr) {
|
2011-03-28 13:05:36 +00:00
|
|
|
// There are several instructions that could get us here,
|
|
|
|
// the break_ instruction, or several variants of traps. All
|
|
|
|
// Are "SPECIAL" class opcode, and are distinuished by function.
|
|
|
|
int32_t func = instr->FunctionFieldRaw();
|
2011-05-26 07:46:18 +00:00
|
|
|
uint32_t code = (func == BREAK) ? instr->Bits(25, 6) : -1;
|
2011-03-28 13:05:36 +00:00
|
|
|
|
2010-02-04 20:36:58 +00:00
|
|
|
// We first check if we met a call_rt_redirected.
|
|
|
|
if (instr->InstructionBits() == rtCallRedirInstr) {
|
|
|
|
Redirection* redirection = Redirection::FromSwiInstruction(instr);
|
|
|
|
int32_t arg0 = get_register(a0);
|
|
|
|
int32_t arg1 = get_register(a1);
|
|
|
|
int32_t arg2 = get_register(a2);
|
|
|
|
int32_t arg3 = get_register(a3);
|
2011-03-28 13:05:36 +00:00
|
|
|
|
|
|
|
int32_t* stack_pointer = reinterpret_cast<int32_t*>(get_register(sp));
|
2011-08-29 13:29:55 +00:00
|
|
|
// Args 4 and 5 are on the stack after the reserved space for args 0..3.
|
|
|
|
int32_t arg4 = stack_pointer[4];
|
|
|
|
int32_t arg5 = stack_pointer[5];
|
2011-05-09 14:28:09 +00:00
|
|
|
|
|
|
|
bool fp_call =
|
|
|
|
(redirection->type() == ExternalReference::BUILTIN_FP_FP_CALL) ||
|
|
|
|
(redirection->type() == ExternalReference::BUILTIN_COMPARE_CALL) ||
|
|
|
|
(redirection->type() == ExternalReference::BUILTIN_FP_CALL) ||
|
|
|
|
(redirection->type() == ExternalReference::BUILTIN_FP_INT_CALL);
|
|
|
|
|
2011-05-24 07:23:32 +00:00
|
|
|
if (!IsMipsSoftFloatABI) {
|
|
|
|
// With the hard floating point calling convention, double
|
|
|
|
// arguments are passed in FPU registers. Fetch the arguments
|
|
|
|
// from there and call the builtin using soft floating point
|
|
|
|
// convention.
|
|
|
|
switch (redirection->type()) {
|
|
|
|
case ExternalReference::BUILTIN_FP_FP_CALL:
|
|
|
|
case ExternalReference::BUILTIN_COMPARE_CALL:
|
|
|
|
arg0 = get_fpu_register(f12);
|
|
|
|
arg1 = get_fpu_register(f13);
|
|
|
|
arg2 = get_fpu_register(f14);
|
|
|
|
arg3 = get_fpu_register(f15);
|
|
|
|
break;
|
|
|
|
case ExternalReference::BUILTIN_FP_CALL:
|
|
|
|
arg0 = get_fpu_register(f12);
|
|
|
|
arg1 = get_fpu_register(f13);
|
|
|
|
break;
|
|
|
|
case ExternalReference::BUILTIN_FP_INT_CALL:
|
|
|
|
arg0 = get_fpu_register(f12);
|
|
|
|
arg1 = get_fpu_register(f13);
|
|
|
|
arg2 = get_register(a2);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-02-04 20:36:58 +00:00
|
|
|
// This is dodgy but it works because the C entry stubs are never moved.
|
|
|
|
// See comment in codegen-arm.cc and bug 1242173.
|
|
|
|
int32_t saved_ra = get_register(ra);
|
2011-03-28 13:05:36 +00:00
|
|
|
|
|
|
|
intptr_t external =
|
2011-05-09 14:28:09 +00:00
|
|
|
reinterpret_cast<intptr_t>(redirection->external_function());
|
2011-03-28 13:05:36 +00:00
|
|
|
|
|
|
|
// Based on CpuFeatures::IsSupported(FPU), Mips will use either hardware
|
|
|
|
// FPU, or gcc soft-float routines. Hardware FPU is simulated in this
|
|
|
|
// simulator. Soft-float has additional abstraction of ExternalReference,
|
2011-05-24 07:23:32 +00:00
|
|
|
// to support serialization.
|
2011-05-09 14:28:09 +00:00
|
|
|
if (fp_call) {
|
2013-04-12 02:01:52 +00:00
|
|
|
double dval0, dval1; // one or two double parameters
|
|
|
|
int32_t ival; // zero or one integer parameters
|
|
|
|
int64_t iresult = 0; // integer return value
|
|
|
|
double dresult = 0; // double return value
|
|
|
|
GetFpArgs(&dval0, &dval1, &ival);
|
|
|
|
SimulatorRuntimeCall generic_target =
|
|
|
|
reinterpret_cast<SimulatorRuntimeCall>(external);
|
2011-05-09 14:28:09 +00:00
|
|
|
if (::v8::internal::FLAG_trace_sim) {
|
2011-05-24 07:23:32 +00:00
|
|
|
switch (redirection->type()) {
|
|
|
|
case ExternalReference::BUILTIN_FP_FP_CALL:
|
|
|
|
case ExternalReference::BUILTIN_COMPARE_CALL:
|
|
|
|
PrintF("Call to host function at %p with args %f, %f",
|
2013-04-12 02:01:52 +00:00
|
|
|
FUNCTION_ADDR(generic_target), dval0, dval1);
|
2011-05-24 07:23:32 +00:00
|
|
|
break;
|
|
|
|
case ExternalReference::BUILTIN_FP_CALL:
|
|
|
|
PrintF("Call to host function at %p with arg %f",
|
2013-04-12 02:01:52 +00:00
|
|
|
FUNCTION_ADDR(generic_target), dval0);
|
2011-05-24 07:23:32 +00:00
|
|
|
break;
|
|
|
|
case ExternalReference::BUILTIN_FP_INT_CALL:
|
|
|
|
PrintF("Call to host function at %p with args %f, %d",
|
2013-04-12 02:01:52 +00:00
|
|
|
FUNCTION_ADDR(generic_target), dval0, ival);
|
2011-05-24 07:23:32 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2013-04-12 02:01:52 +00:00
|
|
|
switch (redirection->type()) {
|
|
|
|
case ExternalReference::BUILTIN_COMPARE_CALL: {
|
|
|
|
SimulatorRuntimeCompareCall target =
|
|
|
|
reinterpret_cast<SimulatorRuntimeCompareCall>(external);
|
|
|
|
iresult = target(dval0, dval1);
|
|
|
|
set_register(v0, static_cast<int32_t>(iresult));
|
|
|
|
set_register(v1, static_cast<int32_t>(iresult >> 32));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ExternalReference::BUILTIN_FP_FP_CALL: {
|
|
|
|
SimulatorRuntimeFPFPCall target =
|
|
|
|
reinterpret_cast<SimulatorRuntimeFPFPCall>(external);
|
|
|
|
dresult = target(dval0, dval1);
|
|
|
|
SetFpResult(dresult);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ExternalReference::BUILTIN_FP_CALL: {
|
2012-06-04 13:56:10 +00:00
|
|
|
SimulatorRuntimeFPCall target =
|
2013-04-12 02:01:52 +00:00
|
|
|
reinterpret_cast<SimulatorRuntimeFPCall>(external);
|
|
|
|
dresult = target(dval0);
|
|
|
|
SetFpResult(dresult);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ExternalReference::BUILTIN_FP_INT_CALL: {
|
|
|
|
SimulatorRuntimeFPIntCall target =
|
|
|
|
reinterpret_cast<SimulatorRuntimeFPIntCall>(external);
|
|
|
|
dresult = target(dval0, ival);
|
|
|
|
SetFpResult(dresult);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (::v8::internal::FLAG_trace_sim) {
|
|
|
|
switch (redirection->type()) {
|
|
|
|
case ExternalReference::BUILTIN_COMPARE_CALL:
|
|
|
|
PrintF("Returned %08x\n", static_cast<int32_t>(iresult));
|
|
|
|
break;
|
|
|
|
case ExternalReference::BUILTIN_FP_FP_CALL:
|
|
|
|
case ExternalReference::BUILTIN_FP_CALL:
|
|
|
|
case ExternalReference::BUILTIN_FP_INT_CALL:
|
|
|
|
PrintF("Returned %f\n", dresult);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
break;
|
|
|
|
}
|
2011-05-24 07:23:32 +00:00
|
|
|
}
|
2011-03-28 13:05:36 +00:00
|
|
|
} else if (redirection->type() == ExternalReference::DIRECT_API_CALL) {
|
2011-05-23 07:12:58 +00:00
|
|
|
// See DirectCEntryStub::GenerateCall for explanation of register usage.
|
|
|
|
SimulatorRuntimeDirectApiCall target =
|
|
|
|
reinterpret_cast<SimulatorRuntimeDirectApiCall>(external);
|
2011-05-09 14:28:09 +00:00
|
|
|
if (::v8::internal::FLAG_trace_sim) {
|
|
|
|
PrintF("Call to host function at %p args %08x\n",
|
2011-05-23 07:12:58 +00:00
|
|
|
FUNCTION_ADDR(target), arg1);
|
|
|
|
}
|
|
|
|
v8::Handle<v8::Value> result = target(arg1);
|
2013-01-07 15:02:56 +00:00
|
|
|
*(reinterpret_cast<int*>(arg0)) = reinterpret_cast<int32_t>(*result);
|
2011-05-23 07:12:58 +00:00
|
|
|
set_register(v0, arg0);
|
|
|
|
} else if (redirection->type() == ExternalReference::DIRECT_GETTER_CALL) {
|
|
|
|
// See DirectCEntryStub::GenerateCall for explanation of register usage.
|
|
|
|
SimulatorRuntimeDirectGetterCall target =
|
|
|
|
reinterpret_cast<SimulatorRuntimeDirectGetterCall>(external);
|
|
|
|
if (::v8::internal::FLAG_trace_sim) {
|
|
|
|
PrintF("Call to host function at %p args %08x %08x\n",
|
|
|
|
FUNCTION_ADDR(target), arg1, arg2);
|
2011-05-09 14:28:09 +00:00
|
|
|
}
|
2011-05-23 07:12:58 +00:00
|
|
|
v8::Handle<v8::Value> result = target(arg1, arg2);
|
2013-01-07 15:02:56 +00:00
|
|
|
*(reinterpret_cast<int*>(arg0)) = reinterpret_cast<int32_t>(*result);
|
2011-05-23 07:12:58 +00:00
|
|
|
set_register(v0, arg0);
|
2010-02-04 20:36:58 +00:00
|
|
|
} else {
|
|
|
|
SimulatorRuntimeCall target =
|
2011-05-09 14:28:09 +00:00
|
|
|
reinterpret_cast<SimulatorRuntimeCall>(external);
|
|
|
|
if (::v8::internal::FLAG_trace_sim) {
|
2010-02-04 20:36:58 +00:00
|
|
|
PrintF(
|
2011-05-09 14:28:09 +00:00
|
|
|
"Call to host function at %p "
|
|
|
|
"args %08x, %08x, %08x, %08x, %08x, %08x\n",
|
2010-02-04 20:36:58 +00:00
|
|
|
FUNCTION_ADDR(target),
|
|
|
|
arg0,
|
|
|
|
arg1,
|
|
|
|
arg2,
|
2011-03-28 13:05:36 +00:00
|
|
|
arg3,
|
|
|
|
arg4,
|
|
|
|
arg5);
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
2011-03-28 13:05:36 +00:00
|
|
|
int64_t result = target(arg0, arg1, arg2, arg3, arg4, arg5);
|
|
|
|
set_register(v0, static_cast<int32_t>(result));
|
|
|
|
set_register(v1, static_cast<int32_t>(result >> 32));
|
|
|
|
}
|
|
|
|
if (::v8::internal::FLAG_trace_sim) {
|
|
|
|
PrintF("Returned %08x : %08x\n", get_register(v1), get_register(v0));
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
set_register(ra, saved_ra);
|
|
|
|
set_pc(get_register(ra));
|
2011-03-28 13:05:36 +00:00
|
|
|
|
2011-05-26 07:46:18 +00:00
|
|
|
} else if (func == BREAK && code <= kMaxStopCode) {
|
|
|
|
if (IsWatchpoint(code)) {
|
|
|
|
PrintWatchpoint(code);
|
|
|
|
} else {
|
|
|
|
IncreaseStopCounter(code);
|
|
|
|
HandleStop(code, instr);
|
|
|
|
}
|
2010-02-04 20:36:58 +00:00
|
|
|
} else {
|
2011-03-28 13:05:36 +00:00
|
|
|
// All remaining break_ codes, and all traps are handled here.
|
|
|
|
MipsDebugger dbg(this);
|
2010-02-04 20:36:58 +00:00
|
|
|
dbg.Debug();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
|
2011-05-26 07:46:18 +00:00
|
|
|
// Stop helper functions.
|
|
|
|
bool Simulator::IsWatchpoint(uint32_t code) {
|
|
|
|
return (code <= kMaxWatchpointCode);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Simulator::PrintWatchpoint(uint32_t code) {
|
|
|
|
MipsDebugger dbg(this);
|
|
|
|
++break_count_;
|
|
|
|
PrintF("\n---- break %d marker: %3d (instr count: %8d) ----------"
|
|
|
|
"----------------------------------",
|
|
|
|
code, break_count_, icount_);
|
|
|
|
dbg.PrintAllRegs(); // Print registers and continue running.
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Simulator::HandleStop(uint32_t code, Instruction* instr) {
|
|
|
|
// Stop if it is enabled, otherwise go on jumping over the stop
|
|
|
|
// and the message address.
|
|
|
|
if (IsEnabledStop(code)) {
|
|
|
|
MipsDebugger dbg(this);
|
|
|
|
dbg.Stop(instr);
|
|
|
|
} else {
|
|
|
|
set_pc(get_pc() + 2 * Instruction::kInstrSize);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
bool Simulator::IsStopInstruction(Instruction* instr) {
|
|
|
|
int32_t func = instr->FunctionFieldRaw();
|
|
|
|
uint32_t code = static_cast<uint32_t>(instr->Bits(25, 6));
|
|
|
|
return (func == BREAK) && code > kMaxWatchpointCode && code <= kMaxStopCode;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
bool Simulator::IsEnabledStop(uint32_t code) {
|
|
|
|
ASSERT(code <= kMaxStopCode);
|
|
|
|
ASSERT(code > kMaxWatchpointCode);
|
2013-04-02 12:36:16 +00:00
|
|
|
return !(watched_stops_[code].count & kStopDisabledBit);
|
2011-05-26 07:46:18 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Simulator::EnableStop(uint32_t code) {
|
|
|
|
if (!IsEnabledStop(code)) {
|
2013-04-02 12:36:16 +00:00
|
|
|
watched_stops_[code].count &= ~kStopDisabledBit;
|
2011-05-26 07:46:18 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Simulator::DisableStop(uint32_t code) {
|
|
|
|
if (IsEnabledStop(code)) {
|
2013-04-02 12:36:16 +00:00
|
|
|
watched_stops_[code].count |= kStopDisabledBit;
|
2011-05-26 07:46:18 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Simulator::IncreaseStopCounter(uint32_t code) {
|
|
|
|
ASSERT(code <= kMaxStopCode);
|
2013-04-02 12:36:16 +00:00
|
|
|
if ((watched_stops_[code].count & ~(1 << 31)) == 0x7fffffff) {
|
2011-05-26 07:46:18 +00:00
|
|
|
PrintF("Stop counter for code %i has overflowed.\n"
|
|
|
|
"Enabling this code and reseting the counter to 0.\n", code);
|
2013-04-02 12:36:16 +00:00
|
|
|
watched_stops_[code].count = 0;
|
2011-05-26 07:46:18 +00:00
|
|
|
EnableStop(code);
|
|
|
|
} else {
|
2013-04-02 12:36:16 +00:00
|
|
|
watched_stops_[code].count++;
|
2011-05-26 07:46:18 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// Print a stop status.
|
|
|
|
void Simulator::PrintStopInfo(uint32_t code) {
|
|
|
|
if (code <= kMaxWatchpointCode) {
|
|
|
|
PrintF("That is a watchpoint, not a stop.\n");
|
|
|
|
return;
|
|
|
|
} else if (code > kMaxStopCode) {
|
|
|
|
PrintF("Code too large, only %u stops can be used\n", kMaxStopCode + 1);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
const char* state = IsEnabledStop(code) ? "Enabled" : "Disabled";
|
2013-04-02 12:36:16 +00:00
|
|
|
int32_t count = watched_stops_[code].count & ~kStopDisabledBit;
|
2011-05-26 07:46:18 +00:00
|
|
|
// Don't print the state of unused breakpoints.
|
|
|
|
if (count != 0) {
|
2013-04-02 12:36:16 +00:00
|
|
|
if (watched_stops_[code].desc) {
|
2011-05-26 07:46:18 +00:00
|
|
|
PrintF("stop %i - 0x%x: \t%s, \tcounter = %i, \t%s\n",
|
2013-04-02 12:36:16 +00:00
|
|
|
code, code, state, count, watched_stops_[code].desc);
|
2011-05-26 07:46:18 +00:00
|
|
|
} else {
|
|
|
|
PrintF("stop %i - 0x%x: \t%s, \tcounter = %i\n",
|
|
|
|
code, code, state, count);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-02-04 20:36:58 +00:00
|
|
|
void Simulator::SignalExceptions() {
|
|
|
|
for (int i = 1; i < kNumExceptions; i++) {
|
|
|
|
if (exceptions[i] != 0) {
|
|
|
|
V8_Fatal(__FILE__, __LINE__, "Error: Exception %i raised.", i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
// Handle execution based on instruction types.
|
2010-02-04 20:36:58 +00:00
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
void Simulator::ConfigureTypeRegister(Instruction* instr,
|
|
|
|
int32_t& alu_out,
|
|
|
|
int64_t& i64hilo,
|
|
|
|
uint64_t& u64hilo,
|
|
|
|
int32_t& next_pc,
|
|
|
|
bool& do_interrupt) {
|
|
|
|
// Every local variable declared here needs to be const.
|
|
|
|
// This is to make sure that changed values are sent back to
|
|
|
|
// DecodeTypeRegister correctly.
|
|
|
|
|
|
|
|
// Instruction fields.
|
|
|
|
const Opcode op = instr->OpcodeFieldRaw();
|
|
|
|
const int32_t rs_reg = instr->RsValue();
|
|
|
|
const int32_t rs = get_register(rs_reg);
|
|
|
|
const uint32_t rs_u = static_cast<uint32_t>(rs);
|
|
|
|
const int32_t rt_reg = instr->RtValue();
|
|
|
|
const int32_t rt = get_register(rt_reg);
|
|
|
|
const uint32_t rt_u = static_cast<uint32_t>(rt);
|
|
|
|
const int32_t rd_reg = instr->RdValue();
|
|
|
|
const uint32_t sa = instr->SaValue();
|
|
|
|
|
|
|
|
const int32_t fs_reg = instr->FsValue();
|
2010-02-04 20:36:58 +00:00
|
|
|
|
|
|
|
|
2011-05-09 14:28:09 +00:00
|
|
|
// ---------- Configuration.
|
2010-02-04 20:36:58 +00:00
|
|
|
switch (op) {
|
2011-05-09 14:28:09 +00:00
|
|
|
case COP1: // Coprocessor instructions.
|
2010-02-04 20:36:58 +00:00
|
|
|
switch (instr->RsFieldRaw()) {
|
2011-03-28 13:05:36 +00:00
|
|
|
case BC1: // Handled in DecodeTypeImmed, should never come here.
|
2010-02-04 20:36:58 +00:00
|
|
|
UNREACHABLE();
|
|
|
|
break;
|
2011-03-28 13:05:36 +00:00
|
|
|
case CFC1:
|
|
|
|
// At the moment only FCSR is supported.
|
|
|
|
ASSERT(fs_reg == kFCSRRegister);
|
|
|
|
alu_out = FCSR_;
|
|
|
|
break;
|
2010-02-04 20:36:58 +00:00
|
|
|
case MFC1:
|
|
|
|
alu_out = get_fpu_register(fs_reg);
|
|
|
|
break;
|
|
|
|
case MFHC1:
|
2011-03-28 13:05:36 +00:00
|
|
|
UNIMPLEMENTED_MIPS();
|
2010-02-04 20:36:58 +00:00
|
|
|
break;
|
2011-03-28 13:05:36 +00:00
|
|
|
case CTC1:
|
2010-02-04 20:36:58 +00:00
|
|
|
case MTC1:
|
|
|
|
case MTHC1:
|
|
|
|
// Do the store in the execution step.
|
|
|
|
break;
|
|
|
|
case S:
|
|
|
|
case D:
|
|
|
|
case W:
|
|
|
|
case L:
|
|
|
|
case PS:
|
|
|
|
// Do everything in the execution step.
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNIMPLEMENTED_MIPS();
|
|
|
|
};
|
|
|
|
break;
|
2013-01-09 12:31:34 +00:00
|
|
|
case COP1X:
|
|
|
|
break;
|
2010-02-04 20:36:58 +00:00
|
|
|
case SPECIAL:
|
|
|
|
switch (instr->FunctionFieldRaw()) {
|
|
|
|
case JR:
|
|
|
|
case JALR:
|
2011-03-28 13:05:36 +00:00
|
|
|
next_pc = get_register(instr->RsValue());
|
2010-02-04 20:36:58 +00:00
|
|
|
break;
|
|
|
|
case SLL:
|
|
|
|
alu_out = rt << sa;
|
|
|
|
break;
|
|
|
|
case SRL:
|
2011-03-28 13:05:36 +00:00
|
|
|
if (rs_reg == 0) {
|
|
|
|
// Regular logical right shift of a word by a fixed number of
|
|
|
|
// bits instruction. RS field is always equal to 0.
|
|
|
|
alu_out = rt_u >> sa;
|
|
|
|
} else {
|
|
|
|
// Logical right-rotate of a word by a fixed number of bits. This
|
|
|
|
// is special case of SRL instruction, added in MIPS32 Release 2.
|
2011-05-09 14:28:09 +00:00
|
|
|
// RS field is equal to 00001.
|
2011-03-28 13:05:36 +00:00
|
|
|
alu_out = (rt_u >> sa) | (rt_u << (32 - sa));
|
|
|
|
}
|
2010-02-04 20:36:58 +00:00
|
|
|
break;
|
|
|
|
case SRA:
|
|
|
|
alu_out = rt >> sa;
|
|
|
|
break;
|
|
|
|
case SLLV:
|
|
|
|
alu_out = rt << rs;
|
|
|
|
break;
|
|
|
|
case SRLV:
|
2011-03-28 13:05:36 +00:00
|
|
|
if (sa == 0) {
|
|
|
|
// Regular logical right-shift of a word by a variable number of
|
|
|
|
// bits instruction. SA field is always equal to 0.
|
|
|
|
alu_out = rt_u >> rs;
|
|
|
|
} else {
|
|
|
|
// Logical right-rotate of a word by a variable number of bits.
|
|
|
|
// This is special case od SRLV instruction, added in MIPS32
|
2011-05-09 14:28:09 +00:00
|
|
|
// Release 2. SA field is equal to 00001.
|
2011-03-28 13:05:36 +00:00
|
|
|
alu_out = (rt_u >> rs_u) | (rt_u << (32 - rs_u));
|
|
|
|
}
|
2010-02-04 20:36:58 +00:00
|
|
|
break;
|
|
|
|
case SRAV:
|
|
|
|
alu_out = rt >> rs;
|
|
|
|
break;
|
|
|
|
case MFHI:
|
|
|
|
alu_out = get_register(HI);
|
|
|
|
break;
|
|
|
|
case MFLO:
|
|
|
|
alu_out = get_register(LO);
|
|
|
|
break;
|
|
|
|
case MULT:
|
2011-03-28 13:05:36 +00:00
|
|
|
i64hilo = static_cast<int64_t>(rs) * static_cast<int64_t>(rt);
|
2010-02-04 20:36:58 +00:00
|
|
|
break;
|
|
|
|
case MULTU:
|
2011-03-28 13:05:36 +00:00
|
|
|
u64hilo = static_cast<uint64_t>(rs_u) * static_cast<uint64_t>(rt_u);
|
2010-02-04 20:36:58 +00:00
|
|
|
break;
|
|
|
|
case ADD:
|
|
|
|
if (HaveSameSign(rs, rt)) {
|
|
|
|
if (rs > 0) {
|
|
|
|
exceptions[kIntegerOverflow] = rs > (Registers::kMaxValue - rt);
|
|
|
|
} else if (rs < 0) {
|
|
|
|
exceptions[kIntegerUnderflow] = rs < (Registers::kMinValue - rt);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
alu_out = rs + rt;
|
|
|
|
break;
|
|
|
|
case ADDU:
|
|
|
|
alu_out = rs + rt;
|
|
|
|
break;
|
|
|
|
case SUB:
|
|
|
|
if (!HaveSameSign(rs, rt)) {
|
|
|
|
if (rs > 0) {
|
|
|
|
exceptions[kIntegerOverflow] = rs > (Registers::kMaxValue + rt);
|
|
|
|
} else if (rs < 0) {
|
|
|
|
exceptions[kIntegerUnderflow] = rs < (Registers::kMinValue + rt);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
alu_out = rs - rt;
|
|
|
|
break;
|
|
|
|
case SUBU:
|
|
|
|
alu_out = rs - rt;
|
|
|
|
break;
|
|
|
|
case AND:
|
|
|
|
alu_out = rs & rt;
|
|
|
|
break;
|
|
|
|
case OR:
|
|
|
|
alu_out = rs | rt;
|
|
|
|
break;
|
|
|
|
case XOR:
|
|
|
|
alu_out = rs ^ rt;
|
|
|
|
break;
|
|
|
|
case NOR:
|
|
|
|
alu_out = ~(rs | rt);
|
|
|
|
break;
|
|
|
|
case SLT:
|
|
|
|
alu_out = rs < rt ? 1 : 0;
|
|
|
|
break;
|
|
|
|
case SLTU:
|
|
|
|
alu_out = rs_u < rt_u ? 1 : 0;
|
|
|
|
break;
|
2011-05-09 14:28:09 +00:00
|
|
|
// Break and trap instructions.
|
2010-02-04 20:36:58 +00:00
|
|
|
case BREAK:
|
2011-03-28 13:05:36 +00:00
|
|
|
|
2010-02-04 20:36:58 +00:00
|
|
|
do_interrupt = true;
|
|
|
|
break;
|
|
|
|
case TGE:
|
|
|
|
do_interrupt = rs >= rt;
|
|
|
|
break;
|
|
|
|
case TGEU:
|
|
|
|
do_interrupt = rs_u >= rt_u;
|
|
|
|
break;
|
|
|
|
case TLT:
|
|
|
|
do_interrupt = rs < rt;
|
|
|
|
break;
|
|
|
|
case TLTU:
|
|
|
|
do_interrupt = rs_u < rt_u;
|
|
|
|
break;
|
|
|
|
case TEQ:
|
|
|
|
do_interrupt = rs == rt;
|
|
|
|
break;
|
|
|
|
case TNE:
|
|
|
|
do_interrupt = rs != rt;
|
|
|
|
break;
|
2011-03-28 13:05:36 +00:00
|
|
|
case MOVN:
|
|
|
|
case MOVZ:
|
|
|
|
case MOVCI:
|
|
|
|
// No action taken on decode.
|
|
|
|
break;
|
2011-05-09 14:28:09 +00:00
|
|
|
case DIV:
|
|
|
|
case DIVU:
|
|
|
|
// div and divu never raise exceptions.
|
|
|
|
break;
|
2010-02-04 20:36:58 +00:00
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
};
|
|
|
|
break;
|
|
|
|
case SPECIAL2:
|
|
|
|
switch (instr->FunctionFieldRaw()) {
|
|
|
|
case MUL:
|
|
|
|
alu_out = rs_u * rt_u; // Only the lower 32 bits are kept.
|
|
|
|
break;
|
2011-03-28 13:05:36 +00:00
|
|
|
case CLZ:
|
|
|
|
alu_out = __builtin_clz(rs_u);
|
|
|
|
break;
|
2010-02-04 20:36:58 +00:00
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
2011-03-28 13:05:36 +00:00
|
|
|
};
|
|
|
|
break;
|
|
|
|
case SPECIAL3:
|
|
|
|
switch (instr->FunctionFieldRaw()) {
|
|
|
|
case INS: { // Mips32r2 instruction.
|
2011-05-09 14:28:09 +00:00
|
|
|
// Interpret rd field as 5-bit msb of insert.
|
2011-03-28 13:05:36 +00:00
|
|
|
uint16_t msb = rd_reg;
|
|
|
|
// Interpret sa field as 5-bit lsb of insert.
|
|
|
|
uint16_t lsb = sa;
|
|
|
|
uint16_t size = msb - lsb + 1;
|
|
|
|
uint32_t mask = (1 << size) - 1;
|
|
|
|
alu_out = (rt_u & ~(mask << lsb)) | ((rs_u & mask) << lsb);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case EXT: { // Mips32r2 instruction.
|
2011-05-09 14:28:09 +00:00
|
|
|
// Interpret rd field as 5-bit msb of extract.
|
2011-03-28 13:05:36 +00:00
|
|
|
uint16_t msb = rd_reg;
|
|
|
|
// Interpret sa field as 5-bit lsb of extract.
|
|
|
|
uint16_t lsb = sa;
|
|
|
|
uint16_t size = msb + 1;
|
|
|
|
uint32_t mask = (1 << size) - 1;
|
|
|
|
alu_out = (rs_u & (mask << lsb)) >> lsb;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
};
|
2010-02-04 20:36:58 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
};
|
2011-03-28 13:05:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void Simulator::DecodeTypeRegister(Instruction* instr) {
|
|
|
|
// Instruction fields.
|
|
|
|
const Opcode op = instr->OpcodeFieldRaw();
|
|
|
|
const int32_t rs_reg = instr->RsValue();
|
|
|
|
const int32_t rs = get_register(rs_reg);
|
|
|
|
const uint32_t rs_u = static_cast<uint32_t>(rs);
|
|
|
|
const int32_t rt_reg = instr->RtValue();
|
|
|
|
const int32_t rt = get_register(rt_reg);
|
|
|
|
const uint32_t rt_u = static_cast<uint32_t>(rt);
|
|
|
|
const int32_t rd_reg = instr->RdValue();
|
|
|
|
|
2013-01-09 12:31:34 +00:00
|
|
|
const int32_t fr_reg = instr->FrValue();
|
2011-03-28 13:05:36 +00:00
|
|
|
const int32_t fs_reg = instr->FsValue();
|
|
|
|
const int32_t ft_reg = instr->FtValue();
|
|
|
|
const int32_t fd_reg = instr->FdValue();
|
|
|
|
int64_t i64hilo = 0;
|
|
|
|
uint64_t u64hilo = 0;
|
|
|
|
|
2011-05-09 14:28:09 +00:00
|
|
|
// ALU output.
|
2011-03-28 13:05:36 +00:00
|
|
|
// It should not be used as is. Instructions using it should always
|
|
|
|
// initialize it first.
|
|
|
|
int32_t alu_out = 0x12345678;
|
|
|
|
|
|
|
|
// For break and trap instructions.
|
|
|
|
bool do_interrupt = false;
|
|
|
|
|
2011-05-09 14:28:09 +00:00
|
|
|
// For jr and jalr.
|
2011-03-28 13:05:36 +00:00
|
|
|
// Get current pc.
|
|
|
|
int32_t current_pc = get_pc();
|
|
|
|
// Next pc
|
|
|
|
int32_t next_pc = 0;
|
|
|
|
|
2012-01-13 13:09:52 +00:00
|
|
|
// Set up the variables if needed before executing the instruction.
|
2011-03-28 13:05:36 +00:00
|
|
|
ConfigureTypeRegister(instr,
|
|
|
|
alu_out,
|
|
|
|
i64hilo,
|
|
|
|
u64hilo,
|
|
|
|
next_pc,
|
|
|
|
do_interrupt);
|
2010-02-04 20:36:58 +00:00
|
|
|
|
|
|
|
// ---------- Raise exceptions triggered.
|
|
|
|
SignalExceptions();
|
|
|
|
|
2011-05-09 14:28:09 +00:00
|
|
|
// ---------- Execution.
|
2010-02-04 20:36:58 +00:00
|
|
|
switch (op) {
|
|
|
|
case COP1:
|
|
|
|
switch (instr->RsFieldRaw()) {
|
2011-05-09 14:28:09 +00:00
|
|
|
case BC1: // Branch on coprocessor condition.
|
2010-02-04 20:36:58 +00:00
|
|
|
UNREACHABLE();
|
|
|
|
break;
|
2011-03-28 13:05:36 +00:00
|
|
|
case CFC1:
|
|
|
|
set_register(rt_reg, alu_out);
|
2010-02-04 20:36:58 +00:00
|
|
|
case MFC1:
|
|
|
|
set_register(rt_reg, alu_out);
|
|
|
|
break;
|
2011-03-28 13:05:36 +00:00
|
|
|
case MFHC1:
|
|
|
|
UNIMPLEMENTED_MIPS();
|
|
|
|
break;
|
|
|
|
case CTC1:
|
|
|
|
// At the moment only FCSR is supported.
|
|
|
|
ASSERT(fs_reg == kFCSRRegister);
|
|
|
|
FCSR_ = registers_[rt_reg];
|
|
|
|
break;
|
2010-02-04 20:36:58 +00:00
|
|
|
case MTC1:
|
|
|
|
FPUregisters_[fs_reg] = registers_[rt_reg];
|
|
|
|
break;
|
|
|
|
case MTHC1:
|
2011-03-28 13:05:36 +00:00
|
|
|
UNIMPLEMENTED_MIPS();
|
2010-02-04 20:36:58 +00:00
|
|
|
break;
|
|
|
|
case S:
|
2011-03-28 13:05:36 +00:00
|
|
|
float f;
|
2010-02-04 20:36:58 +00:00
|
|
|
switch (instr->FunctionFieldRaw()) {
|
|
|
|
case CVT_D_S:
|
2011-03-28 13:05:36 +00:00
|
|
|
f = get_fpu_register_float(fs_reg);
|
|
|
|
set_fpu_register_double(fd_reg, static_cast<double>(f));
|
|
|
|
break;
|
2010-02-04 20:36:58 +00:00
|
|
|
case CVT_W_S:
|
|
|
|
case CVT_L_S:
|
2011-03-28 13:05:36 +00:00
|
|
|
case TRUNC_W_S:
|
|
|
|
case TRUNC_L_S:
|
|
|
|
case ROUND_W_S:
|
|
|
|
case ROUND_L_S:
|
|
|
|
case FLOOR_W_S:
|
|
|
|
case FLOOR_L_S:
|
|
|
|
case CEIL_W_S:
|
|
|
|
case CEIL_L_S:
|
2010-02-04 20:36:58 +00:00
|
|
|
case CVT_PS_S:
|
|
|
|
UNIMPLEMENTED_MIPS();
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case D:
|
2011-03-28 13:05:36 +00:00
|
|
|
double ft, fs;
|
|
|
|
uint32_t cc, fcsr_cc;
|
|
|
|
int64_t i64;
|
|
|
|
fs = get_fpu_register_double(fs_reg);
|
|
|
|
ft = get_fpu_register_double(ft_reg);
|
|
|
|
cc = instr->FCccValue();
|
|
|
|
fcsr_cc = get_fcsr_condition_bit(cc);
|
2010-02-04 20:36:58 +00:00
|
|
|
switch (instr->FunctionFieldRaw()) {
|
2011-03-28 13:05:36 +00:00
|
|
|
case ADD_D:
|
|
|
|
set_fpu_register_double(fd_reg, fs + ft);
|
|
|
|
break;
|
|
|
|
case SUB_D:
|
|
|
|
set_fpu_register_double(fd_reg, fs - ft);
|
|
|
|
break;
|
|
|
|
case MUL_D:
|
|
|
|
set_fpu_register_double(fd_reg, fs * ft);
|
|
|
|
break;
|
|
|
|
case DIV_D:
|
|
|
|
set_fpu_register_double(fd_reg, fs / ft);
|
|
|
|
break;
|
|
|
|
case ABS_D:
|
|
|
|
set_fpu_register_double(fd_reg, fs < 0 ? -fs : fs);
|
|
|
|
break;
|
|
|
|
case MOV_D:
|
|
|
|
set_fpu_register_double(fd_reg, fs);
|
|
|
|
break;
|
|
|
|
case NEG_D:
|
|
|
|
set_fpu_register_double(fd_reg, -fs);
|
|
|
|
break;
|
|
|
|
case SQRT_D:
|
|
|
|
set_fpu_register_double(fd_reg, sqrt(fs));
|
|
|
|
break;
|
|
|
|
case C_UN_D:
|
|
|
|
set_fcsr_bit(fcsr_cc, isnan(fs) || isnan(ft));
|
|
|
|
break;
|
|
|
|
case C_EQ_D:
|
|
|
|
set_fcsr_bit(fcsr_cc, (fs == ft));
|
|
|
|
break;
|
|
|
|
case C_UEQ_D:
|
|
|
|
set_fcsr_bit(fcsr_cc, (fs == ft) || (isnan(fs) || isnan(ft)));
|
|
|
|
break;
|
|
|
|
case C_OLT_D:
|
|
|
|
set_fcsr_bit(fcsr_cc, (fs < ft));
|
|
|
|
break;
|
|
|
|
case C_ULT_D:
|
|
|
|
set_fcsr_bit(fcsr_cc, (fs < ft) || (isnan(fs) || isnan(ft)));
|
|
|
|
break;
|
|
|
|
case C_OLE_D:
|
|
|
|
set_fcsr_bit(fcsr_cc, (fs <= ft));
|
|
|
|
break;
|
|
|
|
case C_ULE_D:
|
|
|
|
set_fcsr_bit(fcsr_cc, (fs <= ft) || (isnan(fs) || isnan(ft)));
|
|
|
|
break;
|
|
|
|
case CVT_W_D: // Convert double to word.
|
|
|
|
// Rounding modes are not yet supported.
|
|
|
|
ASSERT((FCSR_ & 3) == 0);
|
|
|
|
// In rounding mode 0 it should behave like ROUND.
|
2012-08-27 07:29:36 +00:00
|
|
|
case ROUND_W_D: // Round double to word (round half to even).
|
2011-03-28 13:05:36 +00:00
|
|
|
{
|
2012-08-27 07:29:36 +00:00
|
|
|
double rounded = floor(fs + 0.5);
|
2011-03-28 13:05:36 +00:00
|
|
|
int32_t result = static_cast<int32_t>(rounded);
|
2012-08-27 07:29:36 +00:00
|
|
|
if ((result & 1) != 0 && result - fs == 0.5) {
|
|
|
|
// If the number is halfway between two integers,
|
|
|
|
// round to the even one.
|
|
|
|
result--;
|
|
|
|
}
|
2011-03-28 13:05:36 +00:00
|
|
|
set_fpu_register(fd_reg, result);
|
|
|
|
if (set_fcsr_round_error(fs, rounded)) {
|
|
|
|
set_fpu_register(fd_reg, kFPUInvalidResult);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case TRUNC_W_D: // Truncate double to word (round towards 0).
|
|
|
|
{
|
2011-06-06 08:43:15 +00:00
|
|
|
double rounded = trunc(fs);
|
|
|
|
int32_t result = static_cast<int32_t>(rounded);
|
2011-03-28 13:05:36 +00:00
|
|
|
set_fpu_register(fd_reg, result);
|
2011-06-06 08:43:15 +00:00
|
|
|
if (set_fcsr_round_error(fs, rounded)) {
|
2011-03-28 13:05:36 +00:00
|
|
|
set_fpu_register(fd_reg, kFPUInvalidResult);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case FLOOR_W_D: // Round double to word towards negative infinity.
|
|
|
|
{
|
|
|
|
double rounded = floor(fs);
|
|
|
|
int32_t result = static_cast<int32_t>(rounded);
|
|
|
|
set_fpu_register(fd_reg, result);
|
|
|
|
if (set_fcsr_round_error(fs, rounded)) {
|
|
|
|
set_fpu_register(fd_reg, kFPUInvalidResult);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
2011-03-28 13:37:09 +00:00
|
|
|
case CEIL_W_D: // Round double to word towards positive infinity.
|
2011-03-28 13:05:36 +00:00
|
|
|
{
|
|
|
|
double rounded = ceil(fs);
|
|
|
|
int32_t result = static_cast<int32_t>(rounded);
|
|
|
|
set_fpu_register(fd_reg, result);
|
|
|
|
if (set_fcsr_round_error(fs, rounded)) {
|
|
|
|
set_fpu_register(fd_reg, kFPUInvalidResult);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case CVT_S_D: // Convert double to float (single).
|
|
|
|
set_fpu_register_float(fd_reg, static_cast<float>(fs));
|
|
|
|
break;
|
2011-06-06 08:43:15 +00:00
|
|
|
case CVT_L_D: { // Mips32r2: Truncate double to 64-bit long-word.
|
|
|
|
double rounded = trunc(fs);
|
|
|
|
i64 = static_cast<int64_t>(rounded);
|
2011-03-28 13:05:36 +00:00
|
|
|
set_fpu_register(fd_reg, i64 & 0xffffffff);
|
|
|
|
set_fpu_register(fd_reg + 1, i64 >> 32);
|
|
|
|
break;
|
2011-06-06 08:43:15 +00:00
|
|
|
}
|
|
|
|
case TRUNC_L_D: { // Mips32r2 instruction.
|
|
|
|
double rounded = trunc(fs);
|
|
|
|
i64 = static_cast<int64_t>(rounded);
|
2011-03-28 13:05:36 +00:00
|
|
|
set_fpu_register(fd_reg, i64 & 0xffffffff);
|
|
|
|
set_fpu_register(fd_reg + 1, i64 >> 32);
|
|
|
|
break;
|
2011-06-06 08:43:15 +00:00
|
|
|
}
|
2011-03-28 13:05:36 +00:00
|
|
|
case ROUND_L_D: { // Mips32r2 instruction.
|
|
|
|
double rounded = fs > 0 ? floor(fs + 0.5) : ceil(fs - 0.5);
|
|
|
|
i64 = static_cast<int64_t>(rounded);
|
|
|
|
set_fpu_register(fd_reg, i64 & 0xffffffff);
|
|
|
|
set_fpu_register(fd_reg + 1, i64 >> 32);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case FLOOR_L_D: // Mips32r2 instruction.
|
|
|
|
i64 = static_cast<int64_t>(floor(fs));
|
|
|
|
set_fpu_register(fd_reg, i64 & 0xffffffff);
|
|
|
|
set_fpu_register(fd_reg + 1, i64 >> 32);
|
|
|
|
break;
|
|
|
|
case CEIL_L_D: // Mips32r2 instruction.
|
|
|
|
i64 = static_cast<int64_t>(ceil(fs));
|
|
|
|
set_fpu_register(fd_reg, i64 & 0xffffffff);
|
|
|
|
set_fpu_register(fd_reg + 1, i64 >> 32);
|
|
|
|
break;
|
|
|
|
case C_F_D:
|
2010-02-04 20:36:58 +00:00
|
|
|
UNIMPLEMENTED_MIPS();
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case W:
|
|
|
|
switch (instr->FunctionFieldRaw()) {
|
2011-03-28 13:05:36 +00:00
|
|
|
case CVT_S_W: // Convert word to float (single).
|
|
|
|
alu_out = get_fpu_register(fs_reg);
|
|
|
|
set_fpu_register_float(fd_reg, static_cast<float>(alu_out));
|
2010-02-04 20:36:58 +00:00
|
|
|
break;
|
|
|
|
case CVT_D_W: // Convert word to double.
|
2011-03-28 13:05:36 +00:00
|
|
|
alu_out = get_fpu_register(fs_reg);
|
|
|
|
set_fpu_register_double(fd_reg, static_cast<double>(alu_out));
|
2010-02-04 20:36:58 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
};
|
|
|
|
break;
|
|
|
|
case L:
|
|
|
|
switch (instr->FunctionFieldRaw()) {
|
2011-03-28 13:05:36 +00:00
|
|
|
case CVT_D_L: // Mips32r2 instruction.
|
|
|
|
// Watch the signs here, we want 2 32-bit vals
|
|
|
|
// to make a sign-64.
|
2013-01-07 15:02:56 +00:00
|
|
|
i64 = static_cast<uint32_t>(get_fpu_register(fs_reg));
|
|
|
|
i64 |= static_cast<int64_t>(get_fpu_register(fs_reg + 1)) << 32;
|
2011-03-28 13:05:36 +00:00
|
|
|
set_fpu_register_double(fd_reg, static_cast<double>(i64));
|
|
|
|
break;
|
2010-02-04 20:36:58 +00:00
|
|
|
case CVT_S_L:
|
|
|
|
UNIMPLEMENTED_MIPS();
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case PS:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
};
|
|
|
|
break;
|
2013-01-09 12:31:34 +00:00
|
|
|
case COP1X:
|
|
|
|
switch (instr->FunctionFieldRaw()) {
|
|
|
|
case MADD_D:
|
|
|
|
double fr, ft, fs;
|
|
|
|
fr = get_fpu_register_double(fr_reg);
|
|
|
|
fs = get_fpu_register_double(fs_reg);
|
|
|
|
ft = get_fpu_register_double(ft_reg);
|
|
|
|
set_fpu_register_double(fd_reg, fs * ft + fr);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
};
|
|
|
|
break;
|
2010-02-04 20:36:58 +00:00
|
|
|
case SPECIAL:
|
|
|
|
switch (instr->FunctionFieldRaw()) {
|
|
|
|
case JR: {
|
|
|
|
Instruction* branch_delay_instr = reinterpret_cast<Instruction*>(
|
2011-03-28 13:05:36 +00:00
|
|
|
current_pc+Instruction::kInstrSize);
|
2010-02-04 20:36:58 +00:00
|
|
|
BranchDelayInstructionDecode(branch_delay_instr);
|
|
|
|
set_pc(next_pc);
|
|
|
|
pc_modified_ = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case JALR: {
|
|
|
|
Instruction* branch_delay_instr = reinterpret_cast<Instruction*>(
|
2011-03-28 13:05:36 +00:00
|
|
|
current_pc+Instruction::kInstrSize);
|
2010-02-04 20:36:58 +00:00
|
|
|
BranchDelayInstructionDecode(branch_delay_instr);
|
2011-05-09 14:28:09 +00:00
|
|
|
set_register(31, current_pc + 2 * Instruction::kInstrSize);
|
2010-02-04 20:36:58 +00:00
|
|
|
set_pc(next_pc);
|
|
|
|
pc_modified_ = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
// Instructions using HI and LO registers.
|
|
|
|
case MULT:
|
2011-03-28 13:05:36 +00:00
|
|
|
set_register(LO, static_cast<int32_t>(i64hilo & 0xffffffff));
|
|
|
|
set_register(HI, static_cast<int32_t>(i64hilo >> 32));
|
|
|
|
break;
|
2010-02-04 20:36:58 +00:00
|
|
|
case MULTU:
|
2011-03-28 13:05:36 +00:00
|
|
|
set_register(LO, static_cast<int32_t>(u64hilo & 0xffffffff));
|
|
|
|
set_register(HI, static_cast<int32_t>(u64hilo >> 32));
|
2010-02-04 20:36:58 +00:00
|
|
|
break;
|
|
|
|
case DIV:
|
2012-11-20 14:11:53 +00:00
|
|
|
// Divide by zero and overflow was not checked in the configuration
|
|
|
|
// step - div and divu do not raise exceptions. On division by 0 and
|
|
|
|
// on overflow (INT_MIN/-1), the result will be UNPREDICTABLE.
|
|
|
|
if (rt != 0 && !(rs == INT_MIN && rt == -1)) {
|
2011-05-09 14:28:09 +00:00
|
|
|
set_register(LO, rs / rt);
|
|
|
|
set_register(HI, rs % rt);
|
|
|
|
}
|
2010-02-04 20:36:58 +00:00
|
|
|
break;
|
|
|
|
case DIVU:
|
2011-05-09 14:28:09 +00:00
|
|
|
if (rt_u != 0) {
|
|
|
|
set_register(LO, rs_u / rt_u);
|
|
|
|
set_register(HI, rs_u % rt_u);
|
|
|
|
}
|
2010-02-04 20:36:58 +00:00
|
|
|
break;
|
2011-03-28 13:05:36 +00:00
|
|
|
// Break and trap instructions.
|
2010-02-04 20:36:58 +00:00
|
|
|
case BREAK:
|
|
|
|
case TGE:
|
|
|
|
case TGEU:
|
|
|
|
case TLT:
|
|
|
|
case TLTU:
|
|
|
|
case TEQ:
|
|
|
|
case TNE:
|
|
|
|
if (do_interrupt) {
|
|
|
|
SoftwareInterrupt(instr);
|
|
|
|
}
|
|
|
|
break;
|
2011-03-28 13:05:36 +00:00
|
|
|
// Conditional moves.
|
|
|
|
case MOVN:
|
|
|
|
if (rt) set_register(rd_reg, rs);
|
|
|
|
break;
|
|
|
|
case MOVCI: {
|
2011-05-09 14:28:09 +00:00
|
|
|
uint32_t cc = instr->FBccValue();
|
2011-03-28 13:05:36 +00:00
|
|
|
uint32_t fcsr_cc = get_fcsr_condition_bit(cc);
|
2011-05-09 14:28:09 +00:00
|
|
|
if (instr->Bit(16)) { // Read Tf bit.
|
2011-03-28 13:05:36 +00:00
|
|
|
if (test_fcsr_bit(fcsr_cc)) set_register(rd_reg, rs);
|
|
|
|
} else {
|
|
|
|
if (!test_fcsr_bit(fcsr_cc)) set_register(rd_reg, rs);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case MOVZ:
|
|
|
|
if (!rt) set_register(rd_reg, rs);
|
|
|
|
break;
|
2010-02-04 20:36:58 +00:00
|
|
|
default: // For other special opcodes we do the default operation.
|
|
|
|
set_register(rd_reg, alu_out);
|
|
|
|
};
|
|
|
|
break;
|
|
|
|
case SPECIAL2:
|
|
|
|
switch (instr->FunctionFieldRaw()) {
|
|
|
|
case MUL:
|
|
|
|
set_register(rd_reg, alu_out);
|
|
|
|
// HI and LO are UNPREDICTABLE after the operation.
|
|
|
|
set_register(LO, Unpredictable);
|
|
|
|
set_register(HI, Unpredictable);
|
|
|
|
break;
|
2011-03-28 13:05:36 +00:00
|
|
|
default: // For other special2 opcodes we do the default operation.
|
|
|
|
set_register(rd_reg, alu_out);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case SPECIAL3:
|
|
|
|
switch (instr->FunctionFieldRaw()) {
|
|
|
|
case INS:
|
|
|
|
// Ins instr leaves result in Rt, rather than Rd.
|
|
|
|
set_register(rt_reg, alu_out);
|
|
|
|
break;
|
|
|
|
case EXT:
|
|
|
|
// Ext instr leaves result in Rt, rather than Rd.
|
|
|
|
set_register(rt_reg, alu_out);
|
|
|
|
break;
|
2010-02-04 20:36:58 +00:00
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
2011-03-28 13:05:36 +00:00
|
|
|
};
|
2010-02-04 20:36:58 +00:00
|
|
|
break;
|
|
|
|
// Unimplemented opcodes raised an error in the configuration step before,
|
|
|
|
// so we can use the default here to set the destination register in common
|
|
|
|
// cases.
|
|
|
|
default:
|
|
|
|
set_register(rd_reg, alu_out);
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
|
2012-01-16 12:38:59 +00:00
|
|
|
// Type 2: instructions using a 16 bytes immediate. (e.g. addi, beq).
|
2010-02-04 20:36:58 +00:00
|
|
|
void Simulator::DecodeTypeImmediate(Instruction* instr) {
|
2011-03-28 13:05:36 +00:00
|
|
|
// Instruction fields.
|
2010-02-04 20:36:58 +00:00
|
|
|
Opcode op = instr->OpcodeFieldRaw();
|
2011-03-28 13:05:36 +00:00
|
|
|
int32_t rs = get_register(instr->RsValue());
|
2010-02-04 20:36:58 +00:00
|
|
|
uint32_t rs_u = static_cast<uint32_t>(rs);
|
2011-05-09 14:28:09 +00:00
|
|
|
int32_t rt_reg = instr->RtValue(); // Destination register.
|
2010-02-04 20:36:58 +00:00
|
|
|
int32_t rt = get_register(rt_reg);
|
2011-03-28 13:05:36 +00:00
|
|
|
int16_t imm16 = instr->Imm16Value();
|
2010-02-04 20:36:58 +00:00
|
|
|
|
2011-05-09 14:28:09 +00:00
|
|
|
int32_t ft_reg = instr->FtValue(); // Destination register.
|
2010-02-04 20:36:58 +00:00
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
// Zero extended immediate.
|
2010-02-04 20:36:58 +00:00
|
|
|
uint32_t oe_imm16 = 0xffff & imm16;
|
2011-03-28 13:05:36 +00:00
|
|
|
// Sign extended immediate.
|
2010-02-04 20:36:58 +00:00
|
|
|
int32_t se_imm16 = imm16;
|
|
|
|
|
|
|
|
// Get current pc.
|
|
|
|
int32_t current_pc = get_pc();
|
|
|
|
// Next pc.
|
|
|
|
int32_t next_pc = bad_ra;
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
// Used for conditional branch instructions.
|
2010-02-04 20:36:58 +00:00
|
|
|
bool do_branch = false;
|
|
|
|
bool execute_branch_delay_instruction = false;
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
// Used for arithmetic instructions.
|
2010-02-04 20:36:58 +00:00
|
|
|
int32_t alu_out = 0;
|
2011-03-28 13:05:36 +00:00
|
|
|
// Floating point.
|
2010-02-04 20:36:58 +00:00
|
|
|
double fp_out = 0.0;
|
2011-03-28 13:05:36 +00:00
|
|
|
uint32_t cc, cc_value, fcsr_cc;
|
2010-02-04 20:36:58 +00:00
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
// Used for memory instructions.
|
2010-02-04 20:36:58 +00:00
|
|
|
int32_t addr = 0x0;
|
2011-05-09 14:28:09 +00:00
|
|
|
// Value to be written in memory.
|
2011-03-28 13:05:36 +00:00
|
|
|
uint32_t mem_value = 0x0;
|
2010-02-04 20:36:58 +00:00
|
|
|
|
2011-05-09 14:28:09 +00:00
|
|
|
// ---------- Configuration (and execution for REGIMM).
|
2010-02-04 20:36:58 +00:00
|
|
|
switch (op) {
|
2011-03-28 13:05:36 +00:00
|
|
|
// ------------- COP1. Coprocessor instructions.
|
2010-02-04 20:36:58 +00:00
|
|
|
case COP1:
|
|
|
|
switch (instr->RsFieldRaw()) {
|
2011-03-28 13:05:36 +00:00
|
|
|
case BC1: // Branch on coprocessor condition.
|
|
|
|
cc = instr->FBccValue();
|
|
|
|
fcsr_cc = get_fcsr_condition_bit(cc);
|
|
|
|
cc_value = test_fcsr_bit(fcsr_cc);
|
|
|
|
do_branch = (instr->FBtrueValue()) ? cc_value : !cc_value;
|
|
|
|
execute_branch_delay_instruction = true;
|
2011-05-09 14:28:09 +00:00
|
|
|
// Set next_pc.
|
2011-03-28 13:05:36 +00:00
|
|
|
if (do_branch) {
|
|
|
|
next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize;
|
|
|
|
} else {
|
|
|
|
next_pc = current_pc + kBranchReturnOffset;
|
|
|
|
}
|
2010-02-04 20:36:58 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
};
|
|
|
|
break;
|
2011-05-09 14:28:09 +00:00
|
|
|
// ------------- REGIMM class.
|
2010-02-04 20:36:58 +00:00
|
|
|
case REGIMM:
|
|
|
|
switch (instr->RtFieldRaw()) {
|
|
|
|
case BLTZ:
|
|
|
|
do_branch = (rs < 0);
|
|
|
|
break;
|
|
|
|
case BLTZAL:
|
|
|
|
do_branch = rs < 0;
|
|
|
|
break;
|
|
|
|
case BGEZ:
|
|
|
|
do_branch = rs >= 0;
|
|
|
|
break;
|
|
|
|
case BGEZAL:
|
|
|
|
do_branch = rs >= 0;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
};
|
|
|
|
switch (instr->RtFieldRaw()) {
|
|
|
|
case BLTZ:
|
|
|
|
case BLTZAL:
|
|
|
|
case BGEZ:
|
|
|
|
case BGEZAL:
|
|
|
|
// Branch instructions common part.
|
|
|
|
execute_branch_delay_instruction = true;
|
2011-05-09 14:28:09 +00:00
|
|
|
// Set next_pc.
|
2010-02-04 20:36:58 +00:00
|
|
|
if (do_branch) {
|
2011-03-28 13:05:36 +00:00
|
|
|
next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize;
|
2010-02-04 20:36:58 +00:00
|
|
|
if (instr->IsLinkingInstruction()) {
|
|
|
|
set_register(31, current_pc + kBranchReturnOffset);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
next_pc = current_pc + kBranchReturnOffset;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
};
|
2011-05-09 14:28:09 +00:00
|
|
|
break; // case REGIMM.
|
|
|
|
// ------------- Branch instructions.
|
2010-02-04 20:36:58 +00:00
|
|
|
// When comparing to zero, the encoding of rt field is always 0, so we don't
|
|
|
|
// need to replace rt with zero.
|
|
|
|
case BEQ:
|
|
|
|
do_branch = (rs == rt);
|
|
|
|
break;
|
|
|
|
case BNE:
|
|
|
|
do_branch = rs != rt;
|
|
|
|
break;
|
|
|
|
case BLEZ:
|
|
|
|
do_branch = rs <= 0;
|
|
|
|
break;
|
|
|
|
case BGTZ:
|
|
|
|
do_branch = rs > 0;
|
|
|
|
break;
|
2011-05-09 14:28:09 +00:00
|
|
|
// ------------- Arithmetic instructions.
|
2010-02-04 20:36:58 +00:00
|
|
|
case ADDI:
|
|
|
|
if (HaveSameSign(rs, se_imm16)) {
|
|
|
|
if (rs > 0) {
|
|
|
|
exceptions[kIntegerOverflow] = rs > (Registers::kMaxValue - se_imm16);
|
|
|
|
} else if (rs < 0) {
|
|
|
|
exceptions[kIntegerUnderflow] =
|
|
|
|
rs < (Registers::kMinValue - se_imm16);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
alu_out = rs + se_imm16;
|
|
|
|
break;
|
|
|
|
case ADDIU:
|
|
|
|
alu_out = rs + se_imm16;
|
|
|
|
break;
|
|
|
|
case SLTI:
|
|
|
|
alu_out = (rs < se_imm16) ? 1 : 0;
|
|
|
|
break;
|
|
|
|
case SLTIU:
|
|
|
|
alu_out = (rs_u < static_cast<uint32_t>(se_imm16)) ? 1 : 0;
|
|
|
|
break;
|
|
|
|
case ANDI:
|
|
|
|
alu_out = rs & oe_imm16;
|
|
|
|
break;
|
|
|
|
case ORI:
|
|
|
|
alu_out = rs | oe_imm16;
|
|
|
|
break;
|
|
|
|
case XORI:
|
|
|
|
alu_out = rs ^ oe_imm16;
|
|
|
|
break;
|
|
|
|
case LUI:
|
|
|
|
alu_out = (oe_imm16 << 16);
|
|
|
|
break;
|
2011-05-09 14:28:09 +00:00
|
|
|
// ------------- Memory instructions.
|
2010-02-04 20:36:58 +00:00
|
|
|
case LB:
|
|
|
|
addr = rs + se_imm16;
|
|
|
|
alu_out = ReadB(addr);
|
|
|
|
break;
|
2011-03-28 13:05:36 +00:00
|
|
|
case LH:
|
|
|
|
addr = rs + se_imm16;
|
|
|
|
alu_out = ReadH(addr, instr);
|
|
|
|
break;
|
|
|
|
case LWL: {
|
2011-05-09 14:28:09 +00:00
|
|
|
// al_offset is offset of the effective address within an aligned word.
|
2011-03-28 13:05:36 +00:00
|
|
|
uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask;
|
|
|
|
uint8_t byte_shift = kPointerAlignmentMask - al_offset;
|
|
|
|
uint32_t mask = (1 << byte_shift * 8) - 1;
|
|
|
|
addr = rs + se_imm16 - al_offset;
|
|
|
|
alu_out = ReadW(addr, instr);
|
|
|
|
alu_out <<= byte_shift * 8;
|
|
|
|
alu_out |= rt & mask;
|
|
|
|
break;
|
|
|
|
}
|
2010-02-04 20:36:58 +00:00
|
|
|
case LW:
|
|
|
|
addr = rs + se_imm16;
|
|
|
|
alu_out = ReadW(addr, instr);
|
|
|
|
break;
|
|
|
|
case LBU:
|
|
|
|
addr = rs + se_imm16;
|
|
|
|
alu_out = ReadBU(addr);
|
|
|
|
break;
|
2011-03-28 13:05:36 +00:00
|
|
|
case LHU:
|
|
|
|
addr = rs + se_imm16;
|
|
|
|
alu_out = ReadHU(addr, instr);
|
|
|
|
break;
|
|
|
|
case LWR: {
|
2011-05-09 14:28:09 +00:00
|
|
|
// al_offset is offset of the effective address within an aligned word.
|
2011-03-28 13:05:36 +00:00
|
|
|
uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask;
|
|
|
|
uint8_t byte_shift = kPointerAlignmentMask - al_offset;
|
|
|
|
uint32_t mask = al_offset ? (~0 << (byte_shift + 1) * 8) : 0;
|
|
|
|
addr = rs + se_imm16 - al_offset;
|
|
|
|
alu_out = ReadW(addr, instr);
|
|
|
|
alu_out = static_cast<uint32_t> (alu_out) >> al_offset * 8;
|
|
|
|
alu_out |= rt & mask;
|
|
|
|
break;
|
|
|
|
}
|
2010-02-04 20:36:58 +00:00
|
|
|
case SB:
|
|
|
|
addr = rs + se_imm16;
|
|
|
|
break;
|
2011-03-28 13:05:36 +00:00
|
|
|
case SH:
|
|
|
|
addr = rs + se_imm16;
|
|
|
|
break;
|
|
|
|
case SWL: {
|
|
|
|
uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask;
|
|
|
|
uint8_t byte_shift = kPointerAlignmentMask - al_offset;
|
|
|
|
uint32_t mask = byte_shift ? (~0 << (al_offset + 1) * 8) : 0;
|
|
|
|
addr = rs + se_imm16 - al_offset;
|
|
|
|
mem_value = ReadW(addr, instr) & mask;
|
|
|
|
mem_value |= static_cast<uint32_t>(rt) >> byte_shift * 8;
|
|
|
|
break;
|
|
|
|
}
|
2010-02-04 20:36:58 +00:00
|
|
|
case SW:
|
|
|
|
addr = rs + se_imm16;
|
|
|
|
break;
|
2011-03-28 13:05:36 +00:00
|
|
|
case SWR: {
|
|
|
|
uint8_t al_offset = (rs + se_imm16) & kPointerAlignmentMask;
|
|
|
|
uint32_t mask = (1 << al_offset * 8) - 1;
|
|
|
|
addr = rs + se_imm16 - al_offset;
|
|
|
|
mem_value = ReadW(addr, instr);
|
|
|
|
mem_value = (rt << al_offset * 8) | (mem_value & mask);
|
|
|
|
break;
|
|
|
|
}
|
2010-02-04 20:36:58 +00:00
|
|
|
case LWC1:
|
|
|
|
addr = rs + se_imm16;
|
|
|
|
alu_out = ReadW(addr, instr);
|
|
|
|
break;
|
|
|
|
case LDC1:
|
|
|
|
addr = rs + se_imm16;
|
|
|
|
fp_out = ReadD(addr, instr);
|
|
|
|
break;
|
|
|
|
case SWC1:
|
|
|
|
case SDC1:
|
|
|
|
addr = rs + se_imm16;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
};
|
|
|
|
|
|
|
|
// ---------- Raise exceptions triggered.
|
|
|
|
SignalExceptions();
|
|
|
|
|
2011-05-09 14:28:09 +00:00
|
|
|
// ---------- Execution.
|
2010-02-04 20:36:58 +00:00
|
|
|
switch (op) {
|
2011-05-09 14:28:09 +00:00
|
|
|
// ------------- Branch instructions.
|
2010-02-04 20:36:58 +00:00
|
|
|
case BEQ:
|
|
|
|
case BNE:
|
|
|
|
case BLEZ:
|
|
|
|
case BGTZ:
|
|
|
|
// Branch instructions common part.
|
|
|
|
execute_branch_delay_instruction = true;
|
2011-05-09 14:28:09 +00:00
|
|
|
// Set next_pc.
|
2010-02-04 20:36:58 +00:00
|
|
|
if (do_branch) {
|
2011-03-28 13:05:36 +00:00
|
|
|
next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize;
|
2010-02-04 20:36:58 +00:00
|
|
|
if (instr->IsLinkingInstruction()) {
|
2011-03-28 13:05:36 +00:00
|
|
|
set_register(31, current_pc + 2* Instruction::kInstrSize);
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
} else {
|
2011-03-28 13:05:36 +00:00
|
|
|
next_pc = current_pc + 2 * Instruction::kInstrSize;
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
break;
|
2011-05-09 14:28:09 +00:00
|
|
|
// ------------- Arithmetic instructions.
|
2010-02-04 20:36:58 +00:00
|
|
|
case ADDI:
|
|
|
|
case ADDIU:
|
|
|
|
case SLTI:
|
|
|
|
case SLTIU:
|
|
|
|
case ANDI:
|
|
|
|
case ORI:
|
|
|
|
case XORI:
|
|
|
|
case LUI:
|
|
|
|
set_register(rt_reg, alu_out);
|
|
|
|
break;
|
2011-05-09 14:28:09 +00:00
|
|
|
// ------------- Memory instructions.
|
2010-02-04 20:36:58 +00:00
|
|
|
case LB:
|
2011-03-28 13:05:36 +00:00
|
|
|
case LH:
|
|
|
|
case LWL:
|
2010-02-04 20:36:58 +00:00
|
|
|
case LW:
|
|
|
|
case LBU:
|
2011-03-28 13:05:36 +00:00
|
|
|
case LHU:
|
|
|
|
case LWR:
|
2010-02-04 20:36:58 +00:00
|
|
|
set_register(rt_reg, alu_out);
|
|
|
|
break;
|
|
|
|
case SB:
|
|
|
|
WriteB(addr, static_cast<int8_t>(rt));
|
|
|
|
break;
|
2011-03-28 13:05:36 +00:00
|
|
|
case SH:
|
|
|
|
WriteH(addr, static_cast<uint16_t>(rt), instr);
|
|
|
|
break;
|
|
|
|
case SWL:
|
|
|
|
WriteW(addr, mem_value, instr);
|
|
|
|
break;
|
2010-02-04 20:36:58 +00:00
|
|
|
case SW:
|
|
|
|
WriteW(addr, rt, instr);
|
|
|
|
break;
|
2011-03-28 13:05:36 +00:00
|
|
|
case SWR:
|
|
|
|
WriteW(addr, mem_value, instr);
|
|
|
|
break;
|
2010-02-04 20:36:58 +00:00
|
|
|
case LWC1:
|
|
|
|
set_fpu_register(ft_reg, alu_out);
|
|
|
|
break;
|
|
|
|
case LDC1:
|
|
|
|
set_fpu_register_double(ft_reg, fp_out);
|
|
|
|
break;
|
|
|
|
case SWC1:
|
|
|
|
addr = rs + se_imm16;
|
|
|
|
WriteW(addr, get_fpu_register(ft_reg), instr);
|
|
|
|
break;
|
|
|
|
case SDC1:
|
|
|
|
addr = rs + se_imm16;
|
2011-03-28 13:05:36 +00:00
|
|
|
WriteD(addr, get_fpu_register_double(ft_reg), instr);
|
2010-02-04 20:36:58 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
if (execute_branch_delay_instruction) {
|
|
|
|
// Execute branch delay slot
|
|
|
|
// We don't check for end_sim_pc. First it should not be met as the current
|
|
|
|
// pc is valid. Secondly a jump should always execute its branch delay slot.
|
|
|
|
Instruction* branch_delay_instr =
|
2011-03-28 13:05:36 +00:00
|
|
|
reinterpret_cast<Instruction*>(current_pc+Instruction::kInstrSize);
|
2010-02-04 20:36:58 +00:00
|
|
|
BranchDelayInstructionDecode(branch_delay_instr);
|
|
|
|
}
|
|
|
|
|
|
|
|
// If needed update pc after the branch delay execution.
|
|
|
|
if (next_pc != bad_ra) {
|
|
|
|
set_pc(next_pc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
|
2012-01-16 12:38:59 +00:00
|
|
|
// Type 3: instructions using a 26 bytes immediate. (e.g. j, jal).
|
2010-02-04 20:36:58 +00:00
|
|
|
void Simulator::DecodeTypeJump(Instruction* instr) {
|
|
|
|
// Get current pc.
|
|
|
|
int32_t current_pc = get_pc();
|
|
|
|
// Get unchanged bits of pc.
|
|
|
|
int32_t pc_high_bits = current_pc & 0xf0000000;
|
2011-05-09 14:28:09 +00:00
|
|
|
// Next pc.
|
2011-03-28 13:05:36 +00:00
|
|
|
int32_t next_pc = pc_high_bits | (instr->Imm26Value() << 2);
|
2010-02-04 20:36:58 +00:00
|
|
|
|
2011-05-09 14:28:09 +00:00
|
|
|
// Execute branch delay slot.
|
2010-02-04 20:36:58 +00:00
|
|
|
// We don't check for end_sim_pc. First it should not be met as the current pc
|
|
|
|
// is valid. Secondly a jump should always execute its branch delay slot.
|
|
|
|
Instruction* branch_delay_instr =
|
2011-05-09 14:28:09 +00:00
|
|
|
reinterpret_cast<Instruction*>(current_pc + Instruction::kInstrSize);
|
2010-02-04 20:36:58 +00:00
|
|
|
BranchDelayInstructionDecode(branch_delay_instr);
|
|
|
|
|
|
|
|
// Update pc and ra if necessary.
|
|
|
|
// Do this after the branch delay execution.
|
|
|
|
if (instr->IsLinkingInstruction()) {
|
2011-05-09 14:28:09 +00:00
|
|
|
set_register(31, current_pc + 2 * Instruction::kInstrSize);
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
set_pc(next_pc);
|
|
|
|
pc_modified_ = true;
|
|
|
|
}
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
|
2010-02-04 20:36:58 +00:00
|
|
|
// Executes the current instruction.
|
|
|
|
void Simulator::InstructionDecode(Instruction* instr) {
|
2011-03-28 13:05:36 +00:00
|
|
|
if (v8::internal::FLAG_check_icache) {
|
|
|
|
CheckICache(isolate_->simulator_i_cache(), instr);
|
|
|
|
}
|
2010-02-04 20:36:58 +00:00
|
|
|
pc_modified_ = false;
|
|
|
|
if (::v8::internal::FLAG_trace_sim) {
|
|
|
|
disasm::NameConverter converter;
|
|
|
|
disasm::Disassembler dasm(converter);
|
2011-05-09 14:28:09 +00:00
|
|
|
// Use a reasonably large buffer.
|
2010-02-04 20:36:58 +00:00
|
|
|
v8::internal::EmbeddedVector<char, 256> buffer;
|
2011-05-09 14:28:09 +00:00
|
|
|
dasm.InstructionDecode(buffer, reinterpret_cast<byte*>(instr));
|
2011-03-28 13:05:36 +00:00
|
|
|
PrintF(" 0x%08x %s\n", reinterpret_cast<intptr_t>(instr),
|
2011-05-09 14:28:09 +00:00
|
|
|
buffer.start());
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
switch (instr->InstructionType()) {
|
|
|
|
case Instruction::kRegisterType:
|
|
|
|
DecodeTypeRegister(instr);
|
|
|
|
break;
|
|
|
|
case Instruction::kImmediateType:
|
|
|
|
DecodeTypeImmediate(instr);
|
|
|
|
break;
|
|
|
|
case Instruction::kJumpType:
|
|
|
|
DecodeTypeJump(instr);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNSUPPORTED();
|
|
|
|
}
|
|
|
|
if (!pc_modified_) {
|
|
|
|
set_register(pc, reinterpret_cast<int32_t>(instr) +
|
2011-03-28 13:05:36 +00:00
|
|
|
Instruction::kInstrSize);
|
2010-02-04 20:36:58 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
void Simulator::Execute() {
|
|
|
|
// Get the PC to simulate. Cannot use the accessor here as we need the
|
|
|
|
// raw PC value and not the one used as input to arithmetic instructions.
|
|
|
|
int program_counter = get_pc();
|
|
|
|
if (::v8::internal::FLAG_stop_sim_at == 0) {
|
|
|
|
// Fast version of the dispatch loop without checking whether the simulator
|
|
|
|
// should be stopping at a particular executed instruction.
|
|
|
|
while (program_counter != end_sim_pc) {
|
|
|
|
Instruction* instr = reinterpret_cast<Instruction*>(program_counter);
|
|
|
|
icount_++;
|
|
|
|
InstructionDecode(instr);
|
|
|
|
program_counter = get_pc();
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
// FLAG_stop_sim_at is at the non-default value. Stop in the debugger when
|
|
|
|
// we reach the particular instuction count.
|
|
|
|
while (program_counter != end_sim_pc) {
|
|
|
|
Instruction* instr = reinterpret_cast<Instruction*>(program_counter);
|
|
|
|
icount_++;
|
|
|
|
if (icount_ == ::v8::internal::FLAG_stop_sim_at) {
|
2011-03-28 13:05:36 +00:00
|
|
|
MipsDebugger dbg(this);
|
2010-02-04 20:36:58 +00:00
|
|
|
dbg.Debug();
|
|
|
|
} else {
|
|
|
|
InstructionDecode(instr);
|
|
|
|
}
|
|
|
|
program_counter = get_pc();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2012-11-29 09:22:08 +00:00
|
|
|
void Simulator::CallInternal(byte* entry) {
|
2011-05-09 14:28:09 +00:00
|
|
|
// Prepare to execute the code at entry.
|
2010-02-04 20:36:58 +00:00
|
|
|
set_register(pc, reinterpret_cast<int32_t>(entry));
|
|
|
|
// Put down marker for end of simulation. The simulator will stop simulation
|
|
|
|
// when the PC reaches this value. By saving the "end simulation" value into
|
|
|
|
// the LR the simulation stops when returning to this call point.
|
|
|
|
set_register(ra, end_sim_pc);
|
|
|
|
|
|
|
|
// Remember the values of callee-saved registers.
|
|
|
|
// The code below assumes that r9 is not used as sb (static base) in
|
|
|
|
// simulator code and therefore is regarded as a callee-saved register.
|
|
|
|
int32_t s0_val = get_register(s0);
|
|
|
|
int32_t s1_val = get_register(s1);
|
|
|
|
int32_t s2_val = get_register(s2);
|
|
|
|
int32_t s3_val = get_register(s3);
|
|
|
|
int32_t s4_val = get_register(s4);
|
|
|
|
int32_t s5_val = get_register(s5);
|
|
|
|
int32_t s6_val = get_register(s6);
|
|
|
|
int32_t s7_val = get_register(s7);
|
|
|
|
int32_t gp_val = get_register(gp);
|
|
|
|
int32_t sp_val = get_register(sp);
|
|
|
|
int32_t fp_val = get_register(fp);
|
|
|
|
|
2012-01-13 13:09:52 +00:00
|
|
|
// Set up the callee-saved registers with a known value. To be able to check
|
2010-02-04 20:36:58 +00:00
|
|
|
// that they are preserved properly across JS execution.
|
|
|
|
int32_t callee_saved_value = icount_;
|
|
|
|
set_register(s0, callee_saved_value);
|
|
|
|
set_register(s1, callee_saved_value);
|
|
|
|
set_register(s2, callee_saved_value);
|
|
|
|
set_register(s3, callee_saved_value);
|
|
|
|
set_register(s4, callee_saved_value);
|
|
|
|
set_register(s5, callee_saved_value);
|
|
|
|
set_register(s6, callee_saved_value);
|
|
|
|
set_register(s7, callee_saved_value);
|
|
|
|
set_register(gp, callee_saved_value);
|
|
|
|
set_register(fp, callee_saved_value);
|
|
|
|
|
2011-05-09 14:28:09 +00:00
|
|
|
// Start the simulation.
|
2010-02-04 20:36:58 +00:00
|
|
|
Execute();
|
|
|
|
|
|
|
|
// Check that the callee-saved registers have been preserved.
|
|
|
|
CHECK_EQ(callee_saved_value, get_register(s0));
|
|
|
|
CHECK_EQ(callee_saved_value, get_register(s1));
|
|
|
|
CHECK_EQ(callee_saved_value, get_register(s2));
|
|
|
|
CHECK_EQ(callee_saved_value, get_register(s3));
|
|
|
|
CHECK_EQ(callee_saved_value, get_register(s4));
|
|
|
|
CHECK_EQ(callee_saved_value, get_register(s5));
|
|
|
|
CHECK_EQ(callee_saved_value, get_register(s6));
|
|
|
|
CHECK_EQ(callee_saved_value, get_register(s7));
|
|
|
|
CHECK_EQ(callee_saved_value, get_register(gp));
|
|
|
|
CHECK_EQ(callee_saved_value, get_register(fp));
|
|
|
|
|
|
|
|
// Restore callee-saved registers with the original value.
|
|
|
|
set_register(s0, s0_val);
|
|
|
|
set_register(s1, s1_val);
|
|
|
|
set_register(s2, s2_val);
|
|
|
|
set_register(s3, s3_val);
|
|
|
|
set_register(s4, s4_val);
|
|
|
|
set_register(s5, s5_val);
|
|
|
|
set_register(s6, s6_val);
|
|
|
|
set_register(s7, s7_val);
|
|
|
|
set_register(gp, gp_val);
|
|
|
|
set_register(sp, sp_val);
|
|
|
|
set_register(fp, fp_val);
|
2012-11-29 09:22:08 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
int32_t Simulator::Call(byte* entry, int argument_count, ...) {
|
|
|
|
va_list parameters;
|
|
|
|
va_start(parameters, argument_count);
|
|
|
|
// Set up arguments.
|
|
|
|
|
|
|
|
// First four arguments passed in registers.
|
|
|
|
ASSERT(argument_count >= 4);
|
|
|
|
set_register(a0, va_arg(parameters, int32_t));
|
|
|
|
set_register(a1, va_arg(parameters, int32_t));
|
|
|
|
set_register(a2, va_arg(parameters, int32_t));
|
|
|
|
set_register(a3, va_arg(parameters, int32_t));
|
|
|
|
|
|
|
|
// Remaining arguments passed on stack.
|
|
|
|
int original_stack = get_register(sp);
|
|
|
|
// Compute position of stack on entry to generated code.
|
|
|
|
int entry_stack = (original_stack - (argument_count - 4) * sizeof(int32_t)
|
|
|
|
- kCArgsSlotsSize);
|
|
|
|
if (OS::ActivationFrameAlignment() != 0) {
|
|
|
|
entry_stack &= -OS::ActivationFrameAlignment();
|
|
|
|
}
|
|
|
|
// Store remaining arguments on stack, from low to high memory.
|
|
|
|
intptr_t* stack_argument = reinterpret_cast<intptr_t*>(entry_stack);
|
|
|
|
for (int i = 4; i < argument_count; i++) {
|
|
|
|
stack_argument[i - 4 + kCArgSlotCount] = va_arg(parameters, int32_t);
|
|
|
|
}
|
|
|
|
va_end(parameters);
|
|
|
|
set_register(sp, entry_stack);
|
|
|
|
|
|
|
|
CallInternal(entry);
|
2010-02-04 20:36:58 +00:00
|
|
|
|
|
|
|
// Pop stack passed arguments.
|
|
|
|
CHECK_EQ(entry_stack, get_register(sp));
|
|
|
|
set_register(sp, original_stack);
|
|
|
|
|
|
|
|
int32_t result = get_register(v0);
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2012-11-29 09:22:08 +00:00
|
|
|
double Simulator::CallFP(byte* entry, double d0, double d1) {
|
|
|
|
if (!IsMipsSoftFloatABI) {
|
|
|
|
set_fpu_register_double(f12, d0);
|
|
|
|
set_fpu_register_double(f14, d1);
|
|
|
|
} else {
|
|
|
|
int buffer[2];
|
|
|
|
ASSERT(sizeof(buffer[0]) * 2 == sizeof(d0));
|
2013-04-16 12:30:51 +00:00
|
|
|
OS::MemCopy(buffer, &d0, sizeof(d0));
|
2012-11-29 09:22:08 +00:00
|
|
|
set_dw_register(a0, buffer);
|
2013-04-16 12:30:51 +00:00
|
|
|
OS::MemCopy(buffer, &d1, sizeof(d1));
|
2012-11-29 09:22:08 +00:00
|
|
|
set_dw_register(a2, buffer);
|
|
|
|
}
|
|
|
|
CallInternal(entry);
|
|
|
|
if (!IsMipsSoftFloatABI) {
|
|
|
|
return get_fpu_register_double(f0);
|
|
|
|
} else {
|
|
|
|
return get_double_from_register_pair(v0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-02-04 20:36:58 +00:00
|
|
|
uintptr_t Simulator::PushAddress(uintptr_t address) {
|
|
|
|
int new_sp = get_register(sp) - sizeof(uintptr_t);
|
|
|
|
uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(new_sp);
|
|
|
|
*stack_slot = address;
|
|
|
|
set_register(sp, new_sp);
|
|
|
|
return new_sp;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
uintptr_t Simulator::PopAddress() {
|
|
|
|
int current_sp = get_register(sp);
|
|
|
|
uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp);
|
|
|
|
uintptr_t address = *stack_slot;
|
|
|
|
set_register(sp, current_sp + sizeof(uintptr_t));
|
|
|
|
return address;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#undef UNSUPPORTED
|
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
} } // namespace v8::internal
|
2010-02-04 20:36:58 +00:00
|
|
|
|
2011-03-28 13:05:36 +00:00
|
|
|
#endif // USE_SIMULATOR
|
2010-02-04 20:36:58 +00:00
|
|
|
|
2010-05-17 15:41:35 +00:00
|
|
|
#endif // V8_TARGET_ARCH_MIPS
|