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v8/test/cctest/test-disasm-arm.cc

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ARM: Add support load/store multiple VFP registers Enter/exit frames with save doubles use these instructions instead of generating 16 load/store instructions. R=karlklose@chromium.org, rodolph.perfetta@gmail.com BUG= TEST= Review URL: http://codereview.chromium.org//6691057 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7509 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-04-06 09:06:23 +00:00
// Copyright 2011 the V8 project authors. All rights reserved.
Included mjsunit JavaScript test suite and C++ unit tests. In the shell sample don't print the result of executing a script, only evaluating expressions. Fixed issue when building samples on Windows using a shared V8 library. Added visibility option on Linux build which makes the generated library 18% smaller. Changed build system to accept multiple build modes in one build and generate seperate objects, libraries and executables for each mode. Removed deferred negation optimization (a * -b => -(a * b)) since this visibly changes operand conversion order. Improved parsing performance by introducing stack guard in preparsing. Without a stack guard preparsing always bails out with stack overflow. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-08-22 13:33:59 +00:00
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
// * Neither the name of Google Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
#include <stdlib.h>
[arm] Fix SplitAddImmediate test on Armv6. The movw/movt instructions are only available since Armv7. One of the disassembly tests was expecting these instructions when, on Armv6, we generate a load literal. Change-Id: I2b11894b5de748fc185f341b0cd49fa518d005e5 Reviewed-on: https://chromium-review.googlesource.com/978143 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#52738}
2018-04-23 15:44:01 +00:00
// The C++ style guide recommends using <re2> instead of <regex>. However, the
// former isn't available in V8.
#include <regex> // NOLINT(build/c++11)
[iwyu|arm] Pre-work for removing unallowed include macro-assembler.h -> assembler-inl.h The x64 side is included in https://chromium-review.googlesource.com/c/444226/ BUG=v8:5294 Change-Id: Ie255604c5e38c72e3c2b76e1ca3557a5fde108ee Reviewed-on: https://chromium-review.googlesource.com/446394 Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Reviewed-by: Yang Guo <yangguo@chromium.org> Commit-Queue: Marja Hölttä <marja@chromium.org> Cr-Commit-Position: refs/heads/master@{#43481}
2017-02-28 12:27:32 +00:00
#include "src/assembler-inl.h"
Rename src/float.h to src/boxed-float.h Apparently the name float.h causes problems on Windows when V8 is compiled with Visual Studio, see the bug description. R=clemensh@chromium.org Bug: v8:6588 Change-Id: Iaa9c1e93e62509a779f1a8ddecbb03a53981cf8a Reviewed-on: https://chromium-review.googlesource.com/578029 Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Reviewed-by: Clemens Hammacher <clemensh@chromium.org> Commit-Queue: Andreas Haas <ahaas@chromium.org> Cr-Commit-Position: refs/heads/master@{#46791}
2017-07-20 09:41:09 +00:00
#include "src/boxed-float.h"
Debugger: move implementation to a separate folder. R=cbruni@chromium.org Review URL: https://codereview.chromium.org/1265923002 Cr-Commit-Position: refs/heads/master@{#29951}
2015-07-31 11:07:50 +00:00
#include "src/debug/debug.h"
Use full include paths everywhere - this avoids using relative include paths which are forbidden by the style guide - makes the code more readable since it's clear which header is meant - allows for starting to use checkdeps BUG=none R=jkummerow@chromium.org, danno@chromium.org LOG=n Review URL: https://codereview.chromium.org/304153016 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21625 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-06-03 08:12:43 +00:00
#include "src/disasm.h"
#include "src/disassembler.h"
[arm][turbofan] Pass double immediate to vmov as uint64_t On x86, signalling NaNs get converted to quiet NaNs when they get push on the stack and popped again. This happens in the code generation for arm, specifically for the vmov instruction with the immediate parameter. This CL replaces the vmov function in assembler-arm to take the immediate as a uint64_t instead of a double, to guarantee that the bit pattern does not change even if the parameter is a signalling NaN. BUG=v8:6564 Change-Id: I062559f9a7ba8b0f560628e5c39621ca578c3e7d Reviewed-on: https://chromium-review.googlesource.com/558964 Commit-Queue: Andreas Haas <ahaas@chromium.org> Reviewed-by: Ben Titzer <titzer@chromium.org> Reviewed-by: Martyn Capewell <martyn.capewell@arm.com> Cr-Commit-Position: refs/heads/master@{#46418}
2017-07-05 13:48:12 +00:00
#include "src/double.h"
[iwyu] Do not include frames.h in macro assemblers. Since frames.h no longer defines basic register types like RegList, it is no longer necessary to include it in the macro assemblers. Next step: split out frame-constants.h from frames.h so that it will be possible to get frame constants without include the stackwalking logic, which needs objects.h. R=mstarzinger@chromium.org Bug: Change-Id: Ia12d3c8a8d46a73106c3c90bcb4b470c85f1eaa7 Reviewed-on: https://chromium-review.googlesource.com/597788 Commit-Queue: Ben Titzer <titzer@chromium.org> Reviewed-by: Yang Guo <yangguo@chromium.org> Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#47114}
2017-08-02 13:15:04 +00:00
#include "src/frames-inl.h"
Use full include paths everywhere - this avoids using relative include paths which are forbidden by the style guide - makes the code more readable since it's clear which header is meant - allows for starting to use checkdeps BUG=none R=jkummerow@chromium.org, danno@chromium.org LOG=n Review URL: https://codereview.chromium.org/304153016 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21625 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-06-03 08:12:43 +00:00
#include "src/macro-assembler.h"
[iwyu|arm] Pre-work for removing unallowed include macro-assembler.h -> assembler-inl.h The x64 side is included in https://chromium-review.googlesource.com/c/444226/ BUG=v8:5294 Change-Id: Ie255604c5e38c72e3c2b76e1ca3557a5fde108ee Reviewed-on: https://chromium-review.googlesource.com/446394 Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Reviewed-by: Yang Guo <yangguo@chromium.org> Commit-Queue: Marja Hölttä <marja@chromium.org> Cr-Commit-Position: refs/heads/master@{#43481}
2017-02-28 12:27:32 +00:00
#include "src/objects-inl.h"
#include "src/v8.h"
Use full include paths everywhere - this avoids using relative include paths which are forbidden by the style guide - makes the code more readable since it's clear which header is meant - allows for starting to use checkdeps BUG=none R=jkummerow@chromium.org, danno@chromium.org LOG=n Review URL: https://codereview.chromium.org/304153016 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21625 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-06-03 08:12:43 +00:00
#include "test/cctest/cctest.h"
Included mjsunit JavaScript test suite and C++ unit tests. In the shell sample don't print the result of executing a script, only evaluating expressions. Fixed issue when building samples on Windows using a shared V8 library. Added visibility option on Linux build which makes the generated library 18% smaller. Changed build system to accept multiple build modes in one build and generate seperate objects, libraries and executables for each mode. Removed deferred negation optimization (a * -b => -(a * b)) since this visibly changes operand conversion order. Improved parsing performance by introducing stack guard in preparsing. Without a stack guard preparsing always bails out with stack overflow. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-08-22 13:33:59 +00:00
[cctest] Avoid disallowed "using namespace" directive. R=jkummerow@chromium.org Change-Id: I8937933e9ec5b4bd150f5a044700716db458f365 Reviewed-on: https://chromium-review.googlesource.com/645691 Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#47758}
2017-08-31 12:34:55 +00:00
namespace v8 {
namespace internal {
Included mjsunit JavaScript test suite and C++ unit tests. In the shell sample don't print the result of executing a script, only evaluating expressions. Fixed issue when building samples on Windows using a shared V8 library. Added visibility option on Linux build which makes the generated library 18% smaller. Changed build system to accept multiple build modes in one build and generate seperate objects, libraries and executables for each mode. Removed deferred negation optimization (a * -b => -(a * b)) since this visibly changes operand conversion order. Improved parsing performance by introducing stack guard in preparsing. Without a stack guard preparsing always bails out with stack overflow. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-08-22 13:33:59 +00:00
[arm] Fix SplitAddImmediate test on Armv6. The movw/movt instructions are only available since Armv7. One of the disassembly tests was expecting these instructions when, on Armv6, we generate a load literal. Change-Id: I2b11894b5de748fc185f341b0cd49fa518d005e5 Reviewed-on: https://chromium-review.googlesource.com/978143 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#52738}
2018-04-23 15:44:01 +00:00
enum UseRegex { kRawString, kRegexString };
[arm] Introduce UseScratchRegisterScope Introduce a stripped down version of UseScratchRegisterScope for ARM and use it inside the assembler and macro-assembler. At the exception of the Call instructions, we now use this scope instead of using the ip register directly. This is inspired from how the ARM64 backend works. In general, the benefit of doing this is we can catch cases where ip is being used both by the caller and by the assembler. But more specifically, TurboFan reserves r9 as an extra scratch register because ip can already be used by the assembler. With this utility, we can isolate the cases in the code generator which need an extra register and potentially fix them, allowing us to give r9 back to the register allocator. This patch uncovered places in the assembler where we were using ip unconditionally when we could have re-used the destination register instead. Bug: v8:6553 Change-Id: Ib7134e3ed64dd1f90baf209ae831ed8f644cac78 Reviewed-on: https://chromium-review.googlesource.com/544956 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Cr-Commit-Position: refs/heads/master@{#46425}
2017-06-22 10:00:56 +00:00
template <typename... S>
[arm] Fix SplitAddImmediate test on Armv6. The movw/movt instructions are only available since Armv7. One of the disassembly tests was expecting these instructions when, on Armv6, we generate a load literal. Change-Id: I2b11894b5de748fc185f341b0cd49fa518d005e5 Reviewed-on: https://chromium-review.googlesource.com/978143 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#52738}
2018-04-23 15:44:01 +00:00
bool DisassembleAndCompare(byte* begin, UseRegex use_regex,
S... expected_strings) {
Backport the changes from the readability review. Review URL: http://codereview.chromium.org/8939 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@700 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-11-05 19:18:10 +00:00
disasm::NameConverter converter;
disasm::Disassembler disasm(converter);
[arm] Introduce UseScratchRegisterScope Introduce a stripped down version of UseScratchRegisterScope for ARM and use it inside the assembler and macro-assembler. At the exception of the Call instructions, we now use this scope instead of using the ip register directly. This is inspired from how the ARM64 backend works. In general, the benefit of doing this is we can catch cases where ip is being used both by the caller and by the assembler. But more specifically, TurboFan reserves r9 as an extra scratch register because ip can already be used by the assembler. With this utility, we can isolate the cases in the code generator which need an extra register and potentially fix them, allowing us to give r9 back to the register allocator. This patch uncovered places in the assembler where we were using ip unconditionally when we could have re-used the destination register instead. Bug: v8:6553 Change-Id: Ib7134e3ed64dd1f90baf209ae831ed8f644cac78 Reviewed-on: https://chromium-review.googlesource.com/544956 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Cr-Commit-Position: refs/heads/master@{#46425}
2017-06-22 10:00:56 +00:00
EmbeddedVector<char, 128> buffer;
std::vector<std::string> expected_disassembly = {expected_strings...};
size_t n_expected = expected_disassembly.size();
[cleanup] Unify naming of instruction size constant The instruction size in bytes is now kInstrSize on all platforms. Bug: v8:6666 Change-Id: I2f9880a6a74199a439c8327a4117efb74240aa22 Reviewed-on: https://chromium-review.googlesource.com/1164955 Commit-Queue: Sigurd Schneider <sigurds@chromium.org> Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Reviewed-by: Georg Neis <neis@chromium.org> Cr-Commit-Position: refs/heads/master@{#54944}
2018-08-07 11:31:32 +00:00
byte* end = begin + (n_expected * kInstrSize);
[arm] Introduce UseScratchRegisterScope Introduce a stripped down version of UseScratchRegisterScope for ARM and use it inside the assembler and macro-assembler. At the exception of the Call instructions, we now use this scope instead of using the ip register directly. This is inspired from how the ARM64 backend works. In general, the benefit of doing this is we can catch cases where ip is being used both by the caller and by the assembler. But more specifically, TurboFan reserves r9 as an extra scratch register because ip can already be used by the assembler. With this utility, we can isolate the cases in the code generator which need an extra register and potentially fix them, allowing us to give r9 back to the register allocator. This patch uncovered places in the assembler where we were using ip unconditionally when we could have re-used the destination register instead. Bug: v8:6553 Change-Id: Ib7134e3ed64dd1f90baf209ae831ed8f644cac78 Reviewed-on: https://chromium-review.googlesource.com/544956 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Cr-Commit-Position: refs/heads/master@{#46425}
2017-06-22 10:00:56 +00:00
std::vector<std::string> disassembly;
for (byte* pc = begin; pc < end;) {
pc += disasm.InstructionDecode(buffer, pc);
disassembly.emplace_back(buffer.start());
Included mjsunit JavaScript test suite and C++ unit tests. In the shell sample don't print the result of executing a script, only evaluating expressions. Fixed issue when building samples on Windows using a shared V8 library. Added visibility option on Linux build which makes the generated library 18% smaller. Changed build system to accept multiple build modes in one build and generate seperate objects, libraries and executables for each mode. Removed deferred negation optimization (a * -b => -(a * b)) since this visibly changes operand conversion order. Improved parsing performance by introducing stack guard in preparsing. Without a stack guard preparsing always bails out with stack overflow. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-08-22 13:33:59 +00:00
}
[arm] Introduce UseScratchRegisterScope Introduce a stripped down version of UseScratchRegisterScope for ARM and use it inside the assembler and macro-assembler. At the exception of the Call instructions, we now use this scope instead of using the ip register directly. This is inspired from how the ARM64 backend works. In general, the benefit of doing this is we can catch cases where ip is being used both by the caller and by the assembler. But more specifically, TurboFan reserves r9 as an extra scratch register because ip can already be used by the assembler. With this utility, we can isolate the cases in the code generator which need an extra register and potentially fix them, allowing us to give r9 back to the register allocator. This patch uncovered places in the assembler where we were using ip unconditionally when we could have re-used the destination register instead. Bug: v8:6553 Change-Id: Ib7134e3ed64dd1f90baf209ae831ed8f644cac78 Reviewed-on: https://chromium-review.googlesource.com/544956 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Cr-Commit-Position: refs/heads/master@{#46425}
2017-06-22 10:00:56 +00:00
bool test_passed = true;
for (size_t i = 0; i < disassembly.size(); i++) {
[arm] Fix SplitAddImmediate test on Armv6. The movw/movt instructions are only available since Armv7. One of the disassembly tests was expecting these instructions when, on Armv6, we generate a load literal. Change-Id: I2b11894b5de748fc185f341b0cd49fa518d005e5 Reviewed-on: https://chromium-review.googlesource.com/978143 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#52738}
2018-04-23 15:44:01 +00:00
if (use_regex == kRawString) {
if (expected_disassembly[i] != disassembly[i]) {
fprintf(stderr,
"expected: \n"
"%s\n"
"disassembled: \n"
"%s\n\n",
expected_disassembly[i].c_str(), disassembly[i].c_str());
test_passed = false;
}
} else {
DCHECK_EQ(use_regex, kRegexString);
if (!std::regex_match(disassembly[i],
std::regex(expected_disassembly[i]))) {
fprintf(stderr,
"expected (regex): \n"
"%s\n"
"disassembled: \n"
"%s\n\n",
expected_disassembly[i].c_str(), disassembly[i].c_str());
test_passed = false;
}
[arm] Introduce UseScratchRegisterScope Introduce a stripped down version of UseScratchRegisterScope for ARM and use it inside the assembler and macro-assembler. At the exception of the Call instructions, we now use this scope instead of using the ip register directly. This is inspired from how the ARM64 backend works. In general, the benefit of doing this is we can catch cases where ip is being used both by the caller and by the assembler. But more specifically, TurboFan reserves r9 as an extra scratch register because ip can already be used by the assembler. With this utility, we can isolate the cases in the code generator which need an extra register and potentially fix them, allowing us to give r9 back to the register allocator. This patch uncovered places in the assembler where we were using ip unconditionally when we could have re-used the destination register instead. Bug: v8:6553 Change-Id: Ib7134e3ed64dd1f90baf209ae831ed8f644cac78 Reviewed-on: https://chromium-review.googlesource.com/544956 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Cr-Commit-Position: refs/heads/master@{#46425}
2017-06-22 10:00:56 +00:00
}
}
[arm] Support splitting add with immediate instructions When an immediate does not fit an add instruction we use a temporary register to hold the value, using movw/movt to encode it. However, in order to remove a use of r9 in TurboFan's code generator, we need to cope with no scratch registers being available. That is to say that the destination and source registers are the same, and `ip` is not available to use. In this case, we can split an add instruction into a sequence of additions: ``` UseScratchRegisterScope temps(...); Register my_scratch = temps.Acquire(); __ add(r0, r0, Operand(0xabcd); // add r0, r0, #0xcd // add r0, r0, #0xab00 ``` As a drive-by fix, make the disassembler test fail if we expected a different number of instructions generated. Bug: v8:6553 Change-Id: Ib7fcc765d28bccafe39257f47cd73f922c5873bf Reviewed-on: https://chromium-review.googlesource.com/685014 Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Cr-Commit-Position: refs/heads/master@{#48491}
2017-10-11 12:00:21 +00:00
// Fail after printing expected disassembly if we expected a different number
// of instructions.
if (disassembly.size() != expected_disassembly.size()) {
return false;
}
[arm] Introduce UseScratchRegisterScope Introduce a stripped down version of UseScratchRegisterScope for ARM and use it inside the assembler and macro-assembler. At the exception of the Call instructions, we now use this scope instead of using the ip register directly. This is inspired from how the ARM64 backend works. In general, the benefit of doing this is we can catch cases where ip is being used both by the caller and by the assembler. But more specifically, TurboFan reserves r9 as an extra scratch register because ip can already be used by the assembler. With this utility, we can isolate the cases in the code generator which need an extra register and potentially fix them, allowing us to give r9 back to the register allocator. This patch uncovered places in the assembler where we were using ip unconditionally when we could have re-used the destination register instead. Bug: v8:6553 Change-Id: Ib7134e3ed64dd1f90baf209ae831ed8f644cac78 Reviewed-on: https://chromium-review.googlesource.com/544956 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Cr-Commit-Position: refs/heads/master@{#46425}
2017-06-22 10:00:56 +00:00
return test_passed;
}
Included mjsunit JavaScript test suite and C++ unit tests. In the shell sample don't print the result of executing a script, only evaluating expressions. Fixed issue when building samples on Windows using a shared V8 library. Added visibility option on Linux build which makes the generated library 18% smaller. Changed build system to accept multiple build modes in one build and generate seperate objects, libraries and executables for each mode. Removed deferred negation optimization (a * -b => -(a * b)) since this visibly changes operand conversion order. Improved parsing performance by introducing stack guard in preparsing. Without a stack guard preparsing always bails out with stack overflow. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-08-22 13:33:59 +00:00
Cosmetic changes ("set up" is a verb, "setup" is a noun). Review URL: http://codereview.chromium.org/9139051 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10399 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2012-01-13 13:09:52 +00:00
// Set up V8 to a state where we can at least run the assembler and
Backport the changes from the readability review. Review URL: http://codereview.chromium.org/8939 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@700 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-11-05 19:18:10 +00:00
// disassembler. Declare the variables and allocate the data structures used
// in the rest of the macros.
[asm] Remove Assembler(isolate...) constructor This completes the transition to Assembler::Options, which reduces the assemblers's dependency on isolates, and there is now only one way to create an Assembler, which is to use the options. Note that some operations on assemblers still need an isolate, such as GetCode(), and in these cases, the isolate is an additional argument to the method. R=jgruber@chromium.org CC=mstarzinger@chromium.org Change-Id: I413209d816c63a7c3640f1c226764693dcad1e7f Reviewed-on: https://chromium-review.googlesource.com/1106169 Commit-Queue: Ben Titzer <titzer@chromium.org> Reviewed-by: Jakob Gruber <jgruber@chromium.org> Cr-Commit-Position: refs/heads/master@{#53925}
2018-06-21 12:05:33 +00:00
#define SET_UP() \
CcTest::InitializeVM(); \
Isolate* isolate = CcTest::i_isolate(); \
HandleScope scope(isolate); \
byte* buffer = reinterpret_cast<byte*>(malloc(4 * 1024)); \
[turbofan] Thread through AssemblerOptions This CL surfaces AssemblerOptions to CodeAssembler::GenerateCode and to pipeline methods. To allow forward declaring AssemblerOptions, AssemblerBase::Options was moved out of the AssemblerBase class. Bug: v8:6666 Change-Id: If9fc50d3d4767bb5dd39a0c3b6e094021f4cae2b Reviewed-on: https://chromium-review.googlesource.com/1127039 Commit-Queue: Sigurd Schneider <sigurds@chromium.org> Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Reviewed-by: Jakob Gruber <jgruber@chromium.org> Cr-Commit-Position: refs/heads/master@{#54286}
2018-07-06 08:58:43 +00:00
Assembler assm(AssemblerOptions{}, buffer, 4 * 1024); \
Included mjsunit JavaScript test suite and C++ unit tests. In the shell sample don't print the result of executing a script, only evaluating expressions. Fixed issue when building samples on Windows using a shared V8 library. Added visibility option on Linux build which makes the generated library 18% smaller. Changed build system to accept multiple build modes in one build and generate seperate objects, libraries and executables for each mode. Removed deferred negation optimization (a * -b => -(a * b)) since this visibly changes operand conversion order. Improved parsing performance by introducing stack guard in preparsing. Without a stack guard preparsing always bails out with stack overflow. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-08-22 13:33:59 +00:00
bool failure = false;
Backport the changes from the readability review. Review URL: http://codereview.chromium.org/8939 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@700 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-11-05 19:18:10 +00:00
// This macro assembles one instruction using the preallocated assembler and
// disassembles the generated instruction, comparing the output to the expected
// value. If the comparison fails an error message is printed, but the test
// continues to run until the end.
[arm] Fix SplitAddImmediate test on Armv6. The movw/movt instructions are only available since Armv7. One of the disassembly tests was expecting these instructions when, on Armv6, we generate a load literal. Change-Id: I2b11894b5de748fc185f341b0cd49fa518d005e5 Reviewed-on: https://chromium-review.googlesource.com/978143 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#52738}
2018-04-23 15:44:01 +00:00
#define BASE_COMPARE(asm_, use_regex, ...) \
{ \
int pc_offset = assm.pc_offset(); \
byte* progcounter = &buffer[pc_offset]; \
assm.asm_; \
if (!DisassembleAndCompare(progcounter, use_regex, __VA_ARGS__)) { \
failure = true; \
} \
Included mjsunit JavaScript test suite and C++ unit tests. In the shell sample don't print the result of executing a script, only evaluating expressions. Fixed issue when building samples on Windows using a shared V8 library. Added visibility option on Linux build which makes the generated library 18% smaller. Changed build system to accept multiple build modes in one build and generate seperate objects, libraries and executables for each mode. Removed deferred negation optimization (a * -b => -(a * b)) since this visibly changes operand conversion order. Improved parsing performance by introducing stack guard in preparsing. Without a stack guard preparsing always bails out with stack overflow. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-08-22 13:33:59 +00:00
}
[arm] Fix SplitAddImmediate test on Armv6. The movw/movt instructions are only available since Armv7. One of the disassembly tests was expecting these instructions when, on Armv6, we generate a load literal. Change-Id: I2b11894b5de748fc185f341b0cd49fa518d005e5 Reviewed-on: https://chromium-review.googlesource.com/978143 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#52738}
2018-04-23 15:44:01 +00:00
#define COMPARE(asm_, ...) BASE_COMPARE(asm_, kRawString, __VA_ARGS__)
#define COMPARE_REGEX(asm_, ...) BASE_COMPARE(asm_, kRegexString, __VA_ARGS__)
Martyn Capewell <m.m.capewell@googlemail.com> Review URL: https://chromiumcodereview.appspot.com/10451037 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@11784 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2012-06-12 17:26:28 +00:00
// Force emission of any pending literals into a pool.
#define EMIT_PENDING_LITERALS() \
assm.CheckConstPool(true, false)
Included mjsunit JavaScript test suite and C++ unit tests. In the shell sample don't print the result of executing a script, only evaluating expressions. Fixed issue when building samples on Windows using a shared V8 library. Added visibility option on Linux build which makes the generated library 18% smaller. Changed build system to accept multiple build modes in one build and generate seperate objects, libraries and executables for each mode. Removed deferred negation optimization (a * -b => -(a * b)) since this visibly changes operand conversion order. Improved parsing performance by introducing stack guard in preparsing. Without a stack guard preparsing always bails out with stack overflow. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-08-22 13:33:59 +00:00
Backport the changes from the readability review. Review URL: http://codereview.chromium.org/8939 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@700 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-11-05 19:18:10 +00:00
// Verify that all invocations of the COMPARE macro passed successfully.
// Exit with a failure if at least one of the tests failed.
#define VERIFY_RUN() \
if (failure) { \
Included mjsunit JavaScript test suite and C++ unit tests. In the shell sample don't print the result of executing a script, only evaluating expressions. Fixed issue when building samples on Windows using a shared V8 library. Added visibility option on Linux build which makes the generated library 18% smaller. Changed build system to accept multiple build modes in one build and generate seperate objects, libraries and executables for each mode. Removed deferred negation optimization (a * -b => -(a * b)) since this visibly changes operand conversion order. Improved parsing performance by introducing stack guard in preparsing. Without a stack guard preparsing always bails out with stack overflow. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-08-22 13:33:59 +00:00
V8_Fatal(__FILE__, __LINE__, "ARM Disassembler tests failed.\n"); \
}
[turbofan] Add backend support for float32 operations. This adds the basics necessary to support float32 operations in TurboFan. The actual functionality required to detect safe float32 operations will be added based on this later. Therefore this does not affect production code except for some cleanup/refactoring. In detail, this patchset contains the following features: - Add support for float32 operations to arm, arm64, ia32 and x64 backends. - Add float32 machine operators. - Add support for float32 constants to simplified lowering. - Handle float32 representation for phis in simplified lowering. In addition, contains the following (related) cleanups: - Fix/unify naming of backend instructions. - Use AVX comparisons when available. - Extend ArchOpcodeField to 9 bits (required for arm64). - Refactor some code duplication in instruction selectors. BUG=v8:3589 LOG=n R=dcarney@chromium.org Review URL: https://codereview.chromium.org/1044793002 Cr-Commit-Position: refs/heads/master@{#27509}
2015-03-30 07:33:46 +00:00
// clang-format off
Included mjsunit JavaScript test suite and C++ unit tests. In the shell sample don't print the result of executing a script, only evaluating expressions. Fixed issue when building samples on Windows using a shared V8 library. Added visibility option on Linux build which makes the generated library 18% smaller. Changed build system to accept multiple build modes in one build and generate seperate objects, libraries and executables for each mode. Removed deferred negation optimization (a * -b => -(a * b)) since this visibly changes operand conversion order. Improved parsing performance by introducing stack guard in preparsing. Without a stack guard preparsing always bails out with stack overflow. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-08-22 13:33:59 +00:00
TEST(Type0) {
Cosmetic changes ("set up" is a verb, "setup" is a noun). Review URL: http://codereview.chromium.org/9139051 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10399 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2012-01-13 13:09:52 +00:00
SET_UP();
Included mjsunit JavaScript test suite and C++ unit tests. In the shell sample don't print the result of executing a script, only evaluating expressions. Fixed issue when building samples on Windows using a shared V8 library. Added visibility option on Linux build which makes the generated library 18% smaller. Changed build system to accept multiple build modes in one build and generate seperate objects, libraries and executables for each mode. Removed deferred negation optimization (a * -b => -(a * b)) since this visibly changes operand conversion order. Improved parsing performance by introducing stack guard in preparsing. Without a stack guard preparsing always bails out with stack overflow. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-08-22 13:33:59 +00:00
COMPARE(and_(r0, r1, Operand(r2)),
"e0010002 and r0, r1, r2");
COMPARE(and_(r1, r2, Operand(r3), LeaveCC),
"e0021003 and r1, r2, r3");
COMPARE(and_(r2, r3, Operand(r4), SetCC),
"e0132004 ands r2, r3, r4");
COMPARE(and_(r3, r4, Operand(r5), LeaveCC, eq),
"00043005 andeq r3, r4, r5");
COMPARE(eor(r4, r5, Operand(r6, LSL, 0)),
"e0254006 eor r4, r5, r6");
COMPARE(eor(r4, r5, Operand(r7, LSL, 1), SetCC),
"e0354087 eors r4, r5, r7, lsl #1");
COMPARE(eor(r4, r5, Operand(r8, LSL, 2), LeaveCC, ne),
"10254108 eorne r4, r5, r8, lsl #2");
COMPARE(eor(r4, r5, Operand(r9, LSL, 3), SetCC, cs),
"20354189 eorcss r4, r5, r9, lsl #3");
COMPARE(sub(r5, r6, Operand(r10, LSL, 31), LeaveCC, hs),
Reapply ARM root array change to reduce const pool size by using r10 to point to a list of common root objects. This time we also disable a debugger test on ARM that has never worked, but with this change sometimes crashes. Review URL: http://codereview.chromium.org/174317 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2744 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-08-24 11:57:57 +00:00
"20465f8a subcs r5, r6, r10, lsl #31");
Included mjsunit JavaScript test suite and C++ unit tests. In the shell sample don't print the result of executing a script, only evaluating expressions. Fixed issue when building samples on Windows using a shared V8 library. Added visibility option on Linux build which makes the generated library 18% smaller. Changed build system to accept multiple build modes in one build and generate seperate objects, libraries and executables for each mode. Removed deferred negation optimization (a * -b => -(a * b)) since this visibly changes operand conversion order. Improved parsing performance by introducing stack guard in preparsing. Without a stack guard preparsing always bails out with stack overflow. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-08-22 13:33:59 +00:00
COMPARE(sub(r5, r6, Operand(r10, LSL, 30), SetCC, cc),
Reapply ARM root array change to reduce const pool size by using r10 to point to a list of common root objects. This time we also disable a debugger test on ARM that has never worked, but with this change sometimes crashes. Review URL: http://codereview.chromium.org/174317 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2744 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-08-24 11:57:57 +00:00
"30565f0a subccs r5, r6, r10, lsl #30");
Included mjsunit JavaScript test suite and C++ unit tests. In the shell sample don't print the result of executing a script, only evaluating expressions. Fixed issue when building samples on Windows using a shared V8 library. Added visibility option on Linux build which makes the generated library 18% smaller. Changed build system to accept multiple build modes in one build and generate seperate objects, libraries and executables for each mode. Removed deferred negation optimization (a * -b => -(a * b)) since this visibly changes operand conversion order. Improved parsing performance by introducing stack guard in preparsing. Without a stack guard preparsing always bails out with stack overflow. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-08-22 13:33:59 +00:00
COMPARE(sub(r5, r6, Operand(r10, LSL, 24), LeaveCC, lo),
Reapply ARM root array change to reduce const pool size by using r10 to point to a list of common root objects. This time we also disable a debugger test on ARM that has never worked, but with this change sometimes crashes. Review URL: http://codereview.chromium.org/174317 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2744 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-08-24 11:57:57 +00:00
"30465c0a subcc r5, r6, r10, lsl #24");
Included mjsunit JavaScript test suite and C++ unit tests. In the shell sample don't print the result of executing a script, only evaluating expressions. Fixed issue when building samples on Windows using a shared V8 library. Added visibility option on Linux build which makes the generated library 18% smaller. Changed build system to accept multiple build modes in one build and generate seperate objects, libraries and executables for each mode. Removed deferred negation optimization (a * -b => -(a * b)) since this visibly changes operand conversion order. Improved parsing performance by introducing stack guard in preparsing. Without a stack guard preparsing always bails out with stack overflow. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-08-22 13:33:59 +00:00
COMPARE(sub(r5, r6, Operand(r10, LSL, 16), SetCC, mi),
Reapply ARM root array change to reduce const pool size by using r10 to point to a list of common root objects. This time we also disable a debugger test on ARM that has never worked, but with this change sometimes crashes. Review URL: http://codereview.chromium.org/174317 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2744 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-08-24 11:57:57 +00:00
"4056580a submis r5, r6, r10, lsl #16");
Included mjsunit JavaScript test suite and C++ unit tests. In the shell sample don't print the result of executing a script, only evaluating expressions. Fixed issue when building samples on Windows using a shared V8 library. Added visibility option on Linux build which makes the generated library 18% smaller. Changed build system to accept multiple build modes in one build and generate seperate objects, libraries and executables for each mode. Removed deferred negation optimization (a * -b => -(a * b)) since this visibly changes operand conversion order. Improved parsing performance by introducing stack guard in preparsing. Without a stack guard preparsing always bails out with stack overflow. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-08-22 13:33:59 +00:00
COMPARE(rsb(r6, r7, Operand(fp)),
"e067600b rsb r6, r7, fp");
COMPARE(rsb(r6, r7, Operand(fp, LSR, 1)),
"e06760ab rsb r6, r7, fp, lsr #1");
COMPARE(rsb(r6, r7, Operand(fp, LSR, 0), SetCC),
"e077602b rsbs r6, r7, fp, lsr #32");
COMPARE(rsb(r6, r7, Operand(fp, LSR, 31), LeaveCC, pl),
"50676fab rsbpl r6, r7, fp, lsr #31");
COMPARE(add(r7, r8, Operand(ip, ASR, 1)),
"e08870cc add r7, r8, ip, asr #1");
COMPARE(add(r7, r8, Operand(ip, ASR, 0)),
"e088704c add r7, r8, ip, asr #32");
COMPARE(add(r7, r8, Operand(ip), SetCC),
"e098700c adds r7, r8, ip");
COMPARE(add(r7, r8, Operand(ip, ASR, 31), SetCC, vs),
"60987fcc addvss r7, r8, ip, asr #31");
COMPARE(adc(r7, fp, Operand(ip, ASR, 5)),
"e0ab72cc adc r7, fp, ip, asr #5");
COMPARE(adc(r4, ip, Operand(ip, ASR, 1), LeaveCC, vc),
"70ac40cc adcvc r4, ip, ip, asr #1");
COMPARE(adc(r5, sp, Operand(ip), SetCC),
"e0bd500c adcs r5, sp, ip");
COMPARE(adc(r8, lr, Operand(ip, ASR, 31), SetCC, vc),
"70be8fcc adcvcs r8, lr, ip, asr #31");
COMPARE(sbc(r7, r1, Operand(ip, ROR, 1), LeaveCC, hi),
"80c170ec sbchi r7, r1, ip, ror #1");
COMPARE(sbc(r7, r9, Operand(ip, ROR, 4)),
"e0c9726c sbc r7, r9, ip, ror #4");
COMPARE(sbc(r7, r10, Operand(ip), SetCC),
Reapply ARM root array change to reduce const pool size by using r10 to point to a list of common root objects. This time we also disable a debugger test on ARM that has never worked, but with this change sometimes crashes. Review URL: http://codereview.chromium.org/174317 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2744 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-08-24 11:57:57 +00:00
"e0da700c sbcs r7, r10, ip");
Included mjsunit JavaScript test suite and C++ unit tests. In the shell sample don't print the result of executing a script, only evaluating expressions. Fixed issue when building samples on Windows using a shared V8 library. Added visibility option on Linux build which makes the generated library 18% smaller. Changed build system to accept multiple build modes in one build and generate seperate objects, libraries and executables for each mode. Removed deferred negation optimization (a * -b => -(a * b)) since this visibly changes operand conversion order. Improved parsing performance by introducing stack guard in preparsing. Without a stack guard preparsing always bails out with stack overflow. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-08-22 13:33:59 +00:00
COMPARE(sbc(r7, ip, Operand(ip, ROR, 31), SetCC, hi),
"80dc7fec sbchis r7, ip, ip, ror #31");
COMPARE(rsc(r7, r8, Operand(ip, LSL, r0)),
"e0e8701c rsc r7, r8, ip, lsl r0");
COMPARE(rsc(r7, r8, Operand(ip, LSL, r1)),
"e0e8711c rsc r7, r8, ip, lsl r1");
COMPARE(rsc(r7, r8, Operand(ip), SetCC),
"e0f8700c rscs r7, r8, ip");
COMPARE(rsc(r7, r8, Operand(ip, LSL, r3), SetCC, ls),
"90f8731c rsclss r7, r8, ip, lsl r3");
COMPARE(tst(r7, Operand(r5, ASR, ip), ge),
"a1170c55 tstge r7, r5, asr ip");
COMPARE(tst(r7, Operand(r6, ASR, sp)),
"e1170d56 tst r7, r6, asr sp");
COMPARE(tst(r7, Operand(r7), ge),
"a1170007 tstge r7, r7");
COMPARE(tst(r7, Operand(r8, ASR, fp), ge),
"a1170b58 tstge r7, r8, asr fp");
COMPARE(teq(r7, Operand(r5, ROR, r0), lt),
"b1370075 teqlt r7, r5, ror r0");
COMPARE(teq(r7, Operand(r6, ROR, lr)),
"e1370e76 teq r7, r6, ror lr");
COMPARE(teq(r7, Operand(r7), lt),
"b1370007 teqlt r7, r7");
COMPARE(teq(r7, Operand(r8, ROR, r1)),
"e1370178 teq r7, r8, ror r1");
COMPARE(cmp(r7, Operand(r4)),
"e1570004 cmp r7, r4");
COMPARE(cmp(r7, Operand(r6, LSL, 1), gt),
"c1570086 cmpgt r7, r6, lsl #1");
COMPARE(cmp(r7, Operand(r8, LSR, 3), gt),
"c15701a8 cmpgt r7, r8, lsr #3");
COMPARE(cmp(r7, Operand(r8, ASR, 19)),
"e15709c8 cmp r7, r8, asr #19");
COMPARE(cmn(r0, Operand(r4)),
"e1700004 cmn r0, r4");
COMPARE(cmn(r1, Operand(r6, ROR, 1)),
"e17100e6 cmn r1, r6, ror #1");
COMPARE(cmn(r2, Operand(r8)),
"e1720008 cmn r2, r8");
COMPARE(cmn(r3, Operand(fp), le),
"d173000b cmnle r3, fp");
COMPARE(orr(r7, r8, Operand(lr), LeaveCC, al),
"e188700e orr r7, r8, lr");
COMPARE(orr(r7, r8, Operand(fp)),
"e188700b orr r7, r8, fp");
COMPARE(orr(r7, r8, Operand(sp), SetCC),
"e198700d orrs r7, r8, sp");
COMPARE(orr(r7, r8, Operand(ip), SetCC, al),
"e198700c orrs r7, r8, ip");
COMPARE(mov(r0, Operand(r1), LeaveCC, eq),
"01a00001 moveq r0, r1");
COMPARE(mov(r0, Operand(r2)),
"e1a00002 mov r0, r2");
COMPARE(mov(r0, Operand(r3), SetCC),
"e1b00003 movs r0, r3");
COMPARE(mov(r0, Operand(r4), SetCC, pl),
"51b00004 movpls r0, r4");
COMPARE(bic(r0, lr, Operand(r1), LeaveCC, vs),
"61ce0001 bicvs r0, lr, r1");
COMPARE(bic(r0, r9, Operand(r2), LeaveCC, vc),
"71c90002 bicvc r0, r9, r2");
COMPARE(bic(r0, r5, Operand(r3), SetCC),
"e1d50003 bics r0, r5, r3");
COMPARE(bic(r0, r1, Operand(r4), SetCC, pl),
"51d10004 bicpls r0, r1, r4");
COMPARE(mvn(r10, Operand(r1)),
Reapply ARM root array change to reduce const pool size by using r10 to point to a list of common root objects. This time we also disable a debugger test on ARM that has never worked, but with this change sometimes crashes. Review URL: http://codereview.chromium.org/174317 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2744 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-08-24 11:57:57 +00:00
"e1e0a001 mvn r10, r1");
Included mjsunit JavaScript test suite and C++ unit tests. In the shell sample don't print the result of executing a script, only evaluating expressions. Fixed issue when building samples on Windows using a shared V8 library. Added visibility option on Linux build which makes the generated library 18% smaller. Changed build system to accept multiple build modes in one build and generate seperate objects, libraries and executables for each mode. Removed deferred negation optimization (a * -b => -(a * b)) since this visibly changes operand conversion order. Improved parsing performance by introducing stack guard in preparsing. Without a stack guard preparsing always bails out with stack overflow. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-08-22 13:33:59 +00:00
COMPARE(mvn(r9, Operand(r2)),
"e1e09002 mvn r9, r2");
COMPARE(mvn(r0, Operand(r3), SetCC),
"e1f00003 mvns r0, r3");
COMPARE(mvn(r5, Operand(r4), SetCC, cc),
"31f05004 mvnccs r5, r4");
ARM: Be more smart about switching instructions when immediates don't fit in the instruction. Use ubfx and sbfx more. Review URL: http://codereview.chromium.org/2826001 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4855 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-14 11:20:36 +00:00
// Instructions autotransformed by the assembler.
// mov -> mvn.
COMPARE(mov(r3, Operand(-1), LeaveCC, al),
"e3e03000 mvn r3, #0");
COMPARE(mov(r4, Operand(-2), SetCC, al),
"e3f04001 mvns r4, #1");
Normalize casing of hexadecimal digits This patch normalizes the casing of hexadecimal digits in escape sequences of the form `\xNN` and integer literals of the form `0xNNNN`. Previously, the V8 code base used an inconsistent mixture of uppercase and lowercase. Google’s C++ style guide uses uppercase in its examples: https://google.github.io/styleguide/cppguide.html#Non-ASCII_Characters Moreover, uppercase letters more clearly stand out from the lowercase `x` (or `u`) characters at the start, as well as lowercase letters elsewhere in strings. BUG=v8:7109 TBR=marja@chromium.org,titzer@chromium.org,mtrofin@chromium.org,mstarzinger@chromium.org,rossberg@chromium.org,yangguo@chromium.org,mlippautz@chromium.org NOPRESUBMIT=true Cq-Include-Trybots: master.tryserver.blink:linux_trusty_blink_rel;master.tryserver.chromium.linux:linux_chromium_rel_ng Change-Id: I790e21c25d96ad5d95c8229724eb45d2aa9e22d6 Reviewed-on: https://chromium-review.googlesource.com/804294 Commit-Queue: Mathias Bynens <mathias@chromium.org> Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#49810}
2017-12-02 00:30:37 +00:00
COMPARE(mov(r5, Operand(0x0FFFFFF0), SetCC, ne),
ARM: Be more smart about switching instructions when immediates don't fit in the instruction. Use ubfx and sbfx more. Review URL: http://codereview.chromium.org/2826001 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4855 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-14 11:20:36 +00:00
"13f052ff mvnnes r5, #-268435441");
COMPARE(mov(r6, Operand(-1), LeaveCC, ne),
"13e06000 mvnne r6, #0");
// mvn -> mov.
COMPARE(mvn(r3, Operand(-1), LeaveCC, al),
"e3a03000 mov r3, #0");
COMPARE(mvn(r4, Operand(-2), SetCC, al),
"e3b04001 movs r4, #1");
Normalize casing of hexadecimal digits This patch normalizes the casing of hexadecimal digits in escape sequences of the form `\xNN` and integer literals of the form `0xNNNN`. Previously, the V8 code base used an inconsistent mixture of uppercase and lowercase. Google’s C++ style guide uses uppercase in its examples: https://google.github.io/styleguide/cppguide.html#Non-ASCII_Characters Moreover, uppercase letters more clearly stand out from the lowercase `x` (or `u`) characters at the start, as well as lowercase letters elsewhere in strings. BUG=v8:7109 TBR=marja@chromium.org,titzer@chromium.org,mtrofin@chromium.org,mstarzinger@chromium.org,rossberg@chromium.org,yangguo@chromium.org,mlippautz@chromium.org NOPRESUBMIT=true Cq-Include-Trybots: master.tryserver.blink:linux_trusty_blink_rel;master.tryserver.chromium.linux:linux_chromium_rel_ng Change-Id: I790e21c25d96ad5d95c8229724eb45d2aa9e22d6 Reviewed-on: https://chromium-review.googlesource.com/804294 Commit-Queue: Mathias Bynens <mathias@chromium.org> Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#49810}
2017-12-02 00:30:37 +00:00
COMPARE(mvn(r5, Operand(0x0FFFFFF0), SetCC, ne),
ARM: Be more smart about switching instructions when immediates don't fit in the instruction. Use ubfx and sbfx more. Review URL: http://codereview.chromium.org/2826001 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4855 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-14 11:20:36 +00:00
"13b052ff movnes r5, #-268435441");
COMPARE(mvn(r6, Operand(-1), LeaveCC, ne),
"13a06000 movne r6, #0");
Add movw and movt support for ARMv7. This includes some code from Zhang Kun. For now we only emit movw and movt in places where no relocation is needed. Small performance boost (around 0.5%). Also adds support for turning ALU operations (eor etc.) with large immediates into mvn or movw followed by a register-based ALU operation. Review URL: http://codereview.chromium.org/2821014 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4913 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-22 08:38:32 +00:00
// mov -> movw.
VM initialization refactoring. This patch introduces global once per-process initialization and moves the OS and CPU setup there. This makes CPU features isolate-independent. Review URL: http://codereview.chromium.org/6670119 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7462 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-03-31 16:17:37 +00:00
if (CpuFeatures::IsSupported(ARMv7)) {
Add movw and movt support for ARMv7. This includes some code from Zhang Kun. For now we only emit movw and movt in places where no relocation is needed. Small performance boost (around 0.5%). Also adds support for turning ALU operations (eor etc.) with large immediates into mvn or movw followed by a register-based ALU operation. Review URL: http://codereview.chromium.org/2821014 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4913 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-22 08:38:32 +00:00
COMPARE(mov(r5, Operand(0x01234), LeaveCC, ne),
"13015234 movwne r5, #4660");
COMPARE(eor(r5, r4, Operand(0x1234), LeaveCC, ne),
[arm] Introduce UseScratchRegisterScope Introduce a stripped down version of UseScratchRegisterScope for ARM and use it inside the assembler and macro-assembler. At the exception of the Call instructions, we now use this scope instead of using the ip register directly. This is inspired from how the ARM64 backend works. In general, the benefit of doing this is we can catch cases where ip is being used both by the caller and by the assembler. But more specifically, TurboFan reserves r9 as an extra scratch register because ip can already be used by the assembler. With this utility, we can isolate the cases in the code generator which need an extra register and potentially fix them, allowing us to give r9 back to the register allocator. This patch uncovered places in the assembler where we were using ip unconditionally when we could have re-used the destination register instead. Bug: v8:6553 Change-Id: Ib7134e3ed64dd1f90baf209ae831ed8f644cac78 Reviewed-on: https://chromium-review.googlesource.com/544956 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Cr-Commit-Position: refs/heads/master@{#46425}
2017-06-22 10:00:56 +00:00
"13015234 movwne r5, #4660",
"10245005 eorne r5, r4, r5");
// Movw can't do setcc, so first move to r5, then the following instruction
// sets the flags. Mov immediate with setcc is pretty strange anyway.
Add movw and movt support for ARMv7. This includes some code from Zhang Kun. For now we only emit movw and movt in places where no relocation is needed. Small performance boost (around 0.5%). Also adds support for turning ALU operations (eor etc.) with large immediates into mvn or movw followed by a register-based ALU operation. Review URL: http://codereview.chromium.org/2821014 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4913 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-22 08:38:32 +00:00
COMPARE(mov(r5, Operand(0x01234), SetCC, ne),
[arm] Introduce UseScratchRegisterScope Introduce a stripped down version of UseScratchRegisterScope for ARM and use it inside the assembler and macro-assembler. At the exception of the Call instructions, we now use this scope instead of using the ip register directly. This is inspired from how the ARM64 backend works. In general, the benefit of doing this is we can catch cases where ip is being used both by the caller and by the assembler. But more specifically, TurboFan reserves r9 as an extra scratch register because ip can already be used by the assembler. With this utility, we can isolate the cases in the code generator which need an extra register and potentially fix them, allowing us to give r9 back to the register allocator. This patch uncovered places in the assembler where we were using ip unconditionally when we could have re-used the destination register instead. Bug: v8:6553 Change-Id: Ib7134e3ed64dd1f90baf209ae831ed8f644cac78 Reviewed-on: https://chromium-review.googlesource.com/544956 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Cr-Commit-Position: refs/heads/master@{#46425}
2017-06-22 10:00:56 +00:00
"13015234 movwne r5, #4660",
"11b05005 movnes r5, r5");
Martyn Capewell <m.m.capewell@googlemail.com> Review URL: https://chromiumcodereview.appspot.com/10451037 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@11784 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2012-06-12 17:26:28 +00:00
// Emit a literal pool now, otherwise this could be dumped later, in the
// middle of a different test.
EMIT_PENDING_LITERALS();
Add movw and movt support for ARMv7. This includes some code from Zhang Kun. For now we only emit movw and movt in places where no relocation is needed. Small performance boost (around 0.5%). Also adds support for turning ALU operations (eor etc.) with large immediates into mvn or movw followed by a register-based ALU operation. Review URL: http://codereview.chromium.org/2821014 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4913 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-22 08:38:32 +00:00
// The eor does the setcc so we get a movw here.
COMPARE(eor(r5, r4, Operand(0x1234), SetCC, ne),
[arm] Introduce UseScratchRegisterScope Introduce a stripped down version of UseScratchRegisterScope for ARM and use it inside the assembler and macro-assembler. At the exception of the Call instructions, we now use this scope instead of using the ip register directly. This is inspired from how the ARM64 backend works. In general, the benefit of doing this is we can catch cases where ip is being used both by the caller and by the assembler. But more specifically, TurboFan reserves r9 as an extra scratch register because ip can already be used by the assembler. With this utility, we can isolate the cases in the code generator which need an extra register and potentially fix them, allowing us to give r9 back to the register allocator. This patch uncovered places in the assembler where we were using ip unconditionally when we could have re-used the destination register instead. Bug: v8:6553 Change-Id: Ib7134e3ed64dd1f90baf209ae831ed8f644cac78 Reviewed-on: https://chromium-review.googlesource.com/544956 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Cr-Commit-Position: refs/heads/master@{#46425}
2017-06-22 10:00:56 +00:00
"13015234 movwne r5, #4660",
"10345005 eornes r5, r4, r5");
Add movw and movt support for ARMv7. This includes some code from Zhang Kun. For now we only emit movw and movt in places where no relocation is needed. Small performance boost (around 0.5%). Also adds support for turning ALU operations (eor etc.) with large immediates into mvn or movw followed by a register-based ALU operation. Review URL: http://codereview.chromium.org/2821014 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4913 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-22 08:38:32 +00:00
COMPARE(movt(r5, 0x4321, ne),
"13445321 movtne r5, #17185");
Normalize casing of hexadecimal digits This patch normalizes the casing of hexadecimal digits in escape sequences of the form `\xNN` and integer literals of the form `0xNNNN`. Previously, the V8 code base used an inconsistent mixture of uppercase and lowercase. Google’s C++ style guide uses uppercase in its examples: https://google.github.io/styleguide/cppguide.html#Non-ASCII_Characters Moreover, uppercase letters more clearly stand out from the lowercase `x` (or `u`) characters at the start, as well as lowercase letters elsewhere in strings. BUG=v8:7109 TBR=marja@chromium.org,titzer@chromium.org,mtrofin@chromium.org,mstarzinger@chromium.org,rossberg@chromium.org,yangguo@chromium.org,mlippautz@chromium.org NOPRESUBMIT=true Cq-Include-Trybots: master.tryserver.blink:linux_trusty_blink_rel;master.tryserver.chromium.linux:linux_chromium_rel_ng Change-Id: I790e21c25d96ad5d95c8229724eb45d2aa9e22d6 Reviewed-on: https://chromium-review.googlesource.com/804294 Commit-Queue: Mathias Bynens <mathias@chromium.org> Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#49810}
2017-12-02 00:30:37 +00:00
COMPARE(movw(r5, 0xABCD, eq),
Add movw and movt support for ARMv7. This includes some code from Zhang Kun. For now we only emit movw and movt in places where no relocation is needed. Small performance boost (around 0.5%). Also adds support for turning ALU operations (eor etc.) with large immediates into mvn or movw followed by a register-based ALU operation. Review URL: http://codereview.chromium.org/2821014 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4913 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-22 08:38:32 +00:00
"030a5bcd movweq r5, #43981");
}
// Eor doesn't have an eor-negative variant, but we can do an mvn followed by
// an eor to get the same effect.
Normalize casing of hexadecimal digits This patch normalizes the casing of hexadecimal digits in escape sequences of the form `\xNN` and integer literals of the form `0xNNNN`. Previously, the V8 code base used an inconsistent mixture of uppercase and lowercase. Google’s C++ style guide uses uppercase in its examples: https://google.github.io/styleguide/cppguide.html#Non-ASCII_Characters Moreover, uppercase letters more clearly stand out from the lowercase `x` (or `u`) characters at the start, as well as lowercase letters elsewhere in strings. BUG=v8:7109 TBR=marja@chromium.org,titzer@chromium.org,mtrofin@chromium.org,mstarzinger@chromium.org,rossberg@chromium.org,yangguo@chromium.org,mlippautz@chromium.org NOPRESUBMIT=true Cq-Include-Trybots: master.tryserver.blink:linux_trusty_blink_rel;master.tryserver.chromium.linux:linux_chromium_rel_ng Change-Id: I790e21c25d96ad5d95c8229724eb45d2aa9e22d6 Reviewed-on: https://chromium-review.googlesource.com/804294 Commit-Queue: Mathias Bynens <mathias@chromium.org> Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#49810}
2017-12-02 00:30:37 +00:00
COMPARE(eor(r5, r4, Operand(0xFFFFFF34), SetCC, ne),
[arm] Introduce UseScratchRegisterScope Introduce a stripped down version of UseScratchRegisterScope for ARM and use it inside the assembler and macro-assembler. At the exception of the Call instructions, we now use this scope instead of using the ip register directly. This is inspired from how the ARM64 backend works. In general, the benefit of doing this is we can catch cases where ip is being used both by the caller and by the assembler. But more specifically, TurboFan reserves r9 as an extra scratch register because ip can already be used by the assembler. With this utility, we can isolate the cases in the code generator which need an extra register and potentially fix them, allowing us to give r9 back to the register allocator. This patch uncovered places in the assembler where we were using ip unconditionally when we could have re-used the destination register instead. Bug: v8:6553 Change-Id: Ib7134e3ed64dd1f90baf209ae831ed8f644cac78 Reviewed-on: https://chromium-review.googlesource.com/544956 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Cr-Commit-Position: refs/heads/master@{#46425}
2017-06-22 10:00:56 +00:00
"13e050cb mvnne r5, #203",
"10345005 eornes r5, r4, r5");
Add movw and movt support for ARMv7. This includes some code from Zhang Kun. For now we only emit movw and movt in places where no relocation is needed. Small performance boost (around 0.5%). Also adds support for turning ALU operations (eor etc.) with large immediates into mvn or movw followed by a register-based ALU operation. Review URL: http://codereview.chromium.org/2821014 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4913 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-22 08:38:32 +00:00
ARM: Be more smart about switching instructions when immediates don't fit in the instruction. Use ubfx and sbfx more. Review URL: http://codereview.chromium.org/2826001 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4855 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-14 11:20:36 +00:00
// and <-> bic.
Normalize casing of hexadecimal digits This patch normalizes the casing of hexadecimal digits in escape sequences of the form `\xNN` and integer literals of the form `0xNNNN`. Previously, the V8 code base used an inconsistent mixture of uppercase and lowercase. Google’s C++ style guide uses uppercase in its examples: https://google.github.io/styleguide/cppguide.html#Non-ASCII_Characters Moreover, uppercase letters more clearly stand out from the lowercase `x` (or `u`) characters at the start, as well as lowercase letters elsewhere in strings. BUG=v8:7109 TBR=marja@chromium.org,titzer@chromium.org,mtrofin@chromium.org,mstarzinger@chromium.org,rossberg@chromium.org,yangguo@chromium.org,mlippautz@chromium.org NOPRESUBMIT=true Cq-Include-Trybots: master.tryserver.blink:linux_trusty_blink_rel;master.tryserver.chromium.linux:linux_chromium_rel_ng Change-Id: I790e21c25d96ad5d95c8229724eb45d2aa9e22d6 Reviewed-on: https://chromium-review.googlesource.com/804294 Commit-Queue: Mathias Bynens <mathias@chromium.org> Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#49810}
2017-12-02 00:30:37 +00:00
COMPARE(and_(r3, r5, Operand(0xFC03FFFF)),
ARM: Be more smart about switching instructions when immediates don't fit in the instruction. Use ubfx and sbfx more. Review URL: http://codereview.chromium.org/2826001 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4855 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-14 11:20:36 +00:00
"e3c537ff bic r3, r5, #66846720");
Normalize casing of hexadecimal digits This patch normalizes the casing of hexadecimal digits in escape sequences of the form `\xNN` and integer literals of the form `0xNNNN`. Previously, the V8 code base used an inconsistent mixture of uppercase and lowercase. Google’s C++ style guide uses uppercase in its examples: https://google.github.io/styleguide/cppguide.html#Non-ASCII_Characters Moreover, uppercase letters more clearly stand out from the lowercase `x` (or `u`) characters at the start, as well as lowercase letters elsewhere in strings. BUG=v8:7109 TBR=marja@chromium.org,titzer@chromium.org,mtrofin@chromium.org,mstarzinger@chromium.org,rossberg@chromium.org,yangguo@chromium.org,mlippautz@chromium.org NOPRESUBMIT=true Cq-Include-Trybots: master.tryserver.blink:linux_trusty_blink_rel;master.tryserver.chromium.linux:linux_chromium_rel_ng Change-Id: I790e21c25d96ad5d95c8229724eb45d2aa9e22d6 Reviewed-on: https://chromium-review.googlesource.com/804294 Commit-Queue: Mathias Bynens <mathias@chromium.org> Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#49810}
2017-12-02 00:30:37 +00:00
COMPARE(bic(r3, r5, Operand(0xFC03FFFF)),
ARM: Be more smart about switching instructions when immediates don't fit in the instruction. Use ubfx and sbfx more. Review URL: http://codereview.chromium.org/2826001 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4855 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-14 11:20:36 +00:00
"e20537ff and r3, r5, #66846720");
// sub <-> add.
COMPARE(add(r3, r5, Operand(-1024)),
"e2453b01 sub r3, r5, #1024");
COMPARE(sub(r3, r5, Operand(-1024)),
"e2853b01 add r3, r5, #1024");
// cmp <-> cmn.
COMPARE(cmp(r3, Operand(-1024)),
"e3730b01 cmn r3, #1024");
COMPARE(cmn(r3, Operand(-1024)),
"e3530b01 cmp r3, #1024");
Add support for bkpt instruction The bkpt instruction is now supported by both the disassembler and the simulator. In the simulator it breaks to the native debugger if any like int3 on Intel. Moved the handling of the miscellaneous instructions to a separate part. Review URL: http://codereview.chromium.org/1576026 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4360 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-04-08 13:30:48 +00:00
// Miscellaneous instructions encoded as type 0.
COMPARE(blx(ip),
"e12fff3c blx ip");
COMPARE(bkpt(0),
"e1200070 bkpt 0");
Normalize casing of hexadecimal digits This patch normalizes the casing of hexadecimal digits in escape sequences of the form `\xNN` and integer literals of the form `0xNNNN`. Previously, the V8 code base used an inconsistent mixture of uppercase and lowercase. Google’s C++ style guide uses uppercase in its examples: https://google.github.io/styleguide/cppguide.html#Non-ASCII_Characters Moreover, uppercase letters more clearly stand out from the lowercase `x` (or `u`) characters at the start, as well as lowercase letters elsewhere in strings. BUG=v8:7109 TBR=marja@chromium.org,titzer@chromium.org,mtrofin@chromium.org,mstarzinger@chromium.org,rossberg@chromium.org,yangguo@chromium.org,mlippautz@chromium.org NOPRESUBMIT=true Cq-Include-Trybots: master.tryserver.blink:linux_trusty_blink_rel;master.tryserver.chromium.linux:linux_chromium_rel_ng Change-Id: I790e21c25d96ad5d95c8229724eb45d2aa9e22d6 Reviewed-on: https://chromium-review.googlesource.com/804294 Commit-Queue: Mathias Bynens <mathias@chromium.org> Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#49810}
2017-12-02 00:30:37 +00:00
COMPARE(bkpt(0xFFFF),
Add support for bkpt instruction The bkpt instruction is now supported by both the disassembler and the simulator. In the simulator it breaks to the native debugger if any like int3 on Intel. Moved the handling of the miscellaneous instructions to a separate part. Review URL: http://codereview.chromium.org/1576026 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4360 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-04-08 13:30:48 +00:00
"e12fff7f bkpt 65535");
COMPARE(clz(r6, r7),
"e16f6f17 clz r6, r7");
Backport the changes from the readability review. Review URL: http://codereview.chromium.org/8939 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@700 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-11-05 19:18:10 +00:00
VERIFY_RUN();
Included mjsunit JavaScript test suite and C++ unit tests. In the shell sample don't print the result of executing a script, only evaluating expressions. Fixed issue when building samples on Windows using a shared V8 library. Added visibility option on Linux build which makes the generated library 18% smaller. Changed build system to accept multiple build modes in one build and generate seperate objects, libraries and executables for each mode. Removed deferred negation optimization (a * -b => -(a * b)) since this visibly changes operand conversion order. Improved parsing performance by introducing stack guard in preparsing. Without a stack guard preparsing always bails out with stack overflow. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-08-22 13:33:59 +00:00
}
TEST(Type1) {
Cosmetic changes ("set up" is a verb, "setup" is a noun). Review URL: http://codereview.chromium.org/9139051 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10399 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2012-01-13 13:09:52 +00:00
SET_UP();
Included mjsunit JavaScript test suite and C++ unit tests. In the shell sample don't print the result of executing a script, only evaluating expressions. Fixed issue when building samples on Windows using a shared V8 library. Added visibility option on Linux build which makes the generated library 18% smaller. Changed build system to accept multiple build modes in one build and generate seperate objects, libraries and executables for each mode. Removed deferred negation optimization (a * -b => -(a * b)) since this visibly changes operand conversion order. Improved parsing performance by introducing stack guard in preparsing. Without a stack guard preparsing always bails out with stack overflow. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-08-22 13:33:59 +00:00
COMPARE(and_(r0, r1, Operand(0x00000000)),
"e2010000 and r0, r1, #0");
COMPARE(and_(r1, r2, Operand(0x00000001), LeaveCC),
"e2021001 and r1, r2, #1");
COMPARE(and_(r2, r3, Operand(0x00000010), SetCC),
"e2132010 ands r2, r3, #16");
COMPARE(and_(r3, r4, Operand(0x00000100), LeaveCC, eq),
"02043c01 andeq r3, r4, #256");
COMPARE(and_(r4, r5, Operand(0x00001000), SetCC, ne),
"12154a01 andnes r4, r5, #4096");
COMPARE(eor(r4, r5, Operand(0x00001000)),
"e2254a01 eor r4, r5, #4096");
COMPARE(eor(r4, r4, Operand(0x00010000), LeaveCC),
"e2244801 eor r4, r4, #65536");
COMPARE(eor(r4, r3, Operand(0x00100000), SetCC),
"e2334601 eors r4, r3, #1048576");
COMPARE(eor(r4, r2, Operand(0x01000000), LeaveCC, cs),
"22224401 eorcs r4, r2, #16777216");
COMPARE(eor(r4, r1, Operand(0x10000000), SetCC, cc),
"32314201 eorccs r4, r1, #268435456");
Backport the changes from the readability review. Review URL: http://codereview.chromium.org/8939 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@700 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-11-05 19:18:10 +00:00
VERIFY_RUN();
Included mjsunit JavaScript test suite and C++ unit tests. In the shell sample don't print the result of executing a script, only evaluating expressions. Fixed issue when building samples on Windows using a shared V8 library. Added visibility option on Linux build which makes the generated library 18% smaller. Changed build system to accept multiple build modes in one build and generate seperate objects, libraries and executables for each mode. Removed deferred negation optimization (a * -b => -(a * b)) since this visibly changes operand conversion order. Improved parsing performance by introducing stack guard in preparsing. Without a stack guard preparsing always bails out with stack overflow. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2008-08-22 13:33:59 +00:00
}
Update and improve support for ARMv7 bitfield instructions. This is a commit of http://codereview.chromium.org/2124022 for Rodolph Perfetta. I changed the test in test-assembler-arm.cc so it only runs if ARMv7 is supported. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4744 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-05-27 13:46:18 +00:00
TEST(Type3) {
Cosmetic changes ("set up" is a verb, "setup" is a noun). Review URL: http://codereview.chromium.org/9139051 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10399 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2012-01-13 13:09:52 +00:00
SET_UP();
Update and improve support for ARMv7 bitfield instructions. This is a commit of http://codereview.chromium.org/2124022 for Rodolph Perfetta. I changed the test in test-assembler-arm.cc so it only runs if ARMv7 is supported. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4744 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-05-27 13:46:18 +00:00
VM initialization refactoring. This patch introduces global once per-process initialization and moves the OS and CPU setup there. This makes CPU features isolate-independent. Review URL: http://codereview.chromium.org/6670119 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7462 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-03-31 16:17:37 +00:00
if (CpuFeatures::IsSupported(ARMv7)) {
Added a ReverseBits operator and used it to implement Ctz. Let me know if this is not the right approach Review URL: https://codereview.chromium.org/1698483002 Cr-Commit-Position: refs/heads/master@{#34028}
2016-02-16 11:14:01 +00:00
CpuFeatureScope scope(&assm, ARMv7);
Update and improve support for ARMv7 bitfield instructions. This is a commit of http://codereview.chromium.org/2124022 for Rodolph Perfetta. I changed the test in test-assembler-arm.cc so it only runs if ARMv7 is supported. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4744 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-05-27 13:46:18 +00:00
COMPARE(ubfx(r0, r1, 5, 10),
"e7e902d1 ubfx r0, r1, #5, #10");
COMPARE(ubfx(r1, r0, 5, 10),
"e7e912d0 ubfx r1, r0, #5, #10");
COMPARE(ubfx(r0, r1, 31, 1),
"e7e00fd1 ubfx r0, r1, #31, #1");
COMPARE(ubfx(r1, r0, 31, 1),
"e7e01fd0 ubfx r1, r0, #31, #1");
COMPARE(sbfx(r0, r1, 5, 10),
"e7a902d1 sbfx r0, r1, #5, #10");
COMPARE(sbfx(r1, r0, 5, 10),
"e7a912d0 sbfx r1, r0, #5, #10");
COMPARE(sbfx(r0, r1, 31, 1),
"e7a00fd1 sbfx r0, r1, #31, #1");
COMPARE(sbfx(r1, r0, 31, 1),
"e7a01fd0 sbfx r1, r0, #31, #1");
COMPARE(bfc(r0, 5, 10),
"e7ce029f bfc r0, #5, #10");
COMPARE(bfc(r1, 5, 10),
"e7ce129f bfc r1, #5, #10");
COMPARE(bfc(r0, 31, 1),
"e7df0f9f bfc r0, #31, #1");
COMPARE(bfc(r1, 31, 1),
"e7df1f9f bfc r1, #31, #1");
COMPARE(bfi(r0, r1, 5, 10),
"e7ce0291 bfi r0, r1, #5, #10");
COMPARE(bfi(r1, r0, 5, 10),
"e7ce1290 bfi r1, r0, #5, #10");
COMPARE(bfi(r0, r1, 31, 1),
"e7df0f91 bfi r0, r1, #31, #1");
COMPARE(bfi(r1, r0, 31, 1),
"e7df1f90 bfi r1, r0, #31, #1");
Landing for Rodolph Perfetta. Add support for saturation instruction (ARMv6 or above). The byte array clamping code has been updated accordingly. Review URL: http://codereview.chromium.org/3036008/show git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5106 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-07-21 07:42:51 +00:00
ARM: Implement memcpy using NEON. Add support for a few NEON and ARM SIMD instructions and use them for various memcpy operations. BUG=none TEST=none Review URL: https://chromiumcodereview.appspot.com/17858002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15602 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-07-10 15:32:39 +00:00
COMPARE(pkhbt(r3, r4, Operand(r5, LSL, 17)),
"e6843895 pkhbt r3, r4, r5, lsl #17");
COMPARE(pkhtb(r3, r4, Operand(r5, ASR, 17)),
"e68438d5 pkhtb r3, r4, r5, asr #17");
[arm] Recognize SXTB, SXTH, UXTB and UXTH. TEST=cctest,msjunit/asm,unittests R=jarin@chromium.org Review URL: https://codereview.chromium.org/709123005 Cr-Commit-Position: refs/heads/master@{#25228} git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25228 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-11-10 05:48:38 +00:00
COMPARE(sxtb(r1, r7, 0, eq), "06af1077 sxtbeq r1, r7");
COMPARE(sxtb(r0, r0, 8, ne), "16af0470 sxtbne r0, r0, ror #8");
COMPARE(sxtb(r9, r10, 16), "e6af987a sxtb r9, r10, ror #16");
COMPARE(sxtb(r4, r3, 24), "e6af4c73 sxtb r4, r3, ror #24");
COMPARE(sxtab(r3, r4, r5), "e6a43075 sxtab r3, r4, r5");
COMPARE(sxth(r5, r0), "e6bf5070 sxth r5, r0");
COMPARE(sxth(r5, r9, 8), "e6bf5479 sxth r5, r9, ror #8");
COMPARE(sxth(r5, r9, 16, hi), "86bf5879 sxthhi r5, r9, ror #16");
COMPARE(sxth(r8, r9, 24, cc), "36bf8c79 sxthcc r8, r9, ror #24");
COMPARE(sxtah(r3, r4, r5, 16), "e6b43875 sxtah r3, r4, r5, ror #16");
COMPARE(uxtb(r9, r10), "e6ef907a uxtb r9, r10");
COMPARE(uxtb(r3, r4, 8), "e6ef3474 uxtb r3, r4, ror #8");
COMPARE(uxtab(r3, r4, r5, 8), "e6e43475 uxtab r3, r4, r5, ror #8");
COMPARE(uxtb16(r3, r4, 8), "e6cf3474 uxtb16 r3, r4, ror #8");
COMPARE(uxth(r9, r10), "e6ff907a uxth r9, r10");
COMPARE(uxth(r3, r4, 8), "e6ff3474 uxth r3, r4, ror #8");
COMPARE(uxtah(r3, r4, r5, 24), "e6f43c75 uxtah r3, r4, r5, ror #24");
Added a ReverseBits operator and used it to implement Ctz. Let me know if this is not the right approach Review URL: https://codereview.chromium.org/1698483002 Cr-Commit-Position: refs/heads/master@{#34028}
2016-02-16 11:14:01 +00:00
COMPARE(rbit(r1, r2), "e6ff1f32 rbit r1, r2");
COMPARE(rbit(r10, ip), "e6ffaf3c rbit r10, ip");
[turbofan] Further optimize DataView accesses. This adds support for unaligned load/store access to the DataView backing store and uses byteswap operations to fix up the endianess when necessary. This changes the Word32ReverseBytes operator to be a required operator and adds the missing support on the Intel and ARM platforms (on 64-bit platforms the Word64ReverseBytes operator is also mandatory now). This further improves the performance on the dataviewperf.js test mentioned in the tracking bug by up to 40%, and at the same time reduces the code complexity in the EffectControlLinearizer. Bug: chromium:225811 Change-Id: I7c1ec826faf46a144a5a9068f8f815a5fd040997 Reviewed-on: https://chromium-review.googlesource.com/1174252 Reviewed-by: Sigurd Schneider <sigurds@chromium.org> Commit-Queue: Benedikt Meurer <bmeurer@chromium.org> Cr-Commit-Position: refs/heads/master@{#55111}
2018-08-14 08:39:05 +00:00
COMPARE(rev(r1, r2), "e6bf1f32 rev r1, r2");
COMPARE(rev(r10, ip), "e6bfaf3c rev r10, ip");
Update and improve support for ARMv7 bitfield instructions. This is a commit of http://codereview.chromium.org/2124022 for Rodolph Perfetta. I changed the test in test-assembler-arm.cc so it only runs if ARMv7 is supported. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4744 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-05-27 13:46:18 +00:00
}
[arm] Clean up handling of usat. The usat instruction is available from ARMv6, so there's no need to check for the ARMv7 feature before using it. ARMv6 is the oldest supported architecture in V8. Correcting this allows the removal of a special case for predictable code size. BUG= Review-Url: https://codereview.chromium.org/1974903002 Cr-Commit-Position: refs/heads/master@{#36218}
2016-05-12 18:18:23 +00:00
COMPARE(usat(r0, 1, Operand(r1)),
"e6e10011 usat r0, #1, r1");
COMPARE(usat(r2, 7, Operand(lr)),
"e6e7201e usat r2, #7, lr");
COMPARE(usat(r3, 31, Operand(r4, LSL, 31)),
"e6ff3f94 usat r3, #31, r4, lsl #31");
COMPARE(usat(r8, 0, Operand(r5, ASR, 17)),
"e6e088d5 usat r8, #0, r5, asr #17");
[arm] Add support for SMMLA, SMMLS and SMMUL. TEST=cctest,unittests R=hpayer@chromium.org Review URL: https://codereview.chromium.org/648283002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24575 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-10-14 05:03:04 +00:00
COMPARE(smmla(r0, r1, r2, r3), "e7503211 smmla r0, r1, r2, r3");
COMPARE(smmla(r10, r9, r8, r7), "e75a7819 smmla r10, r9, r8, r7");
COMPARE(smmul(r0, r1, r2), "e750f211 smmul r0, r1, r2");
COMPARE(smmul(r8, r9, r10), "e758fa19 smmul r8, r9, r10");
Update and improve support for ARMv7 bitfield instructions. This is a commit of http://codereview.chromium.org/2124022 for Rodolph Perfetta. I changed the test in test-assembler-arm.cc so it only runs if ARMv7 is supported. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4744 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-05-27 13:46:18 +00:00
VERIFY_RUN();
}
ARM: Use the vsqrt instruction when available vsqrt is used to calculate Math.sqrt(x), Math.pow(x, 0.5) and Math.pow(x, -0.5). Code size doesn't matter, as %_MathSqrt and %_MathPow are only called in one place each. Review URL: http://codereview.chromium.org/2885002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4974 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-29 09:40:36 +00:00
[arm] Basic simulation of msr and mrs. Only CPSR_f is supported, and then only for the flags that we actually simulate (NZCV). This isn't currently used, but will be useful for some tests. BUG= Review URL: https://codereview.chromium.org/1776933003 Cr-Commit-Position: refs/heads/master@{#34662}
2016-03-10 11:38:17 +00:00
TEST(msr_mrs_disasm) {
SET_UP();
SRegisterFieldMask CPSR_all = CPSR_f | CPSR_s | CPSR_x | CPSR_c;
SRegisterFieldMask SPSR_all = SPSR_f | SPSR_s | SPSR_x | SPSR_c;
COMPARE(msr(CPSR_f, Operand(r0)), "e128f000 msr CPSR_f, r0");
COMPARE(msr(CPSR_s, Operand(r1)), "e124f001 msr CPSR_s, r1");
COMPARE(msr(CPSR_x, Operand(r2)), "e122f002 msr CPSR_x, r2");
COMPARE(msr(CPSR_c, Operand(r3)), "e121f003 msr CPSR_c, r3");
COMPARE(msr(CPSR_all, Operand(ip)), "e12ff00c msr CPSR_fsxc, ip");
COMPARE(msr(SPSR_f, Operand(r0)), "e168f000 msr SPSR_f, r0");
COMPARE(msr(SPSR_s, Operand(r1)), "e164f001 msr SPSR_s, r1");
COMPARE(msr(SPSR_x, Operand(r2)), "e162f002 msr SPSR_x, r2");
COMPARE(msr(SPSR_c, Operand(r3)), "e161f003 msr SPSR_c, r3");
COMPARE(msr(SPSR_all, Operand(ip)), "e16ff00c msr SPSR_fsxc, ip");
COMPARE(msr(CPSR_f, Operand(r0), eq), "0128f000 msreq CPSR_f, r0");
COMPARE(msr(CPSR_s, Operand(r1), ne), "1124f001 msrne CPSR_s, r1");
COMPARE(msr(CPSR_x, Operand(r2), cs), "2122f002 msrcs CPSR_x, r2");
COMPARE(msr(CPSR_c, Operand(r3), cc), "3121f003 msrcc CPSR_c, r3");
COMPARE(msr(CPSR_all, Operand(ip), mi), "412ff00c msrmi CPSR_fsxc, ip");
COMPARE(msr(SPSR_f, Operand(r0), pl), "5168f000 msrpl SPSR_f, r0");
COMPARE(msr(SPSR_s, Operand(r1), vs), "6164f001 msrvs SPSR_s, r1");
COMPARE(msr(SPSR_x, Operand(r2), vc), "7162f002 msrvc SPSR_x, r2");
COMPARE(msr(SPSR_c, Operand(r3), hi), "8161f003 msrhi SPSR_c, r3");
COMPARE(msr(SPSR_all, Operand(ip), ls), "916ff00c msrls SPSR_fsxc, ip");
// Other combinations of mask bits.
COMPARE(msr(CPSR_s | CPSR_x, Operand(r4)),
"e126f004 msr CPSR_sx, r4");
COMPARE(msr(SPSR_s | SPSR_x | SPSR_c, Operand(r5)),
"e167f005 msr SPSR_sxc, r5");
COMPARE(msr(SPSR_s | SPSR_c, Operand(r6)),
"e165f006 msr SPSR_sc, r6");
COMPARE(msr(SPSR_f | SPSR_c, Operand(r7)),
"e169f007 msr SPSR_fc, r7");
// MSR with no mask is UNPREDICTABLE, and checked by the assembler, but check
// that the disassembler does something sensible.
Normalize casing of hexadecimal digits This patch normalizes the casing of hexadecimal digits in escape sequences of the form `\xNN` and integer literals of the form `0xNNNN`. Previously, the V8 code base used an inconsistent mixture of uppercase and lowercase. Google’s C++ style guide uses uppercase in its examples: https://google.github.io/styleguide/cppguide.html#Non-ASCII_Characters Moreover, uppercase letters more clearly stand out from the lowercase `x` (or `u`) characters at the start, as well as lowercase letters elsewhere in strings. BUG=v8:7109 TBR=marja@chromium.org,titzer@chromium.org,mtrofin@chromium.org,mstarzinger@chromium.org,rossberg@chromium.org,yangguo@chromium.org,mlippautz@chromium.org NOPRESUBMIT=true Cq-Include-Trybots: master.tryserver.blink:linux_trusty_blink_rel;master.tryserver.chromium.linux:linux_chromium_rel_ng Change-Id: I790e21c25d96ad5d95c8229724eb45d2aa9e22d6 Reviewed-on: https://chromium-review.googlesource.com/804294 Commit-Queue: Mathias Bynens <mathias@chromium.org> Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#49810}
2017-12-02 00:30:37 +00:00
COMPARE(dd(0xE120F008), "e120f008 msr CPSR_(none), r8");
[arm] Basic simulation of msr and mrs. Only CPSR_f is supported, and then only for the flags that we actually simulate (NZCV). This isn't currently used, but will be useful for some tests. BUG= Review URL: https://codereview.chromium.org/1776933003 Cr-Commit-Position: refs/heads/master@{#34662}
2016-03-10 11:38:17 +00:00
COMPARE(mrs(r0, CPSR), "e10f0000 mrs r0, CPSR");
COMPARE(mrs(r1, SPSR), "e14f1000 mrs r1, SPSR");
COMPARE(mrs(r2, CPSR, ge), "a10f2000 mrsge r2, CPSR");
COMPARE(mrs(r3, SPSR, lt), "b14f3000 mrslt r3, SPSR");
VERIFY_RUN();
}
ARM: Use the vsqrt instruction when available vsqrt is used to calculate Math.sqrt(x), Math.pow(x, 0.5) and Math.pow(x, -0.5). Code size doesn't matter, as %_MathSqrt and %_MathPow are only called in one place each. Review URL: http://codereview.chromium.org/2885002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4974 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-29 09:40:36 +00:00
TEST(Vfp) {
Cosmetic changes ("set up" is a verb, "setup" is a noun). Review URL: http://codereview.chromium.org/9139051 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10399 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2012-01-13 13:09:52 +00:00
SET_UP();
ARM: Use the vsqrt instruction when available vsqrt is used to calculate Math.sqrt(x), Math.pow(x, 0.5) and Math.pow(x, -0.5). Code size doesn't matter, as %_MathSqrt and %_MathPow are only called in one place each. Review URL: http://codereview.chromium.org/2885002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4974 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-29 09:40:36 +00:00
[arm] Clean up use of IsSupported and IsEnabled. CpuFeatures::IsSupported(feature) indicates that the feature is available on the target. AssemblerBase::IsEnabled(feature) indicates that we've checked for support (using CpuFeatureScope). The main benefit is that we can test on (for example) ARMv8, but have some assurance that we won't generate ARMv8 instructions on ARMv7 targets. This patch simply cleans up the usage, which had become inconsistent. The instruction emission functions now check not only that their dependent features are supported, but also that we've verified that using CpuFeatureScope. BUG= Review-Url: https://codereview.chromium.org/2360243002 Cr-Commit-Position: refs/heads/master@{#39676}
2016-09-23 15:29:11 +00:00
if (CpuFeatures::IsSupported(VFPv3)) {
CpuFeatureScope scope(&assm, VFPv3);
ARM: Make use of d16-d31 when available. Review URL: https://chromiumcodereview.appspot.com/11428137 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13484 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-01-23 16:29:48 +00:00
COMPARE(vmov(d0, r2, r3),
"ec432b10 vmov d0, r2, r3");
COMPARE(vmov(r2, r3, d0),
"ec532b10 vmov r2, r3, d0");
[arm] Use the converter when printing general registers When disassembling some instructions we would print `r12`, which can be confusing when the rest of the disassembly consistently uses `ip`. Bug: Change-Id: Id4cfc5805ef102a0845cdaaa8390e618ee981b19 Reviewed-on: https://chromium-review.googlesource.com/570038 Reviewed-by: Georg Neis <neis@chromium.org> Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Cr-Commit-Position: refs/heads/master@{#46628}
2017-07-13 10:07:46 +00:00
COMPARE(vmov(r4, ip, d1),
"ec5c4b11 vmov r4, ip, d1");
ARM: Special code for raising to the power of an integer When calculating Math.pow where the exponent is a smi use a simple loop to calculate the result. Added support for the vmov instruction moving from one doubleword extension register to another. Added some Math.pow tests which partially covers what is in the Sputnik tests. Review URL: http://codereview.chromium.org/2804033 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4990 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-30 12:22:15 +00:00
COMPARE(vmov(d0, d1),
"eeb00b41 vmov.f64 d0, d1");
COMPARE(vmov(d3, d3, eq),
ARM: Fix disassembly of some VFP instructions with condition codes Previously, we would disassemble some VFP instructions like this: vmla.f64eq d16, d17, d18 This patch moves the condition to the right place: vmlaeq.f64 d16, d17, d18 Spotted by Rodolph Perfetta! BUG=none Review URL: https://chromiumcodereview.appspot.com/12335129 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13752 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-02-27 11:52:45 +00:00
"0eb03b43 vmoveq.f64 d3, d3");
ARM: Special code for raising to the power of an integer When calculating Math.pow where the exponent is a smi use a simple loop to calculate the result. Added support for the vmov instruction moving from one doubleword extension register to another. Added some Math.pow tests which partially covers what is in the Sputnik tests. Review URL: http://codereview.chromium.org/2804033 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4990 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-30 12:22:15 +00:00
Fix incorrect encoding of single and double precision registers for some VFP instructions. Also fix incorrect disassembling of vldr/vstr. This is a commit of http://codereview.chromium.org/3107027 for Rodolph Perfetta. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5352 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-08-26 08:53:00 +00:00
COMPARE(vmov(s0, s31),
"eeb00a6f vmov.f32 s0, s31");
COMPARE(vmov(s31, s0),
"eef0fa40 vmov.f32 s31, s0");
COMPARE(vmov(r0, s0),
"ee100a10 vmov r0, s0");
COMPARE(vmov(r10, s31),
"ee1faa90 vmov r10, s31");
COMPARE(vmov(s0, r0),
"ee000a10 vmov s0, r0");
COMPARE(vmov(s31, r10),
"ee0faa90 vmov s31, r10");
ARM: Add support for DoMathAbs with double inputs. Adds vabs instruction to simulator, assembler, disassembler and tests. BUG=none TEST=Added to cctest. Review URL: http://codereview.chromium.org/6366016 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6531 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-01-31 10:16:28 +00:00
COMPARE(vabs(d0, d1),
ARM: Fix disasm for strh, vabs, vneg. Add load/store tests. Patch from ARM Ltd. BUG=none TEST=added to test/cctest/test-disasm-arm.cc Original review at http://codereview.chromium.org/7013024/. Review URL: http://codereview.chromium.org/7013027 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7875 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-05-12 14:44:49 +00:00
"eeb00bc1 vabs.f64 d0, d1");
ARM: Add support for DoMathAbs with double inputs. Adds vabs instruction to simulator, assembler, disassembler and tests. BUG=none TEST=Added to cctest. Review URL: http://codereview.chromium.org/6366016 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6531 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-01-31 10:16:28 +00:00
COMPARE(vabs(d3, d4, mi),
ARM: Fix disassembly of some VFP instructions with condition codes Previously, we would disassemble some VFP instructions like this: vmla.f64eq d16, d17, d18 This patch moves the condition to the right place: vmlaeq.f64 d16, d17, d18 Spotted by Rodolph Perfetta! BUG=none Review URL: https://chromiumcodereview.appspot.com/12335129 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13752 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-02-27 11:52:45 +00:00
"4eb03bc4 vabsmi.f64 d3, d4");
ARM: Add support for DoMathAbs with double inputs. Adds vabs instruction to simulator, assembler, disassembler and tests. BUG=none TEST=Added to cctest. Review URL: http://codereview.chromium.org/6366016 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6531 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-01-31 10:16:28 +00:00
[turbofan] Add backend support for float32 operations. This adds the basics necessary to support float32 operations in TurboFan. The actual functionality required to detect safe float32 operations will be added based on this later. Therefore this does not affect production code except for some cleanup/refactoring. In detail, this patchset contains the following features: - Add support for float32 operations to arm, arm64, ia32 and x64 backends. - Add float32 machine operators. - Add support for float32 constants to simplified lowering. - Handle float32 representation for phis in simplified lowering. In addition, contains the following (related) cleanups: - Fix/unify naming of backend instructions. - Use AVX comparisons when available. - Extend ArchOpcodeField to 9 bits (required for arm64). - Refactor some code duplication in instruction selectors. BUG=v8:3589 LOG=n R=dcarney@chromium.org Review URL: https://codereview.chromium.org/1044793002 Cr-Commit-Position: refs/heads/master@{#27509}
2015-03-30 07:33:46 +00:00
COMPARE(vabs(s0, s1),
"eeb00ae0 vabs.f32 s0, s1");
COMPARE(vabs(s3, s4, mi),
"4ef01ac2 vabsmi.f32 s3, s4");
ARM: Improved double to integer truncation. Patch from ARM Ltd. BUG=none TEST=Added to cctest/test-assembler-arm.cc and cctest/test-disasm-arm.cc Review URL: http://codereview.chromium.org/6625084 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7174 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-03-15 11:19:13 +00:00
COMPARE(vneg(d0, d1),
ARM: Fix disasm for strh, vabs, vneg. Add load/store tests. Patch from ARM Ltd. BUG=none TEST=added to test/cctest/test-disasm-arm.cc Original review at http://codereview.chromium.org/7013024/. Review URL: http://codereview.chromium.org/7013027 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7875 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-05-12 14:44:49 +00:00
"eeb10b41 vneg.f64 d0, d1");
ARM: Improved double to integer truncation. Patch from ARM Ltd. BUG=none TEST=Added to cctest/test-assembler-arm.cc and cctest/test-disasm-arm.cc Review URL: http://codereview.chromium.org/6625084 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7174 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-03-15 11:19:13 +00:00
COMPARE(vneg(d3, d4, mi),
ARM: Fix disassembly of some VFP instructions with condition codes Previously, we would disassemble some VFP instructions like this: vmla.f64eq d16, d17, d18 This patch moves the condition to the right place: vmlaeq.f64 d16, d17, d18 Spotted by Rodolph Perfetta! BUG=none Review URL: https://chromiumcodereview.appspot.com/12335129 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13752 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-02-27 11:52:45 +00:00
"4eb13b44 vnegmi.f64 d3, d4");
ARM: Improved double to integer truncation. Patch from ARM Ltd. BUG=none TEST=Added to cctest/test-assembler-arm.cc and cctest/test-disasm-arm.cc Review URL: http://codereview.chromium.org/6625084 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7174 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-03-15 11:19:13 +00:00
[turbofan] Add backend support for float32 operations. This adds the basics necessary to support float32 operations in TurboFan. The actual functionality required to detect safe float32 operations will be added based on this later. Therefore this does not affect production code except for some cleanup/refactoring. In detail, this patchset contains the following features: - Add support for float32 operations to arm, arm64, ia32 and x64 backends. - Add float32 machine operators. - Add support for float32 constants to simplified lowering. - Handle float32 representation for phis in simplified lowering. In addition, contains the following (related) cleanups: - Fix/unify naming of backend instructions. - Use AVX comparisons when available. - Extend ArchOpcodeField to 9 bits (required for arm64). - Refactor some code duplication in instruction selectors. BUG=v8:3589 LOG=n R=dcarney@chromium.org Review URL: https://codereview.chromium.org/1044793002 Cr-Commit-Position: refs/heads/master@{#27509}
2015-03-30 07:33:46 +00:00
COMPARE(vneg(s0, s1),
"eeb10a60 vneg.f32 s0, s1");
COMPARE(vneg(s3, s4, mi),
"4ef11a42 vnegmi.f32 s3, s4");
ARM: Fix disassembly of double registers Added a few disassembler tests for vadd, vsub, vmul and vdiv. Review URL: http://codereview.chromium.org/2823036 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4986 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-30 08:46:19 +00:00
COMPARE(vadd(d0, d1, d2),
"ee310b02 vadd.f64 d0, d1, d2");
COMPARE(vadd(d3, d4, d5, mi),
ARM: Fix disassembly of some VFP instructions with condition codes Previously, we would disassemble some VFP instructions like this: vmla.f64eq d16, d17, d18 This patch moves the condition to the right place: vmlaeq.f64 d16, d17, d18 Spotted by Rodolph Perfetta! BUG=none Review URL: https://chromiumcodereview.appspot.com/12335129 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13752 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-02-27 11:52:45 +00:00
"4e343b05 vaddmi.f64 d3, d4, d5");
ARM: Fix disassembly of double registers Added a few disassembler tests for vadd, vsub, vmul and vdiv. Review URL: http://codereview.chromium.org/2823036 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4986 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-30 08:46:19 +00:00
[turbofan] Add backend support for float32 operations. This adds the basics necessary to support float32 operations in TurboFan. The actual functionality required to detect safe float32 operations will be added based on this later. Therefore this does not affect production code except for some cleanup/refactoring. In detail, this patchset contains the following features: - Add support for float32 operations to arm, arm64, ia32 and x64 backends. - Add float32 machine operators. - Add support for float32 constants to simplified lowering. - Handle float32 representation for phis in simplified lowering. In addition, contains the following (related) cleanups: - Fix/unify naming of backend instructions. - Use AVX comparisons when available. - Extend ArchOpcodeField to 9 bits (required for arm64). - Refactor some code duplication in instruction selectors. BUG=v8:3589 LOG=n R=dcarney@chromium.org Review URL: https://codereview.chromium.org/1044793002 Cr-Commit-Position: refs/heads/master@{#27509}
2015-03-30 07:33:46 +00:00
COMPARE(vadd(s0, s1, s2),
"ee300a81 vadd.f32 s0, s1, s2");
COMPARE(vadd(s3, s4, s5, mi),
"4e721a22 vaddmi.f32 s3, s4, s5");
ARM: Fix disassembly of double registers Added a few disassembler tests for vadd, vsub, vmul and vdiv. Review URL: http://codereview.chromium.org/2823036 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4986 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-30 08:46:19 +00:00
COMPARE(vsub(d0, d1, d2),
"ee310b42 vsub.f64 d0, d1, d2");
COMPARE(vsub(d3, d4, d5, ne),
ARM: Fix disassembly of some VFP instructions with condition codes Previously, we would disassemble some VFP instructions like this: vmla.f64eq d16, d17, d18 This patch moves the condition to the right place: vmlaeq.f64 d16, d17, d18 Spotted by Rodolph Perfetta! BUG=none Review URL: https://chromiumcodereview.appspot.com/12335129 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13752 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-02-27 11:52:45 +00:00
"1e343b45 vsubne.f64 d3, d4, d5");
ARM: Fix disassembly of double registers Added a few disassembler tests for vadd, vsub, vmul and vdiv. Review URL: http://codereview.chromium.org/2823036 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4986 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-30 08:46:19 +00:00
[turbofan] Add backend support for float32 operations. This adds the basics necessary to support float32 operations in TurboFan. The actual functionality required to detect safe float32 operations will be added based on this later. Therefore this does not affect production code except for some cleanup/refactoring. In detail, this patchset contains the following features: - Add support for float32 operations to arm, arm64, ia32 and x64 backends. - Add float32 machine operators. - Add support for float32 constants to simplified lowering. - Handle float32 representation for phis in simplified lowering. In addition, contains the following (related) cleanups: - Fix/unify naming of backend instructions. - Use AVX comparisons when available. - Extend ArchOpcodeField to 9 bits (required for arm64). - Refactor some code duplication in instruction selectors. BUG=v8:3589 LOG=n R=dcarney@chromium.org Review URL: https://codereview.chromium.org/1044793002 Cr-Commit-Position: refs/heads/master@{#27509}
2015-03-30 07:33:46 +00:00
COMPARE(vsub(s0, s1, s2),
"ee300ac1 vsub.f32 s0, s1, s2");
COMPARE(vsub(s3, s4, s5, ne),
"1e721a62 vsubne.f32 s3, s4, s5");
ARM: Fix disassembly of double registers Added a few disassembler tests for vadd, vsub, vmul and vdiv. Review URL: http://codereview.chromium.org/2823036 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4986 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-30 08:46:19 +00:00
COMPARE(vmul(d2, d1, d0),
"ee212b00 vmul.f64 d2, d1, d0");
COMPARE(vmul(d6, d4, d5, cc),
ARM: Fix disassembly of some VFP instructions with condition codes Previously, we would disassemble some VFP instructions like this: vmla.f64eq d16, d17, d18 This patch moves the condition to the right place: vmlaeq.f64 d16, d17, d18 Spotted by Rodolph Perfetta! BUG=none Review URL: https://chromiumcodereview.appspot.com/12335129 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13752 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-02-27 11:52:45 +00:00
"3e246b05 vmulcc.f64 d6, d4, d5");
ARM: Fix disassembly of double registers Added a few disassembler tests for vadd, vsub, vmul and vdiv. Review URL: http://codereview.chromium.org/2823036 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4986 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-30 08:46:19 +00:00
[turbofan] Add backend support for float32 operations. This adds the basics necessary to support float32 operations in TurboFan. The actual functionality required to detect safe float32 operations will be added based on this later. Therefore this does not affect production code except for some cleanup/refactoring. In detail, this patchset contains the following features: - Add support for float32 operations to arm, arm64, ia32 and x64 backends. - Add float32 machine operators. - Add support for float32 constants to simplified lowering. - Handle float32 representation for phis in simplified lowering. In addition, contains the following (related) cleanups: - Fix/unify naming of backend instructions. - Use AVX comparisons when available. - Extend ArchOpcodeField to 9 bits (required for arm64). - Refactor some code duplication in instruction selectors. BUG=v8:3589 LOG=n R=dcarney@chromium.org Review URL: https://codereview.chromium.org/1044793002 Cr-Commit-Position: refs/heads/master@{#27509}
2015-03-30 07:33:46 +00:00
COMPARE(vmul(s2, s1, s0),
"ee201a80 vmul.f32 s2, s1, s0");
COMPARE(vmul(s6, s4, s5, cc),
"3e223a22 vmulcc.f32 s6, s4, s5");
ARM: Fix disassembly of double registers Added a few disassembler tests for vadd, vsub, vmul and vdiv. Review URL: http://codereview.chromium.org/2823036 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4986 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-30 08:46:19 +00:00
COMPARE(vdiv(d2, d2, d2),
"ee822b02 vdiv.f64 d2, d2, d2");
COMPARE(vdiv(d6, d7, d7, hi),
ARM: Fix disassembly of some VFP instructions with condition codes Previously, we would disassemble some VFP instructions like this: vmla.f64eq d16, d17, d18 This patch moves the condition to the right place: vmlaeq.f64 d16, d17, d18 Spotted by Rodolph Perfetta! BUG=none Review URL: https://chromiumcodereview.appspot.com/12335129 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13752 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-02-27 11:52:45 +00:00
"8e876b07 vdivhi.f64 d6, d7, d7");
ARM: Fix disassembly of double registers Added a few disassembler tests for vadd, vsub, vmul and vdiv. Review URL: http://codereview.chromium.org/2823036 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4986 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-30 08:46:19 +00:00
[turbofan] Add backend support for float32 operations. This adds the basics necessary to support float32 operations in TurboFan. The actual functionality required to detect safe float32 operations will be added based on this later. Therefore this does not affect production code except for some cleanup/refactoring. In detail, this patchset contains the following features: - Add support for float32 operations to arm, arm64, ia32 and x64 backends. - Add float32 machine operators. - Add support for float32 constants to simplified lowering. - Handle float32 representation for phis in simplified lowering. In addition, contains the following (related) cleanups: - Fix/unify naming of backend instructions. - Use AVX comparisons when available. - Extend ArchOpcodeField to 9 bits (required for arm64). - Refactor some code duplication in instruction selectors. BUG=v8:3589 LOG=n R=dcarney@chromium.org Review URL: https://codereview.chromium.org/1044793002 Cr-Commit-Position: refs/heads/master@{#27509}
2015-03-30 07:33:46 +00:00
COMPARE(vdiv(s2, s2, s2),
"ee811a01 vdiv.f32 s2, s2, s2");
COMPARE(vdiv(s6, s7, s7, hi),
"8e833aa3 vdivhi.f32 s6, s7, s7");
ARM: Make use of d16-d31 when available. Review URL: https://chromiumcodereview.appspot.com/11428137 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13484 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-01-23 16:29:48 +00:00
COMPARE(vcmp(d0, d1),
"eeb40b41 vcmp.f64 d0, d1");
COMPARE(vcmp(d0, 0.0),
"eeb50b40 vcmp.f64 d0, #0.0");
[turbofan] Add backend support for float32 operations. This adds the basics necessary to support float32 operations in TurboFan. The actual functionality required to detect safe float32 operations will be added based on this later. Therefore this does not affect production code except for some cleanup/refactoring. In detail, this patchset contains the following features: - Add support for float32 operations to arm, arm64, ia32 and x64 backends. - Add float32 machine operators. - Add support for float32 constants to simplified lowering. - Handle float32 representation for phis in simplified lowering. In addition, contains the following (related) cleanups: - Fix/unify naming of backend instructions. - Use AVX comparisons when available. - Extend ArchOpcodeField to 9 bits (required for arm64). - Refactor some code duplication in instruction selectors. BUG=v8:3589 LOG=n R=dcarney@chromium.org Review URL: https://codereview.chromium.org/1044793002 Cr-Commit-Position: refs/heads/master@{#27509}
2015-03-30 07:33:46 +00:00
COMPARE(vcmp(s0, s1),
"eeb40a60 vcmp.f32 s0, s1");
COMPARE(vcmp(s0, 0.0f),
"eeb50a40 vcmp.f32 s0, #0.0");
ARM: Use the vsqrt instruction when available vsqrt is used to calculate Math.sqrt(x), Math.pow(x, 0.5) and Math.pow(x, -0.5). Code size doesn't matter, as %_MathSqrt and %_MathPow are only called in one place each. Review URL: http://codereview.chromium.org/2885002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4974 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-29 09:40:36 +00:00
COMPARE(vsqrt(d0, d0),
"eeb10bc0 vsqrt.f64 d0, d0");
ARM: Fix disassembly of double registers Added a few disassembler tests for vadd, vsub, vmul and vdiv. Review URL: http://codereview.chromium.org/2823036 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4986 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-30 08:46:19 +00:00
COMPARE(vsqrt(d2, d3, ne),
ARM: Fix disassembly of some VFP instructions with condition codes Previously, we would disassemble some VFP instructions like this: vmla.f64eq d16, d17, d18 This patch moves the condition to the right place: vmlaeq.f64 d16, d17, d18 Spotted by Rodolph Perfetta! BUG=none Review URL: https://chromiumcodereview.appspot.com/12335129 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13752 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-02-27 11:52:45 +00:00
"1eb12bc3 vsqrtne.f64 d2, d3");
ARM: Add support for the VFP mov literal instruction and mov between single VFP registers. Math.pow implementation has been updated with the new instructions. This is a commit of http://codereview.chromium.org/2813046/show for Rodolph Perfetta. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5037 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-07-08 12:38:02 +00:00
[turbofan] Add backend support for float32 operations. This adds the basics necessary to support float32 operations in TurboFan. The actual functionality required to detect safe float32 operations will be added based on this later. Therefore this does not affect production code except for some cleanup/refactoring. In detail, this patchset contains the following features: - Add support for float32 operations to arm, arm64, ia32 and x64 backends. - Add float32 machine operators. - Add support for float32 constants to simplified lowering. - Handle float32 representation for phis in simplified lowering. In addition, contains the following (related) cleanups: - Fix/unify naming of backend instructions. - Use AVX comparisons when available. - Extend ArchOpcodeField to 9 bits (required for arm64). - Refactor some code duplication in instruction selectors. BUG=v8:3589 LOG=n R=dcarney@chromium.org Review URL: https://codereview.chromium.org/1044793002 Cr-Commit-Position: refs/heads/master@{#27509}
2015-03-30 07:33:46 +00:00
COMPARE(vsqrt(s0, s0),
"eeb10ac0 vsqrt.f32 s0, s0");
COMPARE(vsqrt(s2, s3, ne),
"1eb11ae1 vsqrtne.f32 s2, s3");
[arm][turbofan] Pass double immediate to vmov as uint64_t On x86, signalling NaNs get converted to quiet NaNs when they get push on the stack and popped again. This happens in the code generation for arm, specifically for the vmov instruction with the immediate parameter. This CL replaces the vmov function in assembler-arm to take the immediate as a uint64_t instead of a double, to guarantee that the bit pattern does not change even if the parameter is a signalling NaN. BUG=v8:6564 Change-Id: I062559f9a7ba8b0f560628e5c39621ca578c3e7d Reviewed-on: https://chromium-review.googlesource.com/558964 Commit-Queue: Andreas Haas <ahaas@chromium.org> Reviewed-by: Ben Titzer <titzer@chromium.org> Reviewed-by: Martyn Capewell <martyn.capewell@arm.com> Cr-Commit-Position: refs/heads/master@{#46418}
2017-07-05 13:48:12 +00:00
COMPARE(vmov(d0, Double(1.0)),
ARM: Add support for the VFP mov literal instruction and mov between single VFP registers. Math.pow implementation has been updated with the new instructions. This is a commit of http://codereview.chromium.org/2813046/show for Rodolph Perfetta. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5037 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-07-08 12:38:02 +00:00
"eeb70b00 vmov.f64 d0, #1");
[arm][turbofan] Pass double immediate to vmov as uint64_t On x86, signalling NaNs get converted to quiet NaNs when they get push on the stack and popped again. This happens in the code generation for arm, specifically for the vmov instruction with the immediate parameter. This CL replaces the vmov function in assembler-arm to take the immediate as a uint64_t instead of a double, to guarantee that the bit pattern does not change even if the parameter is a signalling NaN. BUG=v8:6564 Change-Id: I062559f9a7ba8b0f560628e5c39621ca578c3e7d Reviewed-on: https://chromium-review.googlesource.com/558964 Commit-Queue: Andreas Haas <ahaas@chromium.org> Reviewed-by: Ben Titzer <titzer@chromium.org> Reviewed-by: Martyn Capewell <martyn.capewell@arm.com> Cr-Commit-Position: refs/heads/master@{#46418}
2017-07-05 13:48:12 +00:00
COMPARE(vmov(d2, Double(-13.0)),
ARM: Add support for the VFP mov literal instruction and mov between single VFP registers. Math.pow implementation has been updated with the new instructions. This is a commit of http://codereview.chromium.org/2813046/show for Rodolph Perfetta. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5037 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-07-08 12:38:02 +00:00
"eeba2b0a vmov.f64 d2, #-13");
Fix incorrect encoding of single and double precision registers for some VFP instructions. Also fix incorrect disassembling of vldr/vstr. This is a commit of http://codereview.chromium.org/3107027 for Rodolph Perfetta. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5352 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-08-26 08:53:00 +00:00
[arm] Pass float immediates to vmov as uint32_t This CL changes for floats what https://chromium-review.googlesource.com/c/558964/ changed for doubles. Original message: On x86, signalling NaNs get converted to quiet NaNs when they get push on the stack and popped again. This happens in the code generation for arm, specifically for the vmov instruction with the immediate parameter. This CL replaces the vmov function in assembler-arm to take the immediate as a uint64_t instead of a double, to guarantee that the bit pattern does not change even if the parameter is a signalling NaN. New in this CL: Although src/double.h existed already, src/float.h did not exist yet. I created the file in this CL, and moved the classes Float32 and Float64 there, which already existed in src/deoptimizer.h. R=titzer@chromium.org, martyn.capewell@arm.com, v8-arm-ports@googlegroups.com BUG=v8:6564 Change-Id: I6a3f1f154af9c8cd4bb8e7e856235d3eee5e9edd Reviewed-on: https://chromium-review.googlesource.com/561009 Commit-Queue: Andreas Haas <ahaas@chromium.org> Reviewed-by: Martyn Capewell <martyn.capewell@arm.com> Reviewed-by: Ben Titzer <titzer@chromium.org> Cr-Commit-Position: refs/heads/master@{#46473}
2017-07-07 11:32:01 +00:00
COMPARE(vmov(s1, Float32(-1.0f)),
[turbofan] ARM: Reduce out-of-line NaN code size Reduce the amount of code generated for OutOfLineLoadFloat* by computing sqrt(-1) rather than move the NaN as an immediate. Add support for single precision floating point immediate moves to enable this. BUG= Review URL: https://codereview.chromium.org/1758003003 Cr-Commit-Position: refs/heads/master@{#34746}
2016-03-14 15:30:13 +00:00
"eeff0a00 vmov.f32 s1, #-1");
[arm] Pass float immediates to vmov as uint32_t This CL changes for floats what https://chromium-review.googlesource.com/c/558964/ changed for doubles. Original message: On x86, signalling NaNs get converted to quiet NaNs when they get push on the stack and popped again. This happens in the code generation for arm, specifically for the vmov instruction with the immediate parameter. This CL replaces the vmov function in assembler-arm to take the immediate as a uint64_t instead of a double, to guarantee that the bit pattern does not change even if the parameter is a signalling NaN. New in this CL: Although src/double.h existed already, src/float.h did not exist yet. I created the file in this CL, and moved the classes Float32 and Float64 there, which already existed in src/deoptimizer.h. R=titzer@chromium.org, martyn.capewell@arm.com, v8-arm-ports@googlegroups.com BUG=v8:6564 Change-Id: I6a3f1f154af9c8cd4bb8e7e856235d3eee5e9edd Reviewed-on: https://chromium-review.googlesource.com/561009 Commit-Queue: Andreas Haas <ahaas@chromium.org> Reviewed-by: Martyn Capewell <martyn.capewell@arm.com> Reviewed-by: Ben Titzer <titzer@chromium.org> Cr-Commit-Position: refs/heads/master@{#46473}
2017-07-07 11:32:01 +00:00
COMPARE(vmov(s3, Float32(13.0f)),
[turbofan] ARM: Reduce out-of-line NaN code size Reduce the amount of code generated for OutOfLineLoadFloat* by computing sqrt(-1) rather than move the NaN as an immediate. Add support for single precision floating point immediate moves to enable this. BUG= Review URL: https://codereview.chromium.org/1758003003 Cr-Commit-Position: refs/heads/master@{#34746}
2016-03-14 15:30:13 +00:00
"eef21a0a vmov.f32 s3, #13");
[arm] Eliminate old form of core-scalar vmov instructions. - Eliminates less general forms of vmov between core and scalar FP registers. Bug: v8:7754 Change-Id: I3224c57e03dfd64ea6552b215017dacc357dda26 Reviewed-on: https://chromium-review.googlesource.com/1144126 Commit-Queue: Bill Budge <bbudge@chromium.org> Reviewed-by: Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#54663}
2018-07-24 16:56:27 +00:00
COMPARE(vmov(NeonS32, d0, 0, r0),
ARM: Make use of d16-d31 when available. Review URL: https://chromiumcodereview.appspot.com/11428137 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13484 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-01-23 16:29:48 +00:00
"ee000b10 vmov.32 d0[0], r0");
[arm] Eliminate old form of core-scalar vmov instructions. - Eliminates less general forms of vmov between core and scalar FP registers. Bug: v8:7754 Change-Id: I3224c57e03dfd64ea6552b215017dacc357dda26 Reviewed-on: https://chromium-review.googlesource.com/1144126 Commit-Queue: Bill Budge <bbudge@chromium.org> Reviewed-by: Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#54663}
2018-07-24 16:56:27 +00:00
COMPARE(vmov(NeonS32, d0, 1, r0),
ARM: Make use of d16-d31 when available. Review URL: https://chromiumcodereview.appspot.com/11428137 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13484 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-01-23 16:29:48 +00:00
"ee200b10 vmov.32 d0[1], r0");
[arm] Eliminate old form of core-scalar vmov instructions. - Eliminates less general forms of vmov between core and scalar FP registers. Bug: v8:7754 Change-Id: I3224c57e03dfd64ea6552b215017dacc357dda26 Reviewed-on: https://chromium-review.googlesource.com/1144126 Commit-Queue: Bill Budge <bbudge@chromium.org> Reviewed-by: Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#54663}
2018-07-24 16:56:27 +00:00
COMPARE(vmov(NeonS32, r2, d15, 0),
ARM: Make double registers low/high safe This patch prevents taking the low/high part of a double-precision VFP register that has no corresponding single-precision VFP registers. BUG=none TEST=Added to test-disasm-arm.cc, test-assembler-arm.cc Review URL: https://codereview.chromium.org/19560003 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15885 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-07-25 15:04:38 +00:00
"ee1f2b10 vmov.32 r2, d15[0]");
[arm] Eliminate old form of core-scalar vmov instructions. - Eliminates less general forms of vmov between core and scalar FP registers. Bug: v8:7754 Change-Id: I3224c57e03dfd64ea6552b215017dacc357dda26 Reviewed-on: https://chromium-review.googlesource.com/1144126 Commit-Queue: Bill Budge <bbudge@chromium.org> Reviewed-by: Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#54663}
2018-07-24 16:56:27 +00:00
COMPARE(vmov(NeonS32, r3, d14, 1),
ARM: Make double registers low/high safe This patch prevents taking the low/high part of a double-precision VFP register that has no corresponding single-precision VFP registers. BUG=none TEST=Added to test-disasm-arm.cc, test-assembler-arm.cc Review URL: https://codereview.chromium.org/19560003 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15885 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-07-25 15:04:38 +00:00
"ee3e3b10 vmov.32 r3, d14[1]");
Fix incorrect encoding of single and double precision registers for some VFP instructions. Also fix incorrect disassembling of vldr/vstr. This is a commit of http://codereview.chromium.org/3107027 for Rodolph Perfetta. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5352 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-08-26 08:53:00 +00:00
COMPARE(vldr(s0, r0, 0),
"ed900a00 vldr s0, [r0 + 4*0]");
COMPARE(vldr(s1, r1, 4),
"edd10a01 vldr s1, [r1 + 4*1]");
COMPARE(vldr(s15, r4, 16),
"edd47a04 vldr s15, [r4 + 4*4]");
COMPARE(vldr(s16, r5, 20),
"ed958a05 vldr s16, [r5 + 4*5]");
COMPARE(vldr(s31, r10, 1020),
"eddafaff vldr s31, [r10 + 4*255]");
[arm] Use the converter when printing general registers When disassembling some instructions we would print `r12`, which can be confusing when the rest of the disassembly consistently uses `ip`. Bug: Change-Id: Id4cfc5805ef102a0845cdaaa8390e618ee981b19 Reviewed-on: https://chromium-review.googlesource.com/570038 Reviewed-by: Georg Neis <neis@chromium.org> Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Cr-Commit-Position: refs/heads/master@{#46628}
2017-07-13 10:07:46 +00:00
COMPARE(vldr(s31, ip, 1020),
"eddcfaff vldr s31, [ip + 4*255]");
Fix incorrect encoding of single and double precision registers for some VFP instructions. Also fix incorrect disassembling of vldr/vstr. This is a commit of http://codereview.chromium.org/3107027 for Rodolph Perfetta. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5352 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-08-26 08:53:00 +00:00
COMPARE(vstr(s0, r0, 0),
"ed800a00 vstr s0, [r0 + 4*0]");
COMPARE(vstr(s1, r1, 4),
"edc10a01 vstr s1, [r1 + 4*1]");
COMPARE(vstr(s15, r8, 8),
"edc87a02 vstr s15, [r8 + 4*2]");
COMPARE(vstr(s16, r9, 12),
"ed898a03 vstr s16, [r9 + 4*3]");
COMPARE(vstr(s31, r10, 1020),
"edcafaff vstr s31, [r10 + 4*255]");
COMPARE(vldr(d0, r0, 0),
"ed900b00 vldr d0, [r0 + 4*0]");
COMPARE(vldr(d1, r1, 4),
"ed911b01 vldr d1, [r1 + 4*1]");
COMPARE(vldr(d15, r10, 1020),
"ed9afbff vldr d15, [r10 + 4*255]");
COMPARE(vstr(d0, r0, 0),
"ed800b00 vstr d0, [r0 + 4*0]");
COMPARE(vstr(d1, r1, 4),
"ed811b01 vstr d1, [r1 + 4*1]");
COMPARE(vstr(d15, r10, 1020),
"ed8afbff vstr d15, [r10 + 4*255]");
Improve support for vmrs/vmsr in ARM disassembler. This is a commit of http://codereview.chromium.org/4904001 for Martyn Capewell. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5824 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-11-15 10:21:57 +00:00
COMPARE(vmsr(r5),
"eee15a10 vmsr FPSCR, r5");
COMPARE(vmsr(r10, pl),
"5ee1aa10 vmsrpl FPSCR, r10");
COMPARE(vmsr(pc),
"eee1fa10 vmsr FPSCR, APSR");
COMPARE(vmrs(r5),
"eef15a10 vmrs r5, FPSCR");
COMPARE(vmrs(r10, ge),
"aef1aa10 vmrsge r10, FPSCR");
COMPARE(vmrs(pc),
"eef1fa10 vmrs APSR, FPSCR");
ARM: Add support load/store multiple VFP registers Enter/exit frames with save doubles use these instructions instead of generating 16 load/store instructions. R=karlklose@chromium.org, rodolph.perfetta@gmail.com BUG= TEST= Review URL: http://codereview.chromium.org//6691057 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7509 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-04-06 09:06:23 +00:00
COMPARE(vstm(ia, r0, d1, d3),
"ec801b06 vstmia r0, {d1-d3}");
COMPARE(vldm(ia, r1, d2, d5),
"ec912b08 vldmia r1, {d2-d5}");
COMPARE(vstm(ia, r2, d0, d15),
"ec820b20 vstmia r2, {d0-d15}");
COMPARE(vldm(ia, r3, d0, d15),
"ec930b20 vldmia r3, {d0-d15}");
COMPARE(vstm(ia, r4, s1, s3),
"ecc40a03 vstmia r4, {s1-s3}");
COMPARE(vldm(ia, r5, s2, s5),
"ec951a04 vldmia r5, {s2-s5}");
COMPARE(vstm(ia, r6, s0, s31),
"ec860a20 vstmia r6, {s0-s31}");
COMPARE(vldm(ia, r7, s0, s31),
"ec970a20 vldmia r7, {s0-s31}");
Emit VMLA for multiply-add on ARM Review URL: https://chromiumcodereview.appspot.com/11293061 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@12958 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2012-11-14 11:01:18 +00:00
COMPARE(vmla(d2, d1, d0),
"ee012b00 vmla.f64 d2, d1, d0");
COMPARE(vmla(d6, d4, d5, cc),
ARM: Fix disassembly of some VFP instructions with condition codes Previously, we would disassemble some VFP instructions like this: vmla.f64eq d16, d17, d18 This patch moves the condition to the right place: vmlaeq.f64 d16, d17, d18 Spotted by Rodolph Perfetta! BUG=none Review URL: https://chromiumcodereview.appspot.com/12335129 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13752 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-02-27 11:52:45 +00:00
"3e046b05 vmlacc.f64 d6, d4, d5");
ARM: Make use of d16-d31 when available. Review URL: https://chromiumcodereview.appspot.com/11428137 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13484 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-01-23 16:29:48 +00:00
[turbofan] Add backend support for float32 operations. This adds the basics necessary to support float32 operations in TurboFan. The actual functionality required to detect safe float32 operations will be added based on this later. Therefore this does not affect production code except for some cleanup/refactoring. In detail, this patchset contains the following features: - Add support for float32 operations to arm, arm64, ia32 and x64 backends. - Add float32 machine operators. - Add support for float32 constants to simplified lowering. - Handle float32 representation for phis in simplified lowering. In addition, contains the following (related) cleanups: - Fix/unify naming of backend instructions. - Use AVX comparisons when available. - Extend ArchOpcodeField to 9 bits (required for arm64). - Refactor some code duplication in instruction selectors. BUG=v8:3589 LOG=n R=dcarney@chromium.org Review URL: https://codereview.chromium.org/1044793002 Cr-Commit-Position: refs/heads/master@{#27509}
2015-03-30 07:33:46 +00:00
COMPARE(vmla(s2, s1, s0),
"ee001a80 vmla.f32 s2, s1, s0");
COMPARE(vmla(s6, s4, s5, cc),
"3e023a22 vmlacc.f32 s6, s4, s5");
Emit VMLS for multiply-subtract on ARM. BUG=none Review URL: https://chromiumcodereview.appspot.com/12319113 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13748 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-02-27 10:24:40 +00:00
COMPARE(vmls(d2, d1, d0),
"ee012b40 vmls.f64 d2, d1, d0");
COMPARE(vmls(d6, d4, d5, cc),
ARM: Fix disassembly of some VFP instructions with condition codes Previously, we would disassemble some VFP instructions like this: vmla.f64eq d16, d17, d18 This patch moves the condition to the right place: vmlaeq.f64 d16, d17, d18 Spotted by Rodolph Perfetta! BUG=none Review URL: https://chromiumcodereview.appspot.com/12335129 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13752 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-02-27 11:52:45 +00:00
"3e046b45 vmlscc.f64 d6, d4, d5");
Emit VMLS for multiply-subtract on ARM. BUG=none Review URL: https://chromiumcodereview.appspot.com/12319113 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13748 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-02-27 10:24:40 +00:00
[turbofan] Add backend support for float32 operations. This adds the basics necessary to support float32 operations in TurboFan. The actual functionality required to detect safe float32 operations will be added based on this later. Therefore this does not affect production code except for some cleanup/refactoring. In detail, this patchset contains the following features: - Add support for float32 operations to arm, arm64, ia32 and x64 backends. - Add float32 machine operators. - Add support for float32 constants to simplified lowering. - Handle float32 representation for phis in simplified lowering. In addition, contains the following (related) cleanups: - Fix/unify naming of backend instructions. - Use AVX comparisons when available. - Extend ArchOpcodeField to 9 bits (required for arm64). - Refactor some code duplication in instruction selectors. BUG=v8:3589 LOG=n R=dcarney@chromium.org Review URL: https://codereview.chromium.org/1044793002 Cr-Commit-Position: refs/heads/master@{#27509}
2015-03-30 07:33:46 +00:00
COMPARE(vmls(s2, s1, s0),
"ee001ac0 vmls.f32 s2, s1, s0");
COMPARE(vmls(s6, s4, s5, cc),
"3e023a62 vmlscc.f32 s6, s4, s5");
[arm] Add several missing vcvt disassembly tests. BUG= Review URL: https://codereview.chromium.org/1678043002 Cr-Commit-Position: refs/heads/master@{#33811}
2016-02-08 11:45:17 +00:00
COMPARE(vcvt_f32_f64(s31, d15),
"eef7fbcf vcvt.f32.f64 s31, d15");
COMPARE(vcvt_f32_s32(s30, s29),
"eeb8faee vcvt.f32.s32 s30, s29");
COMPARE(vcvt_f64_f32(d14, s28),
"eeb7eace vcvt.f64.f32 d14, s28");
COMPARE(vcvt_f64_s32(d13, s27),
"eeb8dbed vcvt.f64.s32 d13, s27");
COMPARE(vcvt_f64_u32(d12, s26),
"eeb8cb4d vcvt.f64.u32 d12, s26");
COMPARE(vcvt_s32_f32(s25, s24),
"eefdcacc vcvt.s32.f32 s25, s24");
COMPARE(vcvt_s32_f64(s23, d11),
"eefdbbcb vcvt.s32.f64 s23, d11");
COMPARE(vcvt_u32_f32(s22, s21),
"eebcbaea vcvt.u32.f32 s22, s21");
COMPARE(vcvt_u32_f64(s20, d10),
"eebcabca vcvt.u32.f64 s20, d10");
COMPARE(vcvt_f64_s32(d9, 2),
"eeba9bcf vcvt.f64.s32 d9, d9, #2");
ARM: Make use of d16-d31 when available. Review URL: https://chromiumcodereview.appspot.com/11428137 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13484 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-01-23 16:29:48 +00:00
if (CpuFeatures::IsSupported(VFP32DREGS)) {
[arm] Clean up use of IsSupported and IsEnabled. CpuFeatures::IsSupported(feature) indicates that the feature is available on the target. AssemblerBase::IsEnabled(feature) indicates that we've checked for support (using CpuFeatureScope). The main benefit is that we can test on (for example) ARMv8, but have some assurance that we won't generate ARMv8 instructions on ARMv7 targets. This patch simply cleans up the usage, which had become inconsistent. The instruction emission functions now check not only that their dependent features are supported, but also that we've verified that using CpuFeatureScope. BUG= Review-Url: https://codereview.chromium.org/2360243002 Cr-Commit-Position: refs/heads/master@{#39676}
2016-09-23 15:29:11 +00:00
CpuFeatureScope scope(&assm, VFP32DREGS);
ARM: Make use of d16-d31 when available. Review URL: https://chromiumcodereview.appspot.com/11428137 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13484 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-01-23 16:29:48 +00:00
COMPARE(vmov(d3, d27),
"eeb03b6b vmov.f64 d3, d27");
COMPARE(vmov(d18, d7),
"eef02b47 vmov.f64 d18, d7");
COMPARE(vmov(d18, r2, r3),
"ec432b32 vmov d18, r2, r3");
COMPARE(vmov(r2, r3, d18),
"ec532b32 vmov r2, r3, d18");
COMPARE(vmov(d20, d31),
"eef04b6f vmov.f64 d20, d31");
COMPARE(vabs(d16, d31),
"eef00bef vabs.f64 d16, d31");
COMPARE(vneg(d16, d31),
"eef10b6f vneg.f64 d16, d31");
COMPARE(vadd(d16, d17, d18),
"ee710ba2 vadd.f64 d16, d17, d18");
COMPARE(vsub(d16, d17, d18),
"ee710be2 vsub.f64 d16, d17, d18");
COMPARE(vmul(d16, d17, d18),
"ee610ba2 vmul.f64 d16, d17, d18");
COMPARE(vdiv(d16, d17, d18),
"eec10ba2 vdiv.f64 d16, d17, d18");
COMPARE(vcmp(d16, d17),
"eef40b61 vcmp.f64 d16, d17");
COMPARE(vcmp(d16, 0.0),
"eef50b40 vcmp.f64 d16, #0.0");
COMPARE(vsqrt(d16, d17),
"eef10be1 vsqrt.f64 d16, d17");
[arm][turbofan] Pass double immediate to vmov as uint64_t On x86, signalling NaNs get converted to quiet NaNs when they get push on the stack and popped again. This happens in the code generation for arm, specifically for the vmov instruction with the immediate parameter. This CL replaces the vmov function in assembler-arm to take the immediate as a uint64_t instead of a double, to guarantee that the bit pattern does not change even if the parameter is a signalling NaN. BUG=v8:6564 Change-Id: I062559f9a7ba8b0f560628e5c39621ca578c3e7d Reviewed-on: https://chromium-review.googlesource.com/558964 Commit-Queue: Andreas Haas <ahaas@chromium.org> Reviewed-by: Ben Titzer <titzer@chromium.org> Reviewed-by: Martyn Capewell <martyn.capewell@arm.com> Cr-Commit-Position: refs/heads/master@{#46418}
2017-07-05 13:48:12 +00:00
COMPARE(vmov(d30, Double(16.0)),
ARM: Make use of d16-d31 when available. Review URL: https://chromiumcodereview.appspot.com/11428137 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13484 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-01-23 16:29:48 +00:00
"eef3eb00 vmov.f64 d30, #16");
[arm] Eliminate old form of core-scalar vmov instructions. - Eliminates less general forms of vmov between core and scalar FP registers. Bug: v8:7754 Change-Id: I3224c57e03dfd64ea6552b215017dacc357dda26 Reviewed-on: https://chromium-review.googlesource.com/1144126 Commit-Queue: Bill Budge <bbudge@chromium.org> Reviewed-by: Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#54663}
2018-07-24 16:56:27 +00:00
COMPARE(vmov(NeonS32, d31, 0, r7),
ARM: Make use of d16-d31 when available. Review URL: https://chromiumcodereview.appspot.com/11428137 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13484 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-01-23 16:29:48 +00:00
"ee0f7b90 vmov.32 d31[0], r7");
[arm] Eliminate old form of core-scalar vmov instructions. - Eliminates less general forms of vmov between core and scalar FP registers. Bug: v8:7754 Change-Id: I3224c57e03dfd64ea6552b215017dacc357dda26 Reviewed-on: https://chromium-review.googlesource.com/1144126 Commit-Queue: Bill Budge <bbudge@chromium.org> Reviewed-by: Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#54663}
2018-07-24 16:56:27 +00:00
COMPARE(vmov(NeonS32, d31, 1, r7),
ARM: Make use of d16-d31 when available. Review URL: https://chromiumcodereview.appspot.com/11428137 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13484 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-01-23 16:29:48 +00:00
"ee2f7b90 vmov.32 d31[1], r7");
COMPARE(vldr(d25, r0, 0),
"edd09b00 vldr d25, [r0 + 4*0]");
COMPARE(vldr(d26, r1, 4),
"edd1ab01 vldr d26, [r1 + 4*1]");
COMPARE(vldr(d31, r10, 1020),
"eddafbff vldr d31, [r10 + 4*255]");
COMPARE(vstr(d16, r0, 0),
"edc00b00 vstr d16, [r0 + 4*0]");
COMPARE(vstr(d17, r1, 4),
"edc11b01 vstr d17, [r1 + 4*1]");
COMPARE(vstr(d31, r10, 1020),
"edcafbff vstr d31, [r10 + 4*255]");
COMPARE(vstm(ia, r0, d16, d31),
"ecc00b20 vstmia r0, {d16-d31}");
COMPARE(vldm(ia, r3, d16, d31),
"ecd30b20 vldmia r3, {d16-d31}");
COMPARE(vstm(ia, r0, d23, d27),
"ecc07b0a vstmia r0, {d23-d27}");
COMPARE(vldm(ia, r3, d23, d27),
"ecd37b0a vldmia r3, {d23-d27}");
COMPARE(vmla(d16, d17, d18),
"ee410ba2 vmla.f64 d16, d17, d18");
[arm] Add several missing vcvt disassembly tests. BUG= Review URL: https://codereview.chromium.org/1678043002 Cr-Commit-Position: refs/heads/master@{#33811}
2016-02-08 11:45:17 +00:00
COMPARE(vcvt_f32_f64(s0, d31),
"eeb70bef vcvt.f32.f64 s0, d31");
COMPARE(vcvt_f32_s32(s1, s2),
"eef80ac1 vcvt.f32.s32 s1, s2");
COMPARE(vcvt_f64_f32(d30, s3),
"eef7eae1 vcvt.f64.f32 d30, s3");
COMPARE(vcvt_f64_s32(d29, s4),
"eef8dbc2 vcvt.f64.s32 d29, s4");
COMPARE(vcvt_f64_u32(d28, s5),
"eef8cb62 vcvt.f64.u32 d28, s5");
COMPARE(vcvt_s32_f32(s6, s7),
"eebd3ae3 vcvt.s32.f32 s6, s7");
COMPARE(vcvt_s32_f64(s8, d27),
"eebd4beb vcvt.s32.f64 s8, d27");
COMPARE(vcvt_u32_f32(s9, s10),
"eefc4ac5 vcvt.u32.f32 s9, s10");
COMPARE(vcvt_u32_f64(s11, d26),
"eefc5bea vcvt.u32.f64 s11, d26");
COMPARE(vcvt_f64_s32(d25, 2),
"eefa9bcf vcvt.f64.s32 d25, d25, #2");
ARM: Make use of d16-d31 when available. Review URL: https://chromiumcodereview.appspot.com/11428137 Patch from Hans Wennborg <hans@chromium.org>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13484 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-01-23 16:29:48 +00:00
}
ARM: Use the vsqrt instruction when available vsqrt is used to calculate Math.sqrt(x), Math.pow(x, 0.5) and Math.pow(x, -0.5). Code size doesn't matter, as %_MathSqrt and %_MathPow are only called in one place each. Review URL: http://codereview.chromium.org/2885002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4974 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-29 09:40:36 +00:00
}
VERIFY_RUN();
}
ARM: Fix disasm for strh, vabs, vneg. Add load/store tests. Patch from ARM Ltd. BUG=none TEST=added to test/cctest/test-disasm-arm.cc Original review at http://codereview.chromium.org/7013024/. Review URL: http://codereview.chromium.org/7013027 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7875 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-05-12 14:44:49 +00:00
Add vrint{a,n,p,m,z} instructions to arm assembler. These instructions are only available on ARMv8. R=rodolph.perfetta@gmail.com, ulan@chromium.org, bmeurer@chromium.org, rodolph.perfetta@arm.com Review URL: https://codereview.chromium.org/682643002 Cr-Commit-Position: refs/heads/master@{#25013} git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25013 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-10-30 11:00:47 +00:00
TEST(ARMv8_vrintX_disasm) {
SET_UP();
if (CpuFeatures::IsSupported(ARMv8)) {
[arm] Clean up use of IsSupported and IsEnabled. CpuFeatures::IsSupported(feature) indicates that the feature is available on the target. AssemblerBase::IsEnabled(feature) indicates that we've checked for support (using CpuFeatureScope). The main benefit is that we can test on (for example) ARMv8, but have some assurance that we won't generate ARMv8 instructions on ARMv7 targets. This patch simply cleans up the usage, which had become inconsistent. The instruction emission functions now check not only that their dependent features are supported, but also that we've verified that using CpuFeatureScope. BUG= Review-Url: https://codereview.chromium.org/2360243002 Cr-Commit-Position: refs/heads/master@{#39676}
2016-09-23 15:29:11 +00:00
CpuFeatureScope scope(&assm, ARMv8);
Add vrint{a,n,p,m,z} instructions to arm assembler. These instructions are only available on ARMv8. R=rodolph.perfetta@gmail.com, ulan@chromium.org, bmeurer@chromium.org, rodolph.perfetta@arm.com Review URL: https://codereview.chromium.org/682643002 Cr-Commit-Position: refs/heads/master@{#25013} git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25013 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-10-30 11:00:47 +00:00
COMPARE(vrinta(d0, d0), "feb80b40 vrinta.f64.f64 d0, d0");
COMPARE(vrinta(d2, d3), "feb82b43 vrinta.f64.f64 d2, d3");
COMPARE(vrintp(d0, d0), "feba0b40 vrintp.f64.f64 d0, d0");
COMPARE(vrintp(d2, d3), "feba2b43 vrintp.f64.f64 d2, d3");
COMPARE(vrintn(d0, d0), "feb90b40 vrintn.f64.f64 d0, d0");
COMPARE(vrintn(d2, d3), "feb92b43 vrintn.f64.f64 d2, d3");
COMPARE(vrintm(d0, d0), "febb0b40 vrintm.f64.f64 d0, d0");
COMPARE(vrintm(d2, d3), "febb2b43 vrintm.f64.f64 d2, d3");
COMPARE(vrintz(d0, d0), "eeb60bc0 vrintz.f64.f64 d0, d0");
COMPARE(vrintz(d2, d3, ne), "1eb62bc3 vrintzne.f64.f64 d2, d3");
}
VERIFY_RUN();
}
[arm] Add support for vminnm and vmaxnm. These are ARMv8 instructions that will be used in a follow-up patch. BUG= Review-Url: https://codereview.chromium.org/2273003002 Cr-Commit-Position: refs/heads/master@{#39193}
2016-09-06 08:46:17 +00:00
TEST(ARMv8_vminmax_disasm) {
SET_UP();
if (CpuFeatures::IsSupported(ARMv8)) {
[arm] Clean up use of IsSupported and IsEnabled. CpuFeatures::IsSupported(feature) indicates that the feature is available on the target. AssemblerBase::IsEnabled(feature) indicates that we've checked for support (using CpuFeatureScope). The main benefit is that we can test on (for example) ARMv8, but have some assurance that we won't generate ARMv8 instructions on ARMv7 targets. This patch simply cleans up the usage, which had become inconsistent. The instruction emission functions now check not only that their dependent features are supported, but also that we've verified that using CpuFeatureScope. BUG= Review-Url: https://codereview.chromium.org/2360243002 Cr-Commit-Position: refs/heads/master@{#39676}
2016-09-23 15:29:11 +00:00
CpuFeatureScope scope(&assm, ARMv8);
[arm] Add support for vminnm and vmaxnm. These are ARMv8 instructions that will be used in a follow-up patch. BUG= Review-Url: https://codereview.chromium.org/2273003002 Cr-Commit-Position: refs/heads/master@{#39193}
2016-09-06 08:46:17 +00:00
COMPARE(vmaxnm(d0, d1, d2), "fe810b02 vmaxnm.f64 d0, d1, d2");
COMPARE(vminnm(d3, d4, d5), "fe843b45 vminnm.f64 d3, d4, d5");
COMPARE(vmaxnm(s6, s7, s8), "fe833a84 vmaxnm.f32 s6, s7, s8");
COMPARE(vminnm(s9, s10, s11), "fec54a65 vminnm.f32 s9, s10, s11");
}
VERIFY_RUN();
}
[arm] Implement Float(32|64)(Min|Max) using vsel. BUG= Review URL: https://codereview.chromium.org/1862993002 Cr-Commit-Position: refs/heads/master@{#35292}
2016-04-06 10:17:14 +00:00
TEST(ARMv8_vselX_disasm) {
SET_UP();
if (CpuFeatures::IsSupported(ARMv8)) {
[arm] Clean up use of IsSupported and IsEnabled. CpuFeatures::IsSupported(feature) indicates that the feature is available on the target. AssemblerBase::IsEnabled(feature) indicates that we've checked for support (using CpuFeatureScope). The main benefit is that we can test on (for example) ARMv8, but have some assurance that we won't generate ARMv8 instructions on ARMv7 targets. This patch simply cleans up the usage, which had become inconsistent. The instruction emission functions now check not only that their dependent features are supported, but also that we've verified that using CpuFeatureScope. BUG= Review-Url: https://codereview.chromium.org/2360243002 Cr-Commit-Position: refs/heads/master@{#39676}
2016-09-23 15:29:11 +00:00
CpuFeatureScope scope(&assm, ARMv8);
[arm] Implement Float(32|64)(Min|Max) using vsel. BUG= Review URL: https://codereview.chromium.org/1862993002 Cr-Commit-Position: refs/heads/master@{#35292}
2016-04-06 10:17:14 +00:00
// Native instructions.
COMPARE(vsel(eq, d0, d1, d2),
"fe010b02 vseleq.f64 d0, d1, d2");
COMPARE(vsel(eq, s0, s1, s2),
"fe000a81 vseleq.f32 s0, s1, s2");
COMPARE(vsel(ge, d0, d1, d2),
"fe210b02 vselge.f64 d0, d1, d2");
COMPARE(vsel(ge, s0, s1, s2),
"fe200a81 vselge.f32 s0, s1, s2");
COMPARE(vsel(gt, d0, d1, d2),
"fe310b02 vselgt.f64 d0, d1, d2");
COMPARE(vsel(gt, s0, s1, s2),
"fe300a81 vselgt.f32 s0, s1, s2");
COMPARE(vsel(vs, d0, d1, d2),
"fe110b02 vselvs.f64 d0, d1, d2");
COMPARE(vsel(vs, s0, s1, s2),
"fe100a81 vselvs.f32 s0, s1, s2");
// Inverted conditions (and swapped inputs).
COMPARE(vsel(ne, d0, d1, d2),
"fe020b01 vseleq.f64 d0, d2, d1");
COMPARE(vsel(ne, s0, s1, s2),
"fe010a20 vseleq.f32 s0, s2, s1");
COMPARE(vsel(lt, d0, d1, d2),
"fe220b01 vselge.f64 d0, d2, d1");
COMPARE(vsel(lt, s0, s1, s2),
"fe210a20 vselge.f32 s0, s2, s1");
COMPARE(vsel(le, d0, d1, d2),
"fe320b01 vselgt.f64 d0, d2, d1");
COMPARE(vsel(le, s0, s1, s2),
"fe310a20 vselgt.f32 s0, s2, s1");
COMPARE(vsel(vc, d0, d1, d2),
"fe120b01 vselvs.f64 d0, d2, d1");
COMPARE(vsel(vc, s0, s1, s2),
"fe110a20 vselvs.f32 s0, s2, s1");
}
VERIFY_RUN();
}
ARM: Implement memcpy using NEON. Add support for a few NEON and ARM SIMD instructions and use them for various memcpy operations. BUG=none TEST=none Review URL: https://chromiumcodereview.appspot.com/17858002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15602 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-07-10 15:32:39 +00:00
TEST(Neon) {
SET_UP();
if (CpuFeatures::IsSupported(NEON)) {
CpuFeatureScope scope(&assm, NEON);
COMPARE(vld1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(r1)),
"f421420f vld1.8 {d4, d5, d6, d7}, [r1]");
COMPARE(vst1(Neon16, NeonListOperand(d17, 4), NeonMemOperand(r9)),
"f449124f vst1.16 {d17, d18, d19, d20}, [r9]");
[ARM] Implement widening and narrowing integer moves, vmovl, vqmovn. - Fixes vmovl for widening 16 to 32, 32 to 64. - Adds vqmovn. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2773303002 Cr-Commit-Position: refs/heads/master@{#44156}
2017-03-27 18:23:42 +00:00
COMPARE(vmovl(NeonU8, q3, d1), "f3886a11 vmovl.u8 q3, d1");
COMPARE(vmovl(NeonU8, q4, d2), "f3888a12 vmovl.u8 q4, d2");
COMPARE(vmovl(NeonS16, q4, d2), "f2908a12 vmovl.s16 q4, d2");
COMPARE(vmovl(NeonU32, q4, d2), "f3a08a12 vmovl.u32 q4, d2");
COMPARE(vqmovn(NeonU8, d16, q8), "f3f202e0 vqmovn.u16 d16, q8");
COMPARE(vqmovn(NeonS16, d16, q8), "f3f602a0 vqmovn.s32 d16, q8");
COMPARE(vqmovn(NeonU32, d2, q4), "f3ba22c8 vqmovn.u64 d2, q4");
[Turbofan] Add ARM NEON instructions for implementing SIMD. - Adds NEON instructions to assembler, disassembler, simulator. - Adds ExtractLane, ReplaceLane functions to macro assembler. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2546933002 Cr-Commit-Position: refs/heads/master@{#41737}
2016-12-15 18:15:23 +00:00
COMPARE(vmov(NeonS8, d0, 0, r0), "ee400b10 vmov.8 d0[0], r0");
COMPARE(vmov(NeonU8, d1, 1, r1), "ee411b30 vmov.8 d1[1], r1");
COMPARE(vmov(NeonS8, d2, 2, r2), "ee422b50 vmov.8 d2[2], r2");
COMPARE(vmov(NeonU8, d3, 3, r8), "ee438b70 vmov.8 d3[3], r8");
[arm] Use the converter when printing general registers When disassembling some instructions we would print `r12`, which can be confusing when the rest of the disassembly consistently uses `ip`. Bug: Change-Id: Id4cfc5805ef102a0845cdaaa8390e618ee981b19 Reviewed-on: https://chromium-review.googlesource.com/570038 Reviewed-by: Georg Neis <neis@chromium.org> Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Cr-Commit-Position: refs/heads/master@{#46628}
2017-07-13 10:07:46 +00:00
COMPARE(vmov(NeonU8, d3, 3, ip), "ee43cb70 vmov.8 d3[3], ip");
[Turbofan] Add ARM NEON instructions for implementing SIMD. - Adds NEON instructions to assembler, disassembler, simulator. - Adds ExtractLane, ReplaceLane functions to macro assembler. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2546933002 Cr-Commit-Position: refs/heads/master@{#41737}
2016-12-15 18:15:23 +00:00
COMPARE(vmov(NeonS8, d4, 4, r0), "ee640b10 vmov.8 d4[4], r0");
COMPARE(vmov(NeonU8, d5, 5, r1), "ee651b30 vmov.8 d5[5], r1");
COMPARE(vmov(NeonS8, d6, 6, r2), "ee662b50 vmov.8 d6[6], r2");
COMPARE(vmov(NeonU8, d7, 7, r8), "ee678b70 vmov.8 d7[7], r8");
COMPARE(vmov(NeonS16, d0, 0, r0), "ee000b30 vmov.16 d0[0], r0");
COMPARE(vmov(NeonS16, d1, 1, r1), "ee011b70 vmov.16 d1[1], r1");
COMPARE(vmov(NeonS16, d2, 2, r2), "ee222b30 vmov.16 d2[2], r2");
COMPARE(vmov(NeonS16, d3, 3, r7), "ee237b70 vmov.16 d3[3], r7");
[arm] Use the converter when printing general registers When disassembling some instructions we would print `r12`, which can be confusing when the rest of the disassembly consistently uses `ip`. Bug: Change-Id: Id4cfc5805ef102a0845cdaaa8390e618ee981b19 Reviewed-on: https://chromium-review.googlesource.com/570038 Reviewed-by: Georg Neis <neis@chromium.org> Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Cr-Commit-Position: refs/heads/master@{#46628}
2017-07-13 10:07:46 +00:00
COMPARE(vmov(NeonS16, d3, 3, ip), "ee23cb70 vmov.16 d3[3], ip");
[Turbofan] Add ARM NEON instructions for implementing SIMD. - Adds NEON instructions to assembler, disassembler, simulator. - Adds ExtractLane, ReplaceLane functions to macro assembler. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2546933002 Cr-Commit-Position: refs/heads/master@{#41737}
2016-12-15 18:15:23 +00:00
COMPARE(vmov(NeonS32, d0, 0, r0), "ee000b10 vmov.32 d0[0], r0");
COMPARE(vmov(NeonU32, d0, 1, r0), "ee200b10 vmov.32 d0[1], r0");
COMPARE(vmov(NeonS8, r0, d0, 0), "ee500b10 vmov.s8 r0, d0[0]");
COMPARE(vmov(NeonU8, r1, d1, 1), "eed11b30 vmov.u8 r1, d1[1]");
COMPARE(vmov(NeonS8, r2, d2, 2), "ee522b50 vmov.s8 r2, d2[2]");
COMPARE(vmov(NeonU8, r8, d3, 3), "eed38b70 vmov.u8 r8, d3[3]");
COMPARE(vmov(NeonS8, r0, d4, 4), "ee740b10 vmov.s8 r0, d4[4]");
COMPARE(vmov(NeonU8, r1, d5, 5), "eef51b30 vmov.u8 r1, d5[5]");
COMPARE(vmov(NeonS8, r2, d6, 6), "ee762b50 vmov.s8 r2, d6[6]");
COMPARE(vmov(NeonU8, r8, d7, 7), "eef78b70 vmov.u8 r8, d7[7]");
[arm] Use the converter when printing general registers When disassembling some instructions we would print `r12`, which can be confusing when the rest of the disassembly consistently uses `ip`. Bug: Change-Id: Id4cfc5805ef102a0845cdaaa8390e618ee981b19 Reviewed-on: https://chromium-review.googlesource.com/570038 Reviewed-by: Georg Neis <neis@chromium.org> Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Cr-Commit-Position: refs/heads/master@{#46628}
2017-07-13 10:07:46 +00:00
COMPARE(vmov(NeonU8, ip, d7, 7), "eef7cb70 vmov.u8 ip, d7[7]");
[Turbofan] Add ARM NEON instructions for implementing SIMD. - Adds NEON instructions to assembler, disassembler, simulator. - Adds ExtractLane, ReplaceLane functions to macro assembler. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2546933002 Cr-Commit-Position: refs/heads/master@{#41737}
2016-12-15 18:15:23 +00:00
COMPARE(vmov(NeonS16, r0, d0, 0), "ee100b30 vmov.s16 r0, d0[0]");
COMPARE(vmov(NeonU16, r1, d1, 1), "ee911b70 vmov.u16 r1, d1[1]");
COMPARE(vmov(NeonS16, r2, d2, 2), "ee322b30 vmov.s16 r2, d2[2]");
COMPARE(vmov(NeonU16, r7, d3, 3), "eeb37b70 vmov.u16 r7, d3[3]");
COMPARE(vmov(NeonS32, r2, d15, 0), "ee1f2b10 vmov.32 r2, d15[0]");
COMPARE(vmov(NeonS32, r3, d14, 1), "ee3e3b10 vmov.32 r3, d14[1]");
[Turbofan] Add ARM support for simd128 moves and swaps. - Adds vmov, vswp instructions for QwNeonRegisters. - Refactors existing vswp implementation, moves non-Neon adaption to MacroAssembler. - Adds simd128 support to CodeGenerator AssembleMove, AssembleSwap. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2523933002 Cr-Commit-Position: refs/heads/master@{#41291}
2016-11-25 19:36:45 +00:00
COMPARE(vmov(q0, q15),
"f22e01fe vmov q0, q15");
COMPARE(vmov(q8, q9),
"f26201f2 vmov q8, q9");
[Turbofan] Add ARM NEON instructions for implementing SIMD. - Adds NEON instructions to assembler, disassembler, simulator. - Adds ExtractLane, ReplaceLane functions to macro assembler. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2546933002 Cr-Commit-Position: refs/heads/master@{#41737}
2016-12-15 18:15:23 +00:00
COMPARE(vmvn(q0, q15),
"f3b005ee vmvn q0, q15");
COMPARE(vmvn(q8, q9),
"f3f005e2 vmvn q8, q9");
Reland of [turbofan] ARM: Implement vswp and use in gap resolver Reason for revert: Breaks g++ build. Original issue's description: > [turbofan] ARM: Implement vswp and use in gap resolver > > Use vswp to switch double-precision registers in the gap resolver, with fall > back temp register-based code if NEON is not available. > > BUG= > > Committed: https://crrev.com/2837c2e65a2ee5b9fc610f30ce1215f52323ecbd > Cr-Commit-Position: refs/heads/master@{#39209} BUG= Review-Url: https://codereview.chromium.org/2314043002 Cr-Commit-Position: refs/heads/master@{#39264}
2016-09-08 07:11:32 +00:00
COMPARE(vswp(d0, d31),
"f3b2002f vswp d0, d31");
COMPARE(vswp(d16, d14),
"f3f2000e vswp d16, d14");
[Turbofan] Add ARM support for simd128 moves and swaps. - Adds vmov, vswp instructions for QwNeonRegisters. - Refactors existing vswp implementation, moves non-Neon adaption to MacroAssembler. - Adds simd128 support to CodeGenerator AssembleMove, AssembleSwap. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2523933002 Cr-Commit-Position: refs/heads/master@{#41291}
2016-11-25 19:36:45 +00:00
COMPARE(vswp(q0, q15),
"f3b2006e vswp q0, q15");
COMPARE(vswp(q8, q9),
"f3f20062 vswp q8, q9");
[Turbofan] Add ARM NEON instructions for implementing SIMD. - Adds NEON instructions to assembler, disassembler, simulator. - Adds ExtractLane, ReplaceLane functions to macro assembler. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2546933002 Cr-Commit-Position: refs/heads/master@{#41737}
2016-12-15 18:15:23 +00:00
COMPARE(vdup(Neon8, q0, r0),
"eee00b10 vdup.8 q0, r0");
COMPARE(vdup(Neon16, q1, r4),
"eea24b30 vdup.16 q1, r4");
COMPARE(vdup(Neon32, q15, r1),
"eeae1b90 vdup.32 q15, r1");
[ARM] Improve VFP register moves. - Adds vdup.<size> Dd/Qd, Dm[i] instruction. - Adds vsli, vsri instructions. - Changes VMovExtended to use these to avoid moves to core registers. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2868603002 Cr-Commit-Position: refs/heads/master@{#45351}
2017-05-16 20:37:16 +00:00
COMPARE(vdup(Neon32, q0, d1, 1),
"f3bc0c41 vdup.32 q0, d1[1]");
COMPARE(vdup(Neon32, q15, d1, 0),
"f3f4ec41 vdup.32 q15, d1[0]");
COMPARE(vdup(Neon16, q7, d8, 3),
"f3beec48 vdup.16 q7, d8[3]");
COMPARE(vdup(Neon32, d0, d30, 0),
"f3b40c2e vdup.32 d0, d30[0]");
[Turbofan] Add ARM NEON instructions for implementing SIMD. - Adds NEON instructions to assembler, disassembler, simulator. - Adds ExtractLane, ReplaceLane functions to macro assembler. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2546933002 Cr-Commit-Position: refs/heads/master@{#41737}
2016-12-15 18:15:23 +00:00
COMPARE(vcvt_f32_s32(q15, q1),
"f3fbe642 vcvt.f32.s32 q15, q1");
COMPARE(vcvt_f32_u32(q8, q9),
"f3fb06e2 vcvt.f32.u32 q8, q9");
COMPARE(vcvt_s32_f32(q15, q1),
"f3fbe742 vcvt.s32.f32 q15, q1");
COMPARE(vcvt_u32_f32(q8, q9),
"f3fb07e2 vcvt.u32.f32 q8, q9");
[ARM] Add NEON instructions for implementing SIMD. - Adds vabs, vneg, vmul, vext, vzip, vrev instructions. - Adds Swizzle function to macro assembler. - Simplifies if-else logic in disassembler, simulator, for Neon special. - Some refactoring of Neon assembler, macro-assembler tests. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2579913002 Cr-Commit-Position: refs/heads/master@{#41781}
2016-12-17 21:56:26 +00:00
COMPARE(vabs(q0, q1),
"f3b90742 vabs.f32 q0, q1");
COMPARE(vabs(Neon8, q6, q7),
"f3b1c34e vabs.s8 q6, q7");
COMPARE(vabs(Neon16, q0, q1),
"f3b50342 vabs.s16 q0, q1");
COMPARE(vabs(Neon32, q0, q1),
"f3b90342 vabs.s32 q0, q1");
COMPARE(vneg(q0, q1),
"f3b907c2 vneg.f32 q0, q1");
COMPARE(vneg(Neon8, q6, q7),
"f3b1c3ce vneg.s8 q6, q7");
COMPARE(vneg(Neon16, q0, q1),
"f3b503c2 vneg.s16 q0, q1");
COMPARE(vneg(Neon32, q0, q1),
"f3b903c2 vneg.s32 q0, q1");
[Turbofan] Add ARM support for simd128 moves and swaps. - Adds vmov, vswp instructions for QwNeonRegisters. - Refactors existing vswp implementation, moves non-Neon adaption to MacroAssembler. - Adds simd128 support to CodeGenerator AssembleMove, AssembleSwap. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2523933002 Cr-Commit-Position: refs/heads/master@{#41291}
2016-11-25 19:36:45 +00:00
COMPARE(veor(d0, d1, d2),
"f3010112 veor d0, d1, d2");
COMPARE(veor(d0, d30, d31),
"f30e01bf veor d0, d30, d31");
COMPARE(veor(q0, q1, q2),
"f3020154 veor q0, q1, q2");
COMPARE(veor(q15, q0, q8),
"f340e170 veor q15, q0, q8");
[ARM] Add vand, vorr NEON instructions. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2620343002 Cr-Commit-Position: refs/heads/master@{#42273}
2017-01-12 15:36:29 +00:00
COMPARE(vand(q15, q0, q8),
"f240e170 vand q15, q0, q8");
COMPARE(vorr(q15, q0, q8),
"f260e170 vorr q15, q0, q8");
[ARM] Add vmin, vmax NEON instructions. - Adds vmin, vmax for FP and integer vectors, both signed and unsigned. - Regularizes switching logic in disasm and simulator for special codes 4 and 6. - Factors vrecpe, vrsqrte, vrecps, vrsqrts into helper fns. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2623993006 Cr-Commit-Position: refs/heads/master@{#42385}
2017-01-16 19:36:25 +00:00
COMPARE(vmin(q15, q0, q8),
"f260ef60 vmin.f32 q15, q0, q8");
COMPARE(vmax(q15, q0, q8),
"f240ef60 vmax.f32 q15, q0, q8");
COMPARE(vmax(NeonS8, q0, q1, q2),
"f2020644 vmax.s8 q0, q1, q2");
COMPARE(vmin(NeonU16, q1, q2, q8),
"f3142670 vmin.u16 q1, q2, q8");
COMPARE(vmax(NeonS32, q15, q0, q8),
"f260e660 vmax.s32 q15, q0, q8");
[WASM SIMD] Implement horizontal add for float and integer types. - Adds new F32x4AddHoriz, I32x4AddHoriz, etc. to WASM opcodes. - Implements them for ARM. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2804883008 Cr-Commit-Position: refs/heads/master@{#44812}
2017-04-24 18:53:16 +00:00
COMPARE(vpadd(d0, d1, d2),
"f3010d02 vpadd.f32 d0, d1, d2");
COMPARE(vpadd(Neon8, d0, d1, d2),
"f2010b12 vpadd.i8 d0, d1, d2");
COMPARE(vpadd(Neon16, d0, d1, d2),
"f2110b12 vpadd.i16 d0, d1, d2");
COMPARE(vpadd(Neon32, d0, d1, d2),
"f2210b12 vpadd.i32 d0, d1, d2");
Implement remaining Boolean SIMD operations on ARM. - Implements Select instructions using a single ARM vbsl instruction. - Renames boolean machine operators to match renamed S1xN machine types. - Implements S1xN vector logical ops, AND, OR, XOR, NOT for ARM. - Implements S1xN AnyTrue, AllTrue ops for ARM. - Eliminates unused SIMD op categories in opcodes.h. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2711863002 Cr-Commit-Position: refs/heads/master@{#43556}
2017-03-02 19:50:33 +00:00
COMPARE(vpmax(NeonS8, d0, d1, d2),
"f2010a02 vpmax.s8 d0, d1, d2");
COMPARE(vpmin(NeonU16, d1, d2, d8),
"f3121a18 vpmin.u16 d1, d2, d8");
COMPARE(vpmax(NeonS32, d15, d0, d8),
"f220fa08 vpmax.s32 d15, d0, d8");
[Turbofan] Add ARM NEON instructions for implementing SIMD. - Adds NEON instructions to assembler, disassembler, simulator. - Adds ExtractLane, ReplaceLane functions to macro assembler. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2546933002 Cr-Commit-Position: refs/heads/master@{#41737}
2016-12-15 18:15:23 +00:00
COMPARE(vadd(q15, q0, q8),
"f240ed60 vadd.f32 q15, q0, q8");
COMPARE(vadd(Neon8, q0, q1, q2),
"f2020844 vadd.i8 q0, q1, q2");
COMPARE(vadd(Neon16, q1, q2, q8),
"f2142860 vadd.i16 q1, q2, q8");
COMPARE(vadd(Neon32, q15, q0, q8),
"f260e860 vadd.i32 q15, q0, q8");
[ARM] Add Neon saturating add and subtract instructions. - Adds vqadd.s/u, vqsub.s/u for all integer lane sizes. - Refactors disassembler and simulator, using switches instead of long if-else chains. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2649323012 Cr-Commit-Position: refs/heads/master@{#42865}
2017-02-01 18:56:28 +00:00
COMPARE(vqadd(NeonU8, q0, q1, q2),
"f3020054 vqadd.u8 q0, q1, q2");
COMPARE(vqadd(NeonS16, q1, q2, q8),
"f2142070 vqadd.s16 q1, q2, q8");
COMPARE(vqadd(NeonU32, q15, q0, q8),
"f360e070 vqadd.u32 q15, q0, q8");
[Turbofan] Add ARM NEON instructions for implementing SIMD. - Adds NEON instructions to assembler, disassembler, simulator. - Adds ExtractLane, ReplaceLane functions to macro assembler. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2546933002 Cr-Commit-Position: refs/heads/master@{#41737}
2016-12-15 18:15:23 +00:00
COMPARE(vsub(q15, q0, q8),
"f260ed60 vsub.f32 q15, q0, q8");
COMPARE(vsub(Neon8, q0, q1, q2),
"f3020844 vsub.i8 q0, q1, q2");
COMPARE(vsub(Neon16, q1, q2, q8),
"f3142860 vsub.i16 q1, q2, q8");
COMPARE(vsub(Neon32, q15, q0, q8),
"f360e860 vsub.i32 q15, q0, q8");
[ARM] Add Neon saturating add and subtract instructions. - Adds vqadd.s/u, vqsub.s/u for all integer lane sizes. - Refactors disassembler and simulator, using switches instead of long if-else chains. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2649323012 Cr-Commit-Position: refs/heads/master@{#42865}
2017-02-01 18:56:28 +00:00
COMPARE(vqsub(NeonU8, q0, q1, q2),
"f3020254 vqsub.u8 q0, q1, q2");
COMPARE(vqsub(NeonS16, q1, q2, q8),
"f2142270 vqsub.s16 q1, q2, q8");
COMPARE(vqsub(NeonU32, q15, q0, q8),
"f360e270 vqsub.u32 q15, q0, q8");
[ARM] Add NEON instructions for implementing SIMD. - Adds vabs, vneg, vmul, vext, vzip, vrev instructions. - Adds Swizzle function to macro assembler. - Simplifies if-else logic in disassembler, simulator, for Neon special. - Some refactoring of Neon assembler, macro-assembler tests. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2579913002 Cr-Commit-Position: refs/heads/master@{#41781}
2016-12-17 21:56:26 +00:00
COMPARE(vmul(q0, q1, q2),
"f3020d54 vmul.f32 q0, q1, q2");
COMPARE(vmul(Neon8, q0, q1, q2),
"f2020954 vmul.i8 q0, q1, q2");
COMPARE(vmul(Neon16, q1, q2, q8),
"f2142970 vmul.i16 q1, q2, q8");
COMPARE(vmul(Neon32, q15, q0, q8),
"f260e970 vmul.i32 q15, q0, q8");
[ARM] Add Neon shift instructions vshl, vshr. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2629223005 Cr-Commit-Position: refs/heads/master@{#42610}
2017-01-23 18:24:27 +00:00
COMPARE(vshl(NeonS8, q15, q0, 6),
"f2cee550 vshl.i8 q15, q0, #6");
COMPARE(vshl(NeonU16, q15, q0, 10),
"f2dae550 vshl.i16 q15, q0, #10");
COMPARE(vshl(NeonS32, q15, q0, 17),
"f2f1e550 vshl.i32 q15, q0, #17");
COMPARE(vshr(NeonS8, q15, q0, 6),
"f2cae050 vshr.s8 q15, q0, #6");
COMPARE(vshr(NeonU16, q15, q0, 10),
"f3d6e050 vshr.u16 q15, q0, #10");
COMPARE(vshr(NeonS32, q15, q0, 17),
"f2efe050 vshr.s32 q15, q0, #17");
[ARM] Improve VFP register moves. - Adds vdup.<size> Dd/Qd, Dm[i] instruction. - Adds vsli, vsri instructions. - Changes VMovExtended to use these to avoid moves to core registers. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2868603002 Cr-Commit-Position: refs/heads/master@{#45351}
2017-05-16 20:37:16 +00:00
COMPARE(vsli(Neon64, d2, d0, 32),
"f3a02590 vsli.64 d2, d0, #32");
COMPARE(vsli(Neon32, d7, d8, 17),
"f3b17518 vsli.32 d7, d8, #17");
COMPARE(vsri(Neon64, d2, d0, 32),
"f3a02490 vsri.64 d2, d0, #32");
COMPARE(vsri(Neon16, d7, d8, 8),
"f3987418 vsri.16 d7, d8, #8");
[ARM] Add vrecpe, vrecps, vrsqrte, vrsqrts instructions to assembler. - Disassembler, simulator support too. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2600153002 Cr-Commit-Position: refs/heads/master@{#42176}
2017-01-10 12:36:59 +00:00
COMPARE(vrecpe(q15, q0),
"f3fbe540 vrecpe.f32 q15, q0");
COMPARE(vrecps(q15, q0, q8),
"f240ef70 vrecps.f32 q15, q0, q8");
COMPARE(vrsqrte(q15, q0),
"f3fbe5c0 vrsqrte.f32 q15, q0");
COMPARE(vrsqrts(q15, q0, q8),
"f260ef70 vrsqrts.f32 q15, q0, q8");
[Turbofan] Add ARM NEON instructions for implementing SIMD. - Adds NEON instructions to assembler, disassembler, simulator. - Adds ExtractLane, ReplaceLane functions to macro assembler. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2546933002 Cr-Commit-Position: refs/heads/master@{#41737}
2016-12-15 18:15:23 +00:00
COMPARE(vtst(Neon8, q0, q1, q2),
"f2020854 vtst.i8 q0, q1, q2");
COMPARE(vtst(Neon16, q1, q2, q8),
"f2142870 vtst.i16 q1, q2, q8");
COMPARE(vtst(Neon32, q15, q0, q8),
"f260e870 vtst.i32 q15, q0, q8");
[ARM] Add fp version of vceq to assembler, disassembler, and simulator. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2593443002 Cr-Commit-Position: refs/heads/master@{#41859}
2016-12-20 13:06:58 +00:00
COMPARE(vceq(q0, q1, q2),
"f2020e44 vceq.f32 q0, q1, q2");
[ARM] Add vcge, vcgt instructions to assembler. - Floating point, signed, and unsigned. - Disassembler, simulator support too. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2602293002 Cr-Commit-Position: refs/heads/master@{#42262}
2017-01-12 11:20:08 +00:00
COMPARE(vcge(q0, q1, q2),
"f3020e44 vcge.f32 q0, q1, q2");
COMPARE(vcgt(q0, q1, q2),
"f3220e44 vcgt.f32 q0, q1, q2");
[Turbofan] Add ARM NEON instructions for implementing SIMD. - Adds NEON instructions to assembler, disassembler, simulator. - Adds ExtractLane, ReplaceLane functions to macro assembler. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2546933002 Cr-Commit-Position: refs/heads/master@{#41737}
2016-12-15 18:15:23 +00:00
COMPARE(vceq(Neon8, q0, q1, q2),
"f3020854 vceq.i8 q0, q1, q2");
COMPARE(vceq(Neon16, q1, q2, q8),
"f3142870 vceq.i16 q1, q2, q8");
COMPARE(vceq(Neon32, q15, q0, q8),
"f360e870 vceq.i32 q15, q0, q8");
[ARM] Add vcge, vcgt instructions to assembler. - Floating point, signed, and unsigned. - Disassembler, simulator support too. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2602293002 Cr-Commit-Position: refs/heads/master@{#42262}
2017-01-12 11:20:08 +00:00
COMPARE(vcge(NeonS8, q0, q1, q2),
"f2020354 vcge.s8 q0, q1, q2");
COMPARE(vcge(NeonU16, q1, q2, q8),
"f3142370 vcge.u16 q1, q2, q8");
COMPARE(vcge(NeonS32, q15, q0, q8),
"f260e370 vcge.s32 q15, q0, q8");
COMPARE(vcgt(NeonS8, q0, q1, q2),
"f2020344 vcgt.s8 q0, q1, q2");
COMPARE(vcgt(NeonU16, q1, q2, q8),
"f3142360 vcgt.u16 q1, q2, q8");
COMPARE(vcgt(NeonS32, q15, q0, q8),
"f260e360 vcgt.s32 q15, q0, q8");
[Turbofan] Add ARM NEON instructions for implementing SIMD. - Adds NEON instructions to assembler, disassembler, simulator. - Adds ExtractLane, ReplaceLane functions to macro assembler. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2546933002 Cr-Commit-Position: refs/heads/master@{#41737}
2016-12-15 18:15:23 +00:00
COMPARE(vbsl(q0, q1, q2),
"f3120154 vbsl q0, q1, q2");
COMPARE(vbsl(q15, q0, q8),
"f350e170 vbsl q15, q0, q8");
[ARM] Add NEON instructions for implementing SIMD. - Adds vabs, vneg, vmul, vext, vzip, vrev instructions. - Adds Swizzle function to macro assembler. - Simplifies if-else logic in disassembler, simulator, for Neon special. - Some refactoring of Neon assembler, macro-assembler tests. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2579913002 Cr-Commit-Position: refs/heads/master@{#41781}
2016-12-17 21:56:26 +00:00
COMPARE(vext(q15, q0, q8, 3),
"f2f0e360 vext.8 q15, q0, q8, #3");
[ARM] Implement D-register versions of vzip, vuzp, and vtrn. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2797923006 Cr-Original-Commit-Position: refs/heads/master@{#44536} Committed: https://chromium.googlesource.com/v8/v8/+/6588187ae3acaa5b40762c539ee9fe355551bea3 Review-Url: https://codereview.chromium.org/2797923006 Cr-Commit-Position: refs/heads/master@{#44540}
2017-04-10 21:41:02 +00:00
COMPARE(vzip(Neon16, d15, d0),
"f3b6f180 vzip.16 d15, d0");
[ARM] Add NEON instructions for implementing SIMD. - Adds vabs, vneg, vmul, vext, vzip, vrev instructions. - Adds Swizzle function to macro assembler. - Simplifies if-else logic in disassembler, simulator, for Neon special. - Some refactoring of Neon assembler, macro-assembler tests. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2579913002 Cr-Commit-Position: refs/heads/master@{#41781}
2016-12-17 21:56:26 +00:00
COMPARE(vzip(Neon16, q15, q0),
"f3f6e1c0 vzip.16 q15, q0");
[ARM] Implement D-register versions of vzip, vuzp, and vtrn. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2797923006 Cr-Original-Commit-Position: refs/heads/master@{#44536} Committed: https://chromium.googlesource.com/v8/v8/+/6588187ae3acaa5b40762c539ee9fe355551bea3 Review-Url: https://codereview.chromium.org/2797923006 Cr-Commit-Position: refs/heads/master@{#44540}
2017-04-10 21:41:02 +00:00
COMPARE(vuzp(Neon16, d15, d0),
"f3b6f100 vuzp.16 d15, d0");
[ARM] Implement more NEON permutation instructions. - Implements vuzp, vtrn instructions for q-registers. - Refactors vmvn, vswp to use common unary op helper fn. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2739033002 Cr-Commit-Position: refs/heads/master@{#43795}
2017-03-14 16:28:45 +00:00
COMPARE(vuzp(Neon16, q15, q0),
"f3f6e140 vuzp.16 q15, q0");
[ARM] Add NEON instructions for implementing SIMD. - Adds vabs, vneg, vmul, vext, vzip, vrev instructions. - Adds Swizzle function to macro assembler. - Simplifies if-else logic in disassembler, simulator, for Neon special. - Some refactoring of Neon assembler, macro-assembler tests. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2579913002 Cr-Commit-Position: refs/heads/master@{#41781}
2016-12-17 21:56:26 +00:00
COMPARE(vrev64(Neon8, q15, q0),
"f3f0e040 vrev64.8 q15, q0");
[ARM] Implement D-register versions of vzip, vuzp, and vtrn. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2797923006 Cr-Original-Commit-Position: refs/heads/master@{#44536} Committed: https://chromium.googlesource.com/v8/v8/+/6588187ae3acaa5b40762c539ee9fe355551bea3 Review-Url: https://codereview.chromium.org/2797923006 Cr-Commit-Position: refs/heads/master@{#44540}
2017-04-10 21:41:02 +00:00
COMPARE(vtrn(Neon16, d15, d0),
"f3b6f080 vtrn.16 d15, d0");
[ARM] Implement more NEON permutation instructions. - Implements vuzp, vtrn instructions for q-registers. - Refactors vmvn, vswp to use common unary op helper fn. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2739033002 Cr-Commit-Position: refs/heads/master@{#43795}
2017-03-14 16:28:45 +00:00
COMPARE(vtrn(Neon16, q15, q0),
"f3f6e0c0 vtrn.16 q15, q0");
[Turbofan] Add ARM NEON instructions for implementing SIMD. - Adds NEON instructions to assembler, disassembler, simulator. - Adds ExtractLane, ReplaceLane functions to macro assembler. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2546933002 Cr-Commit-Position: refs/heads/master@{#41737}
2016-12-15 18:15:23 +00:00
COMPARE(vtbl(d0, NeonListOperand(d1, 1), d2),
"f3b10802 vtbl.8 d0, {d1}, d2");
COMPARE(vtbl(d31, NeonListOperand(d0, 2), d4),
"f3f0f904 vtbl.8 d31, {d0, d1}, d4");
COMPARE(vtbl(d15, NeonListOperand(d1, 3), d5),
"f3b1fa05 vtbl.8 d15, {d1, d2, d3}, d5");
COMPARE(vtbl(d15, NeonListOperand(d1, 4), d5),
"f3b1fb05 vtbl.8 d15, {d1, d2, d3, d4}, d5");
COMPARE(vtbx(d0, NeonListOperand(d1, 1), d2),
"f3b10842 vtbx.8 d0, {d1}, d2");
COMPARE(vtbx(d31, NeonListOperand(d0, 2), d4),
"f3f0f944 vtbx.8 d31, {d0, d1}, d4");
COMPARE(vtbx(d15, NeonListOperand(d1, 3), d5),
"f3b1fa45 vtbx.8 d15, {d1, d2, d3}, d5");
COMPARE(vtbx(d15, NeonListOperand(d1, 4), d5),
"f3b1fb45 vtbx.8 d15, {d1, d2, d3, d4}, d5");
ARM: Implement memcpy using NEON. Add support for a few NEON and ARM SIMD instructions and use them for various memcpy operations. BUG=none TEST=none Review URL: https://chromiumcodereview.appspot.com/17858002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15602 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-07-10 15:32:39 +00:00
}
VERIFY_RUN();
}
ARM: Fix disasm for strh, vabs, vneg. Add load/store tests. Patch from ARM Ltd. BUG=none TEST=added to test/cctest/test-disasm-arm.cc Original review at http://codereview.chromium.org/7013024/. Review URL: http://codereview.chromium.org/7013027 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7875 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-05-12 14:44:49 +00:00
TEST(LoadStore) {
Cosmetic changes ("set up" is a verb, "setup" is a noun). Review URL: http://codereview.chromium.org/9139051 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10399 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2012-01-13 13:09:52 +00:00
SET_UP();
ARM: Fix disasm for strh, vabs, vneg. Add load/store tests. Patch from ARM Ltd. BUG=none TEST=added to test/cctest/test-disasm-arm.cc Original review at http://codereview.chromium.org/7013024/. Review URL: http://codereview.chromium.org/7013027 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7875 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-05-12 14:44:49 +00:00
COMPARE(ldrb(r0, MemOperand(r1)),
"e5d10000 ldrb r0, [r1, #+0]");
COMPARE(ldrb(r2, MemOperand(r3, 42)),
"e5d3202a ldrb r2, [r3, #+42]");
COMPARE(ldrb(r4, MemOperand(r5, -42)),
"e555402a ldrb r4, [r5, #-42]");
COMPARE(ldrb(r6, MemOperand(r7, 42, PostIndex)),
"e4d7602a ldrb r6, [r7], #+42");
COMPARE(ldrb(r8, MemOperand(r9, -42, PostIndex)),
"e459802a ldrb r8, [r9], #-42");
COMPARE(ldrb(r10, MemOperand(fp, 42, PreIndex)),
"e5fba02a ldrb r10, [fp, #+42]!");
COMPARE(ldrb(ip, MemOperand(sp, -42, PreIndex)),
"e57dc02a ldrb ip, [sp, #-42]!");
COMPARE(ldrb(r0, MemOperand(r1, r2)),
"e7d10002 ldrb r0, [r1, +r2]");
COMPARE(ldrb(r0, MemOperand(r1, r2, NegOffset)),
"e7510002 ldrb r0, [r1, -r2]");
COMPARE(ldrb(r0, MemOperand(r1, r2, PostIndex)),
"e6d10002 ldrb r0, [r1], +r2");
COMPARE(ldrb(r0, MemOperand(r1, r2, NegPostIndex)),
"e6510002 ldrb r0, [r1], -r2");
COMPARE(ldrb(r0, MemOperand(r1, r2, PreIndex)),
"e7f10002 ldrb r0, [r1, +r2]!");
COMPARE(ldrb(r0, MemOperand(r1, r2, NegPreIndex)),
"e7710002 ldrb r0, [r1, -r2]!");
COMPARE(strb(r0, MemOperand(r1)),
"e5c10000 strb r0, [r1, #+0]");
COMPARE(strb(r2, MemOperand(r3, 42)),
"e5c3202a strb r2, [r3, #+42]");
COMPARE(strb(r4, MemOperand(r5, -42)),
"e545402a strb r4, [r5, #-42]");
COMPARE(strb(r6, MemOperand(r7, 42, PostIndex)),
"e4c7602a strb r6, [r7], #+42");
COMPARE(strb(r8, MemOperand(r9, -42, PostIndex)),
"e449802a strb r8, [r9], #-42");
COMPARE(strb(r10, MemOperand(fp, 42, PreIndex)),
"e5eba02a strb r10, [fp, #+42]!");
COMPARE(strb(ip, MemOperand(sp, -42, PreIndex)),
"e56dc02a strb ip, [sp, #-42]!");
COMPARE(strb(r0, MemOperand(r1, r2)),
"e7c10002 strb r0, [r1, +r2]");
COMPARE(strb(r0, MemOperand(r1, r2, NegOffset)),
"e7410002 strb r0, [r1, -r2]");
COMPARE(strb(r0, MemOperand(r1, r2, PostIndex)),
"e6c10002 strb r0, [r1], +r2");
COMPARE(strb(r0, MemOperand(r1, r2, NegPostIndex)),
"e6410002 strb r0, [r1], -r2");
COMPARE(strb(r0, MemOperand(r1, r2, PreIndex)),
"e7e10002 strb r0, [r1, +r2]!");
COMPARE(strb(r0, MemOperand(r1, r2, NegPreIndex)),
"e7610002 strb r0, [r1, -r2]!");
COMPARE(ldrh(r0, MemOperand(r1)),
"e1d100b0 ldrh r0, [r1, #+0]");
COMPARE(ldrh(r2, MemOperand(r3, 42)),
"e1d322ba ldrh r2, [r3, #+42]");
COMPARE(ldrh(r4, MemOperand(r5, -42)),
"e15542ba ldrh r4, [r5, #-42]");
COMPARE(ldrh(r6, MemOperand(r7, 42, PostIndex)),
"e0d762ba ldrh r6, [r7], #+42");
COMPARE(ldrh(r8, MemOperand(r9, -42, PostIndex)),
"e05982ba ldrh r8, [r9], #-42");
COMPARE(ldrh(r10, MemOperand(fp, 42, PreIndex)),
"e1fba2ba ldrh r10, [fp, #+42]!");
COMPARE(ldrh(ip, MemOperand(sp, -42, PreIndex)),
"e17dc2ba ldrh ip, [sp, #-42]!");
COMPARE(ldrh(r0, MemOperand(r1, r2)),
"e19100b2 ldrh r0, [r1, +r2]");
COMPARE(ldrh(r0, MemOperand(r1, r2, NegOffset)),
"e11100b2 ldrh r0, [r1, -r2]");
COMPARE(ldrh(r0, MemOperand(r1, r2, PostIndex)),
"e09100b2 ldrh r0, [r1], +r2");
COMPARE(ldrh(r0, MemOperand(r1, r2, NegPostIndex)),
"e01100b2 ldrh r0, [r1], -r2");
COMPARE(ldrh(r0, MemOperand(r1, r2, PreIndex)),
"e1b100b2 ldrh r0, [r1, +r2]!");
COMPARE(ldrh(r0, MemOperand(r1, r2, NegPreIndex)),
"e13100b2 ldrh r0, [r1, -r2]!");
COMPARE(strh(r0, MemOperand(r1)),
"e1c100b0 strh r0, [r1, #+0]");
COMPARE(strh(r2, MemOperand(r3, 42)),
"e1c322ba strh r2, [r3, #+42]");
COMPARE(strh(r4, MemOperand(r5, -42)),
"e14542ba strh r4, [r5, #-42]");
COMPARE(strh(r6, MemOperand(r7, 42, PostIndex)),
"e0c762ba strh r6, [r7], #+42");
COMPARE(strh(r8, MemOperand(r9, -42, PostIndex)),
"e04982ba strh r8, [r9], #-42");
COMPARE(strh(r10, MemOperand(fp, 42, PreIndex)),
"e1eba2ba strh r10, [fp, #+42]!");
COMPARE(strh(ip, MemOperand(sp, -42, PreIndex)),
"e16dc2ba strh ip, [sp, #-42]!");
COMPARE(strh(r0, MemOperand(r1, r2)),
"e18100b2 strh r0, [r1, +r2]");
COMPARE(strh(r0, MemOperand(r1, r2, NegOffset)),
"e10100b2 strh r0, [r1, -r2]");
COMPARE(strh(r0, MemOperand(r1, r2, PostIndex)),
"e08100b2 strh r0, [r1], +r2");
COMPARE(strh(r0, MemOperand(r1, r2, NegPostIndex)),
"e00100b2 strh r0, [r1], -r2");
COMPARE(strh(r0, MemOperand(r1, r2, PreIndex)),
"e1a100b2 strh r0, [r1, +r2]!");
COMPARE(strh(r0, MemOperand(r1, r2, NegPreIndex)),
"e12100b2 strh r0, [r1, -r2]!");
COMPARE(ldr(r0, MemOperand(r1)),
"e5910000 ldr r0, [r1, #+0]");
COMPARE(ldr(r2, MemOperand(r3, 42)),
"e593202a ldr r2, [r3, #+42]");
COMPARE(ldr(r4, MemOperand(r5, -42)),
"e515402a ldr r4, [r5, #-42]");
COMPARE(ldr(r6, MemOperand(r7, 42, PostIndex)),
"e497602a ldr r6, [r7], #+42");
COMPARE(ldr(r8, MemOperand(r9, -42, PostIndex)),
"e419802a ldr r8, [r9], #-42");
COMPARE(ldr(r10, MemOperand(fp, 42, PreIndex)),
"e5bba02a ldr r10, [fp, #+42]!");
COMPARE(ldr(ip, MemOperand(sp, -42, PreIndex)),
"e53dc02a ldr ip, [sp, #-42]!");
COMPARE(ldr(r0, MemOperand(r1, r2)),
"e7910002 ldr r0, [r1, +r2]");
COMPARE(ldr(r0, MemOperand(r1, r2, NegOffset)),
"e7110002 ldr r0, [r1, -r2]");
COMPARE(ldr(r0, MemOperand(r1, r2, PostIndex)),
"e6910002 ldr r0, [r1], +r2");
COMPARE(ldr(r0, MemOperand(r1, r2, NegPostIndex)),
"e6110002 ldr r0, [r1], -r2");
COMPARE(ldr(r0, MemOperand(r1, r2, PreIndex)),
"e7b10002 ldr r0, [r1, +r2]!");
COMPARE(ldr(r0, MemOperand(r1, r2, NegPreIndex)),
"e7310002 ldr r0, [r1, -r2]!");
COMPARE(str(r0, MemOperand(r1)),
"e5810000 str r0, [r1, #+0]");
COMPARE(str(r2, MemOperand(r3, 42)),
"e583202a str r2, [r3, #+42]");
COMPARE(str(r4, MemOperand(r5, -42)),
"e505402a str r4, [r5, #-42]");
COMPARE(str(r6, MemOperand(r7, 42, PostIndex)),
"e487602a str r6, [r7], #+42");
COMPARE(str(r8, MemOperand(r9, -42, PostIndex)),
"e409802a str r8, [r9], #-42");
COMPARE(str(r10, MemOperand(fp, 42, PreIndex)),
"e5aba02a str r10, [fp, #+42]!");
COMPARE(str(ip, MemOperand(sp, -42, PreIndex)),
"e52dc02a str ip, [sp, #-42]!");
COMPARE(str(r0, MemOperand(r1, r2)),
"e7810002 str r0, [r1, +r2]");
COMPARE(str(r0, MemOperand(r1, r2, NegOffset)),
"e7010002 str r0, [r1, -r2]");
COMPARE(str(r0, MemOperand(r1, r2, PostIndex)),
"e6810002 str r0, [r1], +r2");
COMPARE(str(r0, MemOperand(r1, r2, NegPostIndex)),
"e6010002 str r0, [r1], -r2");
COMPARE(str(r0, MemOperand(r1, r2, PreIndex)),
"e7a10002 str r0, [r1, +r2]!");
COMPARE(str(r0, MemOperand(r1, r2, NegPreIndex)),
"e7210002 str r0, [r1, -r2]!");
if (CpuFeatures::IsSupported(ARMv7)) {
Cleaned up CpuFeature scope handling. First of all, it has nothing to do with Isolates, it is related to the assembler at hand. Furthermore, the saving/restoring is platform-independent. Cleaned up some platform-specific stuff on the way. Note that there are some things which still need some cleanup, like e.g. using EnumSet instead of uint64_t, making Probe() more uniform across platforms etc., but the CL is already big enough. BUG=v8:2487 Review URL: https://codereview.chromium.org/12391055 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13823 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-03-05 10:48:16 +00:00
CpuFeatureScope scope(&assm, ARMv7);
ARM: Fix disasm for strh, vabs, vneg. Add load/store tests. Patch from ARM Ltd. BUG=none TEST=added to test/cctest/test-disasm-arm.cc Original review at http://codereview.chromium.org/7013024/. Review URL: http://codereview.chromium.org/7013027 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7875 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-05-12 14:44:49 +00:00
COMPARE(ldrd(r0, r1, MemOperand(r1)),
"e1c100d0 ldrd r0, [r1, #+0]");
COMPARE(ldrd(r2, r3, MemOperand(r3, 127)),
"e1c327df ldrd r2, [r3, #+127]");
COMPARE(ldrd(r4, r5, MemOperand(r5, -127)),
"e14547df ldrd r4, [r5, #-127]");
COMPARE(ldrd(r6, r7, MemOperand(r7, 127, PostIndex)),
"e0c767df ldrd r6, [r7], #+127");
COMPARE(ldrd(r8, r9, MemOperand(r9, -127, PostIndex)),
"e04987df ldrd r8, [r9], #-127");
COMPARE(ldrd(r10, fp, MemOperand(fp, 127, PreIndex)),
"e1eba7df ldrd r10, [fp, #+127]!");
COMPARE(ldrd(ip, sp, MemOperand(sp, -127, PreIndex)),
"e16dc7df ldrd ip, [sp, #-127]!");
COMPARE(strd(r0, r1, MemOperand(r1)),
"e1c100f0 strd r0, [r1, #+0]");
COMPARE(strd(r2, r3, MemOperand(r3, 127)),
"e1c327ff strd r2, [r3, #+127]");
COMPARE(strd(r4, r5, MemOperand(r5, -127)),
"e14547ff strd r4, [r5, #-127]");
COMPARE(strd(r6, r7, MemOperand(r7, 127, PostIndex)),
"e0c767ff strd r6, [r7], #+127");
COMPARE(strd(r8, r9, MemOperand(r9, -127, PostIndex)),
"e04987ff strd r8, [r9], #-127");
COMPARE(strd(r10, fp, MemOperand(fp, 127, PreIndex)),
"e1eba7ff strd r10, [fp, #+127]!");
COMPARE(strd(ip, sp, MemOperand(sp, -127, PreIndex)),
"e16dc7ff strd ip, [sp, #-127]!");
ARM: Implement memcpy using NEON. Add support for a few NEON and ARM SIMD instructions and use them for various memcpy operations. BUG=none TEST=none Review URL: https://chromiumcodereview.appspot.com/17858002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15602 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-07-10 15:32:39 +00:00
COMPARE(pld(MemOperand(r1, 0)),
"f5d1f000 pld [r1]");
[arm] Use the converter when printing general registers When disassembling some instructions we would print `r12`, which can be confusing when the rest of the disassembly consistently uses `ip`. Bug: Change-Id: Id4cfc5805ef102a0845cdaaa8390e618ee981b19 Reviewed-on: https://chromium-review.googlesource.com/570038 Reviewed-by: Georg Neis <neis@chromium.org> Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Cr-Commit-Position: refs/heads/master@{#46628}
2017-07-13 10:07:46 +00:00
COMPARE(pld(MemOperand(ip, 64)),
"f5dcf040 pld [ip, #+64]");
ARM: Implement memcpy using NEON. Add support for a few NEON and ARM SIMD instructions and use them for various memcpy operations. BUG=none TEST=none Review URL: https://chromiumcodereview.appspot.com/17858002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15602 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-07-10 15:32:39 +00:00
COMPARE(pld(MemOperand(r2, 128)),
"f5d2f080 pld [r2, #+128]");
ARM: Fix disasm for strh, vabs, vneg. Add load/store tests. Patch from ARM Ltd. BUG=none TEST=added to test/cctest/test-disasm-arm.cc Original review at http://codereview.chromium.org/7013024/. Review URL: http://codereview.chromium.org/7013027 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7875 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-05-12 14:44:49 +00:00
}
[arm] Introduce UseScratchRegisterScope Introduce a stripped down version of UseScratchRegisterScope for ARM and use it inside the assembler and macro-assembler. At the exception of the Call instructions, we now use this scope instead of using the ip register directly. This is inspired from how the ARM64 backend works. In general, the benefit of doing this is we can catch cases where ip is being used both by the caller and by the assembler. But more specifically, TurboFan reserves r9 as an extra scratch register because ip can already be used by the assembler. With this utility, we can isolate the cases in the code generator which need an extra register and potentially fix them, allowing us to give r9 back to the register allocator. This patch uncovered places in the assembler where we were using ip unconditionally when we could have re-used the destination register instead. Bug: v8:6553 Change-Id: Ib7134e3ed64dd1f90baf209ae831ed8f644cac78 Reviewed-on: https://chromium-review.googlesource.com/544956 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Cr-Commit-Position: refs/heads/master@{#46425}
2017-06-22 10:00:56 +00:00
// Test out-of-bound immediates.
COMPARE(ldrb(r6, MemOperand(r7, 42 << 12)),
"e3a06a2a mov r6, #172032",
"e7d76006 ldrb r6, [r7, +r6]");
COMPARE(ldrh(r6, MemOperand(r7, 42 << 8, PostIndex)),
"e3a06c2a mov r6, #10752",
"e09760b6 ldrh r6, [r7], +r6");
// Make sure ip is used if the destination is the same as the base.
COMPARE(ldr(r8, MemOperand(r8, 42 << 12, PreIndex)),
"e3a0ca2a mov ip, #172032",
"e7b8800c ldr r8, [r8, +ip]!");
COMPARE(strb(r6, MemOperand(r7, 42 << 12)),
"e3a0ca2a mov ip, #172032",
"e7c7600c strb r6, [r7, +ip]");
COMPARE(strh(r6, MemOperand(r7, 42 << 8, PostIndex)),
"e3a0cc2a mov ip, #10752",
"e08760bc strh r6, [r7], +ip");
COMPARE(str(r6, MemOperand(r7, 42 << 12, PreIndex)),
"e3a0ca2a mov ip, #172032",
"e7a7600c str r6, [r7, +ip]!");
// Test scaled operands for instructions that do not support it natively.
COMPARE(ldrh(r0, MemOperand(r1, r2, LSL, 2)),
"e1a00102 mov r0, r2, lsl #2",
"e19100b0 ldrh r0, [r1, +r0]");
COMPARE(strh(r3, MemOperand(r4, r5, LSR, 3)),
"e1a0c1a5 mov ip, r5, lsr #3",
"e18430bc strh r3, [r4, +ip]");
// Make sure ip is used if the destination is the same as the base.
COMPARE(ldrsb(r6, MemOperand(r6, r8, ASR, 4)),
"e1a0c248 mov ip, r8, asr #4",
"e19660dc ldrsb r6, [r6, +ip]");
COMPARE(ldrsh(r9, MemOperand(sp, r10, ROR, 5)),
"e1a092ea mov r9, r10, ror #5",
"e19d90f9 ldrsh r9, [sp, +r9]");
ARM: Fix disasm for strh, vabs, vneg. Add load/store tests. Patch from ARM Ltd. BUG=none TEST=added to test/cctest/test-disasm-arm.cc Original review at http://codereview.chromium.org/7013024/. Review URL: http://codereview.chromium.org/7013027 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7875 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-05-12 14:44:49 +00:00
VERIFY_RUN();
}
[Atomics] Add dmb/dsb/isb instructions to ARM This is not currently implemented in the simulator, just the assembler and disassembler. BUG=v8:4614 LOG=y Review URL: https://codereview.chromium.org/1699173003 Cr-Commit-Position: refs/heads/master@{#34093}
2016-02-17 19:57:18 +00:00
[arm] Print address for load literal instructions. BUG= Review-Url: https://codereview.chromium.org/2871863003 Cr-Commit-Position: refs/heads/master@{#45297}
2017-05-15 11:00:16 +00:00
static void TestLoadLiteral(byte* buffer, Assembler* assm, bool* failure,
int offset) {
int pc_offset = assm->pc_offset();
byte *progcounter = &buffer[pc_offset];
[arm] Restrict usage of pc-relative LDR. Disallow using the PC as a base in LDR and instead provide a dedicated assembler method for pc-relative loads. The reason for this is that the generic `Assembler::ldr` method may decide to generate more instructions if the offset is out of range, and if the PC was the base, we would get surprising results. For example: ~~~ ldr r0, [pc, #0xcabba9e] ~~~ is not equivalent to: ~~~ movw ip, #0xba9e movt ip, #0xcab ldr r0, [pc, ip] ~~~ since the reference to the PC has moved down two instructions! We could teach the assembler to handle those cases correctly, but pc-relative loads are used in specific cases only so that's not necessary. As a drive-by, remove a reference to code aging. Bug: Change-Id: I586d83a418db52cf28d3b524f889bf40f077998a Reviewed-on: https://chromium-review.googlesource.com/847008 Reviewed-by: Jaroslav Sevcik <jarin@chromium.org> Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Cr-Commit-Position: refs/heads/master@{#50475}
2018-01-02 18:56:22 +00:00
assm->ldr_pcrel(r0, offset);
[arm] Print address for load literal instructions. BUG= Review-Url: https://codereview.chromium.org/2871863003 Cr-Commit-Position: refs/heads/master@{#45297}
2017-05-15 11:00:16 +00:00
const char *expected_string_template =
(offset >= 0) ?
"e59f0%03x ldr r0, [pc, #+%d] (addr %p)" :
"e51f0%03x ldr r0, [pc, #%d] (addr %p)";
char expected_string[80];
snprintf(expected_string, sizeof(expected_string), expected_string_template,
abs(offset), offset,
[arm,ppc] Consolidate kPCReadOffset to kPcLoadDelta We have two constants for the PC load delta; this CL consolidates them into one. The CL does not change MIPS as the two constants are defined to different values there. Bug: v8:6666 Change-Id: If207a59dea3ef33756a5d7330217ab8a176bdf63 Reviewed-on: https://chromium-review.googlesource.com/1161926 Reviewed-by: Jakob Gruber <jgruber@chromium.org> Commit-Queue: Sigurd Schneider <sigurds@chromium.org> Cr-Commit-Position: refs/heads/master@{#54898}
2018-08-03 09:57:09 +00:00
progcounter + Instruction::kPcLoadDelta + offset);
[arm] Fix SplitAddImmediate test on Armv6. The movw/movt instructions are only available since Armv7. One of the disassembly tests was expecting these instructions when, on Armv6, we generate a load literal. Change-Id: I2b11894b5de748fc185f341b0cd49fa518d005e5 Reviewed-on: https://chromium-review.googlesource.com/978143 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#52738}
2018-04-23 15:44:01 +00:00
if (!DisassembleAndCompare(progcounter, kRawString, expected_string)) {
*failure = true;
}
[arm] Print address for load literal instructions. BUG= Review-Url: https://codereview.chromium.org/2871863003 Cr-Commit-Position: refs/heads/master@{#45297}
2017-05-15 11:00:16 +00:00
}
TEST(LoadLiteral) {
SET_UP();
TestLoadLiteral(buffer, &assm, &failure, 0);
TestLoadLiteral(buffer, &assm, &failure, 1);
TestLoadLiteral(buffer, &assm, &failure, 4);
TestLoadLiteral(buffer, &assm, &failure, 4095);
TestLoadLiteral(buffer, &assm, &failure, -1);
TestLoadLiteral(buffer, &assm, &failure, -4);
TestLoadLiteral(buffer, &assm, &failure, -4095);
VERIFY_RUN();
}
[Atomics] Add dmb/dsb/isb instructions to ARM This is not currently implemented in the simulator, just the assembler and disassembler. BUG=v8:4614 LOG=y Review URL: https://codereview.chromium.org/1699173003 Cr-Commit-Position: refs/heads/master@{#34093}
2016-02-17 19:57:18 +00:00
TEST(Barrier) {
SET_UP();
if (CpuFeatures::IsSupported(ARMv7)) {
CpuFeatureScope scope(&assm, ARMv7);
COMPARE(dmb(OSHLD),
"f57ff051 dmb oshld");
COMPARE(dmb(OSHST),
"f57ff052 dmb oshst");
COMPARE(dmb(OSH),
"f57ff053 dmb osh");
COMPARE(dmb(NSHLD),
"f57ff055 dmb nshld");
COMPARE(dmb(NSHST),
"f57ff056 dmb nshst");
COMPARE(dmb(NSH),
"f57ff057 dmb nsh");
COMPARE(dmb(ISHLD),
"f57ff059 dmb ishld");
COMPARE(dmb(ISHST),
"f57ff05a dmb ishst");
COMPARE(dmb(ISH),
"f57ff05b dmb ish");
COMPARE(dmb(LD),
"f57ff05d dmb ld");
COMPARE(dmb(ST),
"f57ff05e dmb st");
COMPARE(dmb(SY),
"f57ff05f dmb sy");
COMPARE(dsb(ISH),
"f57ff04b dsb ish");
[arm] Implement barriers on ARMv6 using CP15. ARMv6 has the same basic barriers as ARMv7+, but they are accessed using the CP15 coprocessor. This patch allows the assembler to select the appropriate instruction. This also fixes TurboFan's atomic loads and stores for ARMv6 platforms. BUG= Review-Url: https://codereview.chromium.org/2318553002 Cr-Commit-Position: refs/heads/master@{#39203}
2016-09-06 11:29:57 +00:00
COMPARE(isb(SY),
"f57ff06f isb sy");
} else {
// ARMv6 uses CP15 to implement barriers. The BarrierOption argument is
// ignored.
COMPARE(dmb(ISH),
"ee070fba mcr (CP15DMB)");
COMPARE(dsb(OSH),
"ee070f9a mcr (CP15DSB)");
COMPARE(isb(SY),
"ee070f95 mcr (CP15ISB)");
[Atomics] Add dmb/dsb/isb instructions to ARM This is not currently implemented in the simulator, just the assembler and disassembler. BUG=v8:4614 LOG=y Review URL: https://codereview.chromium.org/1699173003 Cr-Commit-Position: refs/heads/master@{#34093}
2016-02-17 19:57:18 +00:00
}
[arm] Implement barriers on ARMv6 using CP15. ARMv6 has the same basic barriers as ARMv7+, but they are accessed using the CP15 coprocessor. This patch allows the assembler to select the appropriate instruction. This also fixes TurboFan's atomic loads and stores for ARMv6 platforms. BUG= Review-Url: https://codereview.chromium.org/2318553002 Cr-Commit-Position: refs/heads/master@{#39203}
2016-09-06 11:29:57 +00:00
// ARMv6 barriers.
// Details available in ARM DDI 0406C.b, B3-1750.
COMPARE(mcr(p15, 0, r0, cr7, cr10, 5), "ee070fba mcr (CP15DMB)");
COMPARE(mcr(p15, 0, r0, cr7, cr10, 4), "ee070f9a mcr (CP15DSB)");
COMPARE(mcr(p15, 0, r0, cr7, cr5, 4), "ee070f95 mcr (CP15ISB)");
// Rt is ignored.
COMPARE(mcr(p15, 0, lr, cr7, cr10, 5), "ee07efba mcr (CP15DMB)");
COMPARE(mcr(p15, 0, lr, cr7, cr10, 4), "ee07ef9a mcr (CP15DSB)");
COMPARE(mcr(p15, 0, lr, cr7, cr5, 4), "ee07ef95 mcr (CP15ISB)");
// The mcr instruction can be conditional.
COMPARE(mcr(p15, 0, r0, cr7, cr10, 5, eq), "0e070fba mcreq (CP15DMB)");
COMPARE(mcr(p15, 0, r0, cr7, cr10, 4, ne), "1e070f9a mcrne (CP15DSB)");
COMPARE(mcr(p15, 0, r0, cr7, cr5, 4, mi), "4e070f95 mcrmi (CP15ISB)");
[arm] Support CSDB instruction Add support for CSDB in the 32-bit assembler, disassembler and simulator. Change-Id: I0e5432e4d219dd4699d5f9b7f911791acc87114c Reviewed-on: https://chromium-review.googlesource.com/928522 Reviewed-by: Ross McIlroy <rmcilroy@chromium.org> Commit-Queue: Martyn Capewell <martyn.capewell@arm.com> Cr-Commit-Position: refs/heads/master@{#51425}
2018-02-21 11:03:02 +00:00
// Conditional speculation barrier.
COMPARE(csdb(), "e320f014 csdb");
[Atomics] Add dmb/dsb/isb instructions to ARM This is not currently implemented in the simulator, just the assembler and disassembler. BUG=v8:4614 LOG=y Review URL: https://codereview.chromium.org/1699173003 Cr-Commit-Position: refs/heads/master@{#34093}
2016-02-17 19:57:18 +00:00
VERIFY_RUN();
}
Add ldrex and strex instructions to ARM assembler/disassmbler R=jarin@chromium.org,bmeurer@chromium.org Review-Url: https://codereview.chromium.org/1993033002 Cr-Commit-Position: refs/heads/master@{#36380}
2016-05-19 19:11:09 +00:00
TEST(LoadStoreExclusive) {
SET_UP();
COMPARE(ldrexb(r0, r1), "e1d10f9f ldrexb r0, [r1]");
COMPARE(strexb(r0, r1, r2), "e1c20f91 strexb r0, r1, [r2]");
COMPARE(ldrexh(r0, r1), "e1f10f9f ldrexh r0, [r1]");
COMPARE(strexh(r0, r1, r2), "e1e20f91 strexh r0, r1, [r2]");
COMPARE(ldrex(r0, r1), "e1910f9f ldrex r0, [r1]");
COMPARE(strex(r0, r1, r2), "e1820f91 strex r0, r1, [r2]");
[arm] Implement I64Atomic operations on Arm - Implement all the I64Atomic operations on ARM - Change assembler methods to use Registers instead of memory operands - Move atomics64 test up be tested on all archs, disable tests on MIPS BUG:v8:6532 Change-Id: I91bd42fa819f194be15c719266c36230f9c65db8 Reviewed-on: https://chromium-review.googlesource.com/1180211 Commit-Queue: Deepti Gandluri <gdeepti@chromium.org> Reviewed-by: Bill Budge <bbudge@chromium.org> Reviewed-by: Ben Smith <binji@chromium.org> Cr-Commit-Position: refs/heads/master@{#55416}
2018-08-25 01:32:25 +00:00
COMPARE(ldrexd(r0, r1, r2), "e1b20f9f ldrexd r0, [r2]");
COMPARE(strexd(r0, r2, r3, r4),
Add ldrexd/strexd to the Arm assembler Bug: v8:6532 Change-Id: Id89f81b12205900fc935e6232840e1976e24d3b4 Reviewed-on: https://chromium-review.googlesource.com/1176962 Commit-Queue: Deepti Gandluri <gdeepti@chromium.org> Reviewed-by: Bill Budge <bbudge@chromium.org> Cr-Commit-Position: refs/heads/master@{#55228}
2018-08-20 17:01:34 +00:00
"e1a40f92 strexd r0, r2, [r4]");
Add ldrex and strex instructions to ARM assembler/disassmbler R=jarin@chromium.org,bmeurer@chromium.org Review-Url: https://codereview.chromium.org/1993033002 Cr-Commit-Position: refs/heads/master@{#36380}
2016-05-19 19:11:09 +00:00
VERIFY_RUN();
}
[cctest] Avoid disallowed "using namespace" directive. R=jkummerow@chromium.org Change-Id: I8937933e9ec5b4bd150f5a044700716db458f365 Reviewed-on: https://chromium-review.googlesource.com/645691 Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#47758}
2017-08-31 12:34:55 +00:00
[arm] Support splitting add with immediate instructions When an immediate does not fit an add instruction we use a temporary register to hold the value, using movw/movt to encode it. However, in order to remove a use of r9 in TurboFan's code generator, we need to cope with no scratch registers being available. That is to say that the destination and source registers are the same, and `ip` is not available to use. In this case, we can split an add instruction into a sequence of additions: ``` UseScratchRegisterScope temps(...); Register my_scratch = temps.Acquire(); __ add(r0, r0, Operand(0xabcd); // add r0, r0, #0xcd // add r0, r0, #0xab00 ``` As a drive-by fix, make the disassembler test fail if we expected a different number of instructions generated. Bug: v8:6553 Change-Id: Ib7fcc765d28bccafe39257f47cd73f922c5873bf Reviewed-on: https://chromium-review.googlesource.com/685014 Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Cr-Commit-Position: refs/heads/master@{#48491}
2017-10-11 12:00:21 +00:00
TEST(SplitAddImmediate) {
SET_UP();
[arm] Fix SplitAddImmediate test on Armv6. The movw/movt instructions are only available since Armv7. One of the disassembly tests was expecting these instructions when, on Armv6, we generate a load literal. Change-Id: I2b11894b5de748fc185f341b0cd49fa518d005e5 Reviewed-on: https://chromium-review.googlesource.com/978143 Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Reviewed-by: Jaroslav Sevcik <jarin@chromium.org> Cr-Commit-Position: refs/heads/master@{#52738}
2018-04-23 15:44:01 +00:00
if (CpuFeatures::IsSupported(ARMv7)) {
// Re-use the destination as a scratch.
COMPARE(add(r0, r1, Operand(0x12345678)),
"e3050678 movw r0, #22136",
"e3410234 movt r0, #4660",
"e0810000 add r0, r1, r0");
// Use ip as a scratch.
COMPARE(add(r0, r0, Operand(0x12345678)),
"e305c678 movw ip, #22136",
"e341c234 movt ip, #4660",
"e080000c add r0, r0, ip");
} else {
// Re-use the destination as a scratch.
COMPARE_REGEX(add(r0, r1, Operand(0x12345678)),
"e59f0[0-9a-f]{3} "
"ldr r0, \\[pc, #\\+[0-9]+\\] \\(addr 0x[0-9a-f]{8}\\)",
"e0810000 add r0, r1, r0");
// Use ip as a scratch.
COMPARE_REGEX(add(r0, r0, Operand(0x12345678)),
"e59fc[0-9a-f]{3} "
"ldr ip, \\[pc, #\\+[0-9]+\\] \\(addr 0x[0-9a-f]{8}\\)",
"e080000c add r0, r0, ip");
}
[arm] Support splitting add with immediate instructions When an immediate does not fit an add instruction we use a temporary register to hold the value, using movw/movt to encode it. However, in order to remove a use of r9 in TurboFan's code generator, we need to cope with no scratch registers being available. That is to say that the destination and source registers are the same, and `ip` is not available to use. In this case, we can split an add instruction into a sequence of additions: ``` UseScratchRegisterScope temps(...); Register my_scratch = temps.Acquire(); __ add(r0, r0, Operand(0xabcd); // add r0, r0, #0xcd // add r0, r0, #0xab00 ``` As a drive-by fix, make the disassembler test fail if we expected a different number of instructions generated. Bug: v8:6553 Change-Id: Ib7fcc765d28bccafe39257f47cd73f922c5873bf Reviewed-on: https://chromium-review.googlesource.com/685014 Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Cr-Commit-Position: refs/heads/master@{#48491}
2017-10-11 12:00:21 +00:00
// If ip is not available, split the operation into multiple additions.
{
UseScratchRegisterScope temps(&assm);
Register reserved = temps.Acquire();
USE(reserved);
COMPARE(add(r2, r2, Operand(0x12345678)),
"e2822f9e add r2, r2, #632",
"e2822b15 add r2, r2, #21504",
"e282278d add r2, r2, #36962304",
"e2822201 add r2, r2, #268435456");
}
VERIFY_RUN();
}
[cctest] Avoid disallowed "using namespace" directive. R=jkummerow@chromium.org Change-Id: I8937933e9ec5b4bd150f5a044700716db458f365 Reviewed-on: https://chromium-review.googlesource.com/645691 Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#47758}
2017-08-31 12:34:55 +00:00
} // namespace internal
} // namespace v8
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