S390 [liftoff]: Implement simd extract lane ops
Change-Id: Id3bd334dcd7ee028d2843b7ab4dd616d48afb947 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3038531 Reviewed-by: Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#75795}
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@ -5115,6 +5115,48 @@ void TurboAssembler::I8x16Splat(Simd128Register dst, Register src) {
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vrep(dst, dst, Operand(0), Condition(0));
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}
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void TurboAssembler::F64x2ExtractLane(DoubleRegister dst, Simd128Register src,
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uint8_t imm_lane_idx) {
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vrep(dst, src, Operand(1 - imm_lane_idx), Condition(3));
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}
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void TurboAssembler::F32x4ExtractLane(DoubleRegister dst, Simd128Register src,
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uint8_t imm_lane_idx) {
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vrep(dst, src, Operand(3 - imm_lane_idx), Condition(2));
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}
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void TurboAssembler::I64x2ExtractLane(Register dst, Simd128Register src,
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uint8_t imm_lane_idx) {
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vlgv(dst, src, MemOperand(r0, 1 - imm_lane_idx), Condition(3));
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}
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void TurboAssembler::I32x4ExtractLane(Register dst, Simd128Register src,
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uint8_t imm_lane_idx) {
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vlgv(dst, src, MemOperand(r0, 3 - imm_lane_idx), Condition(2));
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}
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void TurboAssembler::I16x8ExtractLaneU(Register dst, Simd128Register src,
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uint8_t imm_lane_idx) {
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vlgv(dst, src, MemOperand(r0, 7 - imm_lane_idx), Condition(1));
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}
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void TurboAssembler::I16x8ExtractLaneS(Register dst, Simd128Register src,
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uint8_t imm_lane_idx) {
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vlgv(r0, src, MemOperand(r0, 7 - imm_lane_idx), Condition(1));
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lghr(dst, r0);
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}
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void TurboAssembler::I8x16ExtractLaneU(Register dst, Simd128Register src,
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uint8_t imm_lane_idx) {
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vlgv(dst, src, MemOperand(r0, 15 - imm_lane_idx), Condition(0));
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}
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void TurboAssembler::I8x16ExtractLaneS(Register dst, Simd128Register src,
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uint8_t imm_lane_idx) {
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vlgv(r0, src, MemOperand(r0, 15 - imm_lane_idx), Condition(0));
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lgbr(dst, r0);
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}
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} // namespace internal
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} // namespace v8
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@ -1038,6 +1038,22 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
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void I32x4Splat(Simd128Register dst, Register src);
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void I16x8Splat(Simd128Register dst, Register src);
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void I8x16Splat(Simd128Register dst, Register src);
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void F64x2ExtractLane(DoubleRegister dst, Simd128Register src,
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uint8_t imm_lane_idx);
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void F32x4ExtractLane(DoubleRegister dst, Simd128Register src,
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uint8_t imm_lane_idx);
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void I64x2ExtractLane(Register dst, Simd128Register src,
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uint8_t imm_lane_idx);
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void I32x4ExtractLane(Register dst, Simd128Register src,
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uint8_t imm_lane_idx);
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void I16x8ExtractLaneU(Register dst, Simd128Register src,
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uint8_t imm_lane_idx);
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void I16x8ExtractLaneS(Register dst, Simd128Register src,
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uint8_t imm_lane_idx);
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void I8x16ExtractLaneU(Register dst, Simd128Register src,
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uint8_t imm_lane_idx);
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void I8x16ExtractLaneS(Register dst, Simd128Register src,
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uint8_t imm_lane_idx);
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// ---------------------------------------------------------------------------
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// Pointer compression Support
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@ -2498,50 +2498,26 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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SIMD_UNOP_LIST(EMIT_SIMD_UNOP)
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#undef EMIT_SIMD_UNOP
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#undef SIMD_UNOP_LIST
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// vector extract element
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case kS390_F64x2ExtractLane: {
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__ vrep(i.OutputDoubleRegister(), i.InputSimd128Register(0),
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Operand(1 - i.InputInt8(1)), Condition(3));
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break;
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}
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case kS390_F32x4ExtractLane: {
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__ vrep(i.OutputDoubleRegister(), i.InputSimd128Register(0),
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Operand(3 - i.InputInt8(1)), Condition(2));
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break;
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}
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case kS390_I64x2ExtractLane: {
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__ vlgv(i.OutputRegister(), i.InputSimd128Register(0),
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MemOperand(r0, 1 - i.InputInt8(1)), Condition(3));
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break;
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}
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case kS390_I32x4ExtractLane: {
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__ vlgv(i.OutputRegister(), i.InputSimd128Register(0),
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MemOperand(r0, 3 - i.InputInt8(1)), Condition(2));
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break;
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}
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case kS390_I16x8ExtractLaneU: {
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__ vlgv(i.OutputRegister(), i.InputSimd128Register(0),
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MemOperand(r0, 7 - i.InputInt8(1)), Condition(1));
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break;
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}
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case kS390_I16x8ExtractLaneS: {
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__ vlgv(kScratchReg, i.InputSimd128Register(0),
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MemOperand(r0, 7 - i.InputInt8(1)), Condition(1));
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__ lghr(i.OutputRegister(), kScratchReg);
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break;
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}
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case kS390_I8x16ExtractLaneU: {
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__ vlgv(i.OutputRegister(), i.InputSimd128Register(0),
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MemOperand(r0, 15 - i.InputInt8(1)), Condition(0));
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break;
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}
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case kS390_I8x16ExtractLaneS: {
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__ vlgv(kScratchReg, i.InputSimd128Register(0),
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MemOperand(r0, 15 - i.InputInt8(1)), Condition(0));
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__ lgbr(i.OutputRegister(), kScratchReg);
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break;
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}
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// vector replace element
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#define SIMD_EXTRACT_LANE_LIST(V) \
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V(F64x2ExtractLane, DoubleRegister) \
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V(F32x4ExtractLane, DoubleRegister) \
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V(I64x2ExtractLane, Register) \
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V(I32x4ExtractLane, Register) \
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V(I16x8ExtractLaneU, Register) \
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V(I16x8ExtractLaneS, Register) \
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V(I8x16ExtractLaneU, Register) \
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V(I8x16ExtractLaneS, Register)
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#define EMIT_SIMD_EXTRACT_LANE(name, dtype) \
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case kS390_##name: { \
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__ name(i.Output##dtype(), i.InputSimd128Register(0), i.InputInt8(1)); \
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break; \
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}
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SIMD_EXTRACT_LANE_LIST(EMIT_SIMD_EXTRACT_LANE)
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#undef EMIT_SIMD_EXTRACT_LANE
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#undef SIMD_EXTRACT_LANE_LIST
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// vector replace element
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case kS390_F64x2ReplaceLane: {
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Simd128Register src = i.InputSimd128Register(0);
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Simd128Register dst = i.OutputSimd128Register();
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@ -2159,6 +2159,25 @@ SIMD_UNOP_LIST(EMIT_SIMD_UNOP)
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#undef EMIT_SIMD_UNOP
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#undef SIMD_UNOP_LIST
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#define SIMD_EXTRACT_LANE_LIST(V) \
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V(f64x2_extract_lane, F64x2ExtractLane, fp) \
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V(f32x4_extract_lane, F32x4ExtractLane, fp) \
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V(i64x2_extract_lane, I64x2ExtractLane, gp) \
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V(i32x4_extract_lane, I32x4ExtractLane, gp) \
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V(i16x8_extract_lane_u, I16x8ExtractLaneU, gp) \
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V(i16x8_extract_lane_s, I16x8ExtractLaneS, gp) \
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V(i8x16_extract_lane_u, I8x16ExtractLaneU, gp) \
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V(i8x16_extract_lane_s, I8x16ExtractLaneS, gp)
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#define EMIT_SIMD_EXTRACT_LANE(name, op, dtype) \
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void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister src, \
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uint8_t imm_lane_idx) { \
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op(dst.dtype(), src.fp(), imm_lane_idx); \
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}
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SIMD_EXTRACT_LANE_LIST(EMIT_SIMD_EXTRACT_LANE)
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#undef EMIT_SIMD_EXTRACT_LANE
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#undef SIMD_EXTRACT_LANE_LIST
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void LiftoffAssembler::LoadTransform(LiftoffRegister dst, Register src_addr,
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Register offset_reg, uintptr_t offset_imm,
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LoadType type,
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@ -2187,12 +2206,6 @@ void LiftoffAssembler::emit_i8x16_swizzle(LiftoffRegister dst,
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bailout(kUnsupportedArchitecture, "emit_i8x16_swizzle");
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}
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void LiftoffAssembler::emit_f64x2_extract_lane(LiftoffRegister dst,
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LiftoffRegister lhs,
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uint8_t imm_lane_idx) {
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bailout(kUnsupportedArchitecture, "emit_f64x2extractlane");
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}
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void LiftoffAssembler::emit_f64x2_replace_lane(LiftoffRegister dst,
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LiftoffRegister src1,
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LiftoffRegister src2,
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@ -2294,12 +2307,6 @@ void LiftoffAssembler::emit_f64x2_promote_low_f32x4(LiftoffRegister dst,
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bailout(kSimd, "f64x2.promote_low_f32x4");
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}
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void LiftoffAssembler::emit_f32x4_extract_lane(LiftoffRegister dst,
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LiftoffRegister lhs,
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uint8_t imm_lane_idx) {
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bailout(kUnsupportedArchitecture, "emit_f32x4extractlane");
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}
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void LiftoffAssembler::emit_f32x4_replace_lane(LiftoffRegister dst,
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LiftoffRegister src1,
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LiftoffRegister src2,
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@ -2386,12 +2393,6 @@ void LiftoffAssembler::emit_f32x4_pmax(LiftoffRegister dst, LiftoffRegister lhs,
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bailout(kSimd, "pmax unimplemented");
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}
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void LiftoffAssembler::emit_i64x2_extract_lane(LiftoffRegister dst,
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LiftoffRegister lhs,
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uint8_t imm_lane_idx) {
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bailout(kUnsupportedArchitecture, "emit_i64x2extractlane");
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}
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void LiftoffAssembler::emit_i64x2_replace_lane(LiftoffRegister dst,
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LiftoffRegister src1,
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LiftoffRegister src2,
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@ -2505,12 +2506,6 @@ void LiftoffAssembler::emit_i64x2_extmul_high_i32x4_u(LiftoffRegister dst,
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bailout(kSimd, "i64x2_extmul_high_i32x4_u unsupported");
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}
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void LiftoffAssembler::emit_i32x4_extract_lane(LiftoffRegister dst,
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LiftoffRegister lhs,
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uint8_t imm_lane_idx) {
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bailout(kUnsupportedArchitecture, "emit_i32x4extractlane");
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}
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void LiftoffAssembler::emit_i32x4_replace_lane(LiftoffRegister dst,
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LiftoffRegister src1,
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LiftoffRegister src2,
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@ -2754,12 +2749,6 @@ void LiftoffAssembler::emit_i16x8_max_u(LiftoffRegister dst,
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bailout(kUnsupportedArchitecture, "emit_i16x8_max_u");
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}
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void LiftoffAssembler::emit_i16x8_extract_lane_u(LiftoffRegister dst,
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LiftoffRegister lhs,
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uint8_t imm_lane_idx) {
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bailout(kUnsupportedArchitecture, "emit_i16x8extractlane_u");
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}
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void LiftoffAssembler::emit_i16x8_replace_lane(LiftoffRegister dst,
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LiftoffRegister src1,
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LiftoffRegister src2,
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@ -2777,12 +2766,6 @@ void LiftoffAssembler::emit_i16x8_extadd_pairwise_i8x16_u(LiftoffRegister dst,
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bailout(kSimd, "i16x8.extadd_pairwise_i8x16_u");
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}
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void LiftoffAssembler::emit_i16x8_extract_lane_s(LiftoffRegister dst,
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LiftoffRegister lhs,
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uint8_t imm_lane_idx) {
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bailout(kUnsupportedArchitecture, "emit_i16x8extractlane_s");
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}
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void LiftoffAssembler::emit_i16x8_extmul_low_i8x16_s(LiftoffRegister dst,
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LiftoffRegister src1,
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LiftoffRegister src2) {
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@ -2826,18 +2809,6 @@ void LiftoffAssembler::emit_i8x16_popcnt(LiftoffRegister dst,
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bailout(kSimd, "i8x16.popcnt");
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}
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void LiftoffAssembler::emit_i8x16_extract_lane_u(LiftoffRegister dst,
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LiftoffRegister lhs,
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uint8_t imm_lane_idx) {
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bailout(kUnsupportedArchitecture, "emit_i8x16extractlane_u");
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}
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void LiftoffAssembler::emit_i8x16_extract_lane_s(LiftoffRegister dst,
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LiftoffRegister lhs,
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uint8_t imm_lane_idx) {
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bailout(kUnsupportedArchitecture, "emit_i8x16extractlane_s");
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}
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void LiftoffAssembler::emit_i8x16_replace_lane(LiftoffRegister dst,
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LiftoffRegister src1,
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LiftoffRegister src2,
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