AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity

Clean up macros

Browse Source 
Move some instruction definitions into sse-instr, which is used to
generate some disasm tests, so we can remove some cases there.

Bug: v8:9810
Change-Id: I0615ec823396da08bc5d234cf1dabca6afd3f052
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1866965
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64441}
This commit is contained in:
Ng Zhi An 2019-10-17 16:21:56 -07:00 committed by Commit Bot
parent 44d68718b1
commit 08b26f53c6
4 changed files with 10 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
src/codegen/ia32/assembler-ia32.cc
View File

@ -2495,14 +2495,6 @@ void Assembler::psllq(XMMRegister reg, uint8_t shift) {
EMIT(shift);
}
void Assembler::psllq(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
EMIT(0xF3);
emit_sse_operand(dst, src);
}
void Assembler::psrlq(XMMRegister reg, uint8_t shift) {
EnsureSpace ensure_space(this);
EMIT(0x66);
@ -2512,14 +2504,6 @@ void Assembler::psrlq(XMMRegister reg, uint8_t shift) {
EMIT(shift);
}
void Assembler::psrlq(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
EMIT(0xD3);
emit_sse_operand(dst, src);
}
void Assembler::pshufhw(XMMRegister dst, Operand src, uint8_t shuffle) {
EnsureSpace ensure_space(this);
EMIT(0xF3);
@ -2798,6 +2782,12 @@ void Assembler::vpslld(XMMRegister dst, XMMRegister src, uint8_t imm8) {
EMIT(imm8);
}
void Assembler::vpsllq(XMMRegister dst, XMMRegister src, uint8_t imm8) {
XMMRegister iop = XMMRegister::from_code(6);
vinstr(0x73, iop, dst, Operand(src), k66, k0F, kWIG);
EMIT(imm8);
}
void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, uint8_t imm8) {
XMMRegister iop = XMMRegister::from_code(2);
vinstr(0x71, iop, dst, Operand(src), k66, k0F, kWIG);

3
src/codegen/ia32/assembler-ia32.h
View File

@ -996,9 +996,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
void psraw(XMMRegister reg, uint8_t shift);
void psrad(XMMRegister reg, uint8_t shift);
void psllq(XMMRegister reg, uint8_t shift);
void psllq(XMMRegister dst, XMMRegister src);
void psrlq(XMMRegister reg, uint8_t shift);
void psrlq(XMMRegister dst, XMMRegister src);
void pshufhw(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
pshufhw(dst, Operand(src), shuffle);
@ -1332,6 +1330,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
void vpsllw(XMMRegister dst, XMMRegister src, uint8_t imm8);
void vpslld(XMMRegister dst, XMMRegister src, uint8_t imm8);
void vpsllq(XMMRegister dst, XMMRegister src, uint8_t imm8);
void vpsrlw(XMMRegister dst, XMMRegister src, uint8_t imm8);
void vpsrld(XMMRegister dst, XMMRegister src, uint8_t imm8);
void vpsraw(XMMRegister dst, XMMRegister src, uint8_t imm8);

2
src/codegen/ia32/sse-instr.h
View File

@ -31,10 +31,12 @@
V(por, 66, 0F, EB) \
V(psllw, 66, 0F, F1) \
V(pslld, 66, 0F, F2) \
V(psllq, 66, 0F, F3) \
V(psraw, 66, 0F, E1) \
V(psrad, 66, 0F, E2) \
V(psrlw, 66, 0F, D1) \
V(psrld, 66, 0F, D2) \
V(psrlq, 66, 0F, D3) \
V(psubb, 66, 0F, F8) \
V(psubw, 66, 0F, F9) \
V(psubd, 66, 0F, FA) \

3
test/cctest/test-disasm-ia32.cc
View File

@ -535,9 +535,7 @@ TEST(DisasmIa320) {
__ psraw(xmm0, 17);
__ psrad(xmm0, 17);
__ psllq(xmm0, 17);
__ psllq(xmm0, xmm1);
__ psrlq(xmm0, 17);
__ psrlq(xmm0, xmm1);
__ pshufhw(xmm5, xmm1, 5);
__ pshufhw(xmm5, Operand(edx, 4), 5);
@ -735,6 +733,7 @@ TEST(DisasmIa320) {
__ vpsllw(xmm0, xmm7, 21);
__ vpslld(xmm0, xmm7, 21);
__ vpsllq(xmm0, xmm7, 21);
__ vpsrlw(xmm0, xmm7, 21);
__ vpsrld(xmm0, xmm7, 21);
__ vpsrlq(xmm0, xmm7, 21);