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Fix MIPS maddf and msubf instructions in simulator and tests.

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Tests were falling in qemu because of inexact computation in tests.
After correcting tests, simulator also had to be fixed.

Review-Url: https://codereview.chromium.org/2539133002
Cr-Commit-Position: refs/heads/master@{#41447}
This commit is contained in:
predrag.rudic 2016-12-02 01:11:47 -08:00 committed by Commit bot
parent 1a6dae8070
commit 11f0a0e819
4 changed files with 16 additions and 12 deletions
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8
src/mips/simulator-mips.cc
View File

@ -2537,11 +2537,11 @@ void Simulator::DecodeTypeRegisterDRsType() {
break;
case MADDF_D:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_double(fd_reg(), fd + (fs * ft));
set_fpu_register_double(fd_reg(), std::fma(fs, ft, fd));
break;
case MSUBF_D:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_double(fd_reg(), fd - (fs * ft));
set_fpu_register_double(fd_reg(), std::fma(-fs, ft, fd));
break;
case MUL_D:
set_fpu_register_double(
@ -2964,11 +2964,11 @@ void Simulator::DecodeTypeRegisterSRsType() {
break;
case MADDF_S:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_float(fd_reg(), fd + (fs * ft));
set_fpu_register_float(fd_reg(), std::fma(fs, ft, fd));
break;
case MSUBF_S:
DCHECK(IsMipsArchVariant(kMips32r6));
set_fpu_register_float(fd_reg(), fd - (fs * ft));
set_fpu_register_float(fd_reg(), std::fma(-fs, ft, fd));
break;
case MUL_S:
set_fpu_register_float(

8
src/mips64/simulator-mips64.cc
View File

@ -2475,11 +2475,11 @@ void Simulator::DecodeTypeRegisterSRsType() {
break;
case MADDF_S:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_float(fd_reg(), fd + (fs * ft));
set_fpu_register_float(fd_reg(), std::fma(fs, ft, fd));
break;
case MSUBF_S:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_float(fd_reg(), fd - (fs * ft));
set_fpu_register_float(fd_reg(), std::fma(-fs, ft, fd));
break;
case MUL_S:
set_fpu_register_float(
@ -2901,11 +2901,11 @@ void Simulator::DecodeTypeRegisterDRsType() {
break;
case MADDF_D:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_double(fd_reg(), fd + (fs * ft));
set_fpu_register_double(fd_reg(), std::fma(fs, ft, fd));
break;
case MSUBF_D:
DCHECK(kArchVariant == kMips64r6);
set_fpu_register_double(fd_reg(), fd - (fs * ft));
set_fpu_register_double(fd_reg(), std::fma(-fs, ft, fd));
break;
case MUL_D:
set_fpu_register_double(

6
test/cctest/test-assembler-mips.cc
View File

@ -5457,12 +5457,14 @@ void helper_madd_msub_maddf_msubf(F func) {
(CALL_GENERATED_CODE(isolate, f, &tc, 0, 0, 0, 0));
T res_add = tc.fr + (tc.fs * tc.ft);
T res_add = 0;
T res_sub = 0;
if (IsMipsArchVariant(kMips32r2)) {
res_add = (tc.fs * tc.ft) + tc.fr;
res_sub = (tc.fs * tc.ft) - tc.fr;
} else if (IsMipsArchVariant(kMips32r6)) {
res_sub = tc.fr - (tc.fs * tc.ft);
res_add = std::fma(tc.fs, tc.ft, tc.fr);
res_sub = std::fma(-tc.fs, tc.ft, tc.fr);
} else {
UNREACHABLE();
}

6
test/cctest/test-assembler-mips64.cc
View File

@ -6005,12 +6005,14 @@ void helper_madd_msub_maddf_msubf(F func) {
(CALL_GENERATED_CODE(isolate, f, &tc, 0, 0, 0, 0));
T res_add = tc.fr + (tc.fs * tc.ft);
T res_sub;
T res_add;
if (kArchVariant != kMips64r6) {
res_add = tc.fr + (tc.fs * tc.ft);
res_sub = (tc.fs * tc.ft) - tc.fr;
} else {
res_sub = tc.fr - (tc.fs * tc.ft);
res_add = std::fma(tc.fs, tc.ft, tc.fr);
res_sub = std::fma(-tc.fs, tc.ft, tc.fr);
}
CHECK_EQ(tc.fd_add, res_add);