MIPS: Fix transcendental cache on ARM in optimized code.
Port r12086 (84066033) BUG= TEST= Review URL: https://chromiumcodereview.appspot.com/10782023 Patch from Akos Palfi <palfia@homejinni.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@12132 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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@ -3533,23 +3533,23 @@ void TranscendentalCacheStub::Generate(MacroAssembler* masm) {
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1,
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1,
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1);
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1);
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} else {
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} else {
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if (!CpuFeatures::IsSupported(FPU)) UNREACHABLE();
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ASSERT(CpuFeatures::IsSupported(FPU));
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CpuFeatures::Scope scope(FPU);
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CpuFeatures::Scope scope(FPU);
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Label no_update;
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Label no_update;
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Label skip_cache;
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Label skip_cache;
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// Call C function to calculate the result and update the cache.
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// Call C function to calculate the result and update the cache.
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// Register a0 holds precalculated cache entry address; preserve
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// a0: precalculated cache entry address.
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// it on the stack and pop it into register cache_entry after the
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// a2 and a3: parts of the double value.
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// call.
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// Store a0, a2 and a3 on stack for later before calling C function.
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__ Push(cache_entry, a2, a3);
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__ Push(a3, a2, cache_entry);
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GenerateCallCFunction(masm, scratch0);
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GenerateCallCFunction(masm, scratch0);
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__ GetCFunctionDoubleResult(f4);
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__ GetCFunctionDoubleResult(f4);
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// Try to update the cache. If we cannot allocate a
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// Try to update the cache. If we cannot allocate a
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// heap number, we return the result without updating.
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// heap number, we return the result without updating.
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__ Pop(cache_entry, a2, a3);
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__ Pop(a3, a2, cache_entry);
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__ LoadRoot(t1, Heap::kHeapNumberMapRootIndex);
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__ LoadRoot(t1, Heap::kHeapNumberMapRootIndex);
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__ AllocateHeapNumber(t2, scratch0, scratch1, t1, &no_update);
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__ AllocateHeapNumber(t2, scratch0, scratch1, t1, &no_update);
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__ sdc1(f4, FieldMemOperand(t2, HeapNumber::kValueOffset));
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__ sdc1(f4, FieldMemOperand(t2, HeapNumber::kValueOffset));
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