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[wasm-simd] Implement i64x2 neg for ia32

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Bug: v8:9728
Change-Id: I0b90bf97fc8f57f8b372c3254d585c707da9fe7a
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1865255
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64434}
This commit is contained in:
Ng Zhi An 2019-10-17 15:42:01 -07:00 committed by Commit Bot
parent d1c35a4852
commit 2669f27daa
8 changed files with 19 additions and 2 deletions
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1
src/codegen/ia32/macro-assembler-ia32.h
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@ -291,6 +291,7 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
AVX_OP3_XO(Psubb, psubb)
AVX_OP3_XO(Psubw, psubw)
AVX_OP3_XO(Psubd, psubd)
AVX_OP3_XO(Psubq, psubq)
AVX_OP3_XO(Punpcklbw, punpcklbw)
AVX_OP3_XO(Punpckhbw, punpckhbw)
AVX_OP3_XO(Pxor, pxor)

1
src/codegen/ia32/sse-instr.h
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@ -38,6 +38,7 @@
V(psubb, 66, 0F, F8) \
V(psubw, 66, 0F, F9) \
V(psubd, 66, 0F, FA) \
V(psubq, 66, 0F, FB) \
V(psubsb, 66, 0F, E8) \
V(psubsw, 66, 0F, E9) \
V(psubusb, 66, 0F, D8) \

7
src/compiler/backend/ia32/code-generator-ia32.cc
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@ -2007,6 +2007,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ Pinsrd(i.OutputSimd128Register(), i.InputOperand(3), lane * 2 + 1);
break;
}
case kIA32I64x2Neg: {
XMMRegister dst = i.OutputSimd128Register();
Operand src = i.InputOperand(0);
__ Pxor(dst, dst);
__ Psubq(dst, src);
break;
}
case kSSEF32x4Splat: {
DCHECK_EQ(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
XMMRegister dst = i.OutputSimd128Register();

1
src/compiler/backend/ia32/instruction-codes-ia32.h
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@ -135,6 +135,7 @@ namespace compiler {
V(IA32F64x2Le) \
V(IA32I64x2SplatI32Pair) \
V(IA32I64x2ReplaceLaneI32Pair) \
V(IA32I64x2Neg) \
V(SSEF32x4Splat) \
V(AVXF32x4Splat) \
V(SSEF32x4ExtractLane) \

1
src/compiler/backend/ia32/instruction-scheduler-ia32.cc
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@ -116,6 +116,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kIA32F64x2Le:
case kIA32I64x2SplatI32Pair:
case kIA32I64x2ReplaceLaneI32Pair:
case kIA32I64x2Neg:
case kSSEF32x4Splat:
case kAVXF32x4Splat:
case kSSEF32x4ExtractLane:

6
src/compiler/backend/ia32/instruction-selector-ia32.cc
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@ -2104,6 +2104,12 @@ void InstructionSelector::VisitI64x2ReplaceLaneI32Pair(Node* node) {
low, high);
}
void InstructionSelector::VisitI64x2Neg(Node* node) {
IA32OperandGenerator g(this);
InstructionOperand operand0 = g.UseUnique(node->InputAt(0));
Emit(kIA32I64x2Neg, g.DefineAsRegister(node), operand0);
}
void InstructionSelector::VisitF32x4Splat(Node* node) {
VisitRRSimd(this, node, kAVXF32x4Splat, kSSEF32x4Splat);
}

2
src/compiler/backend/instruction-selector.cc
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@ -2659,11 +2659,11 @@ void InstructionSelector::VisitF64x2Lt(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF64x2Le(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF64x2Min(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF64x2Max(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2Neg(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_IA32
void InstructionSelector::VisitI64x2Splat(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2ExtractLane(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2ReplaceLane(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2Neg(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2Shl(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2ShrS(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI64x2Add(Node* node) { UNIMPLEMENTED(); }

2
test/cctest/wasm/test-run-wasm-simd.cc
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@ -942,7 +942,6 @@ WASM_SIMD_TEST_NO_LOWERING(I64x2ReplaceLane) {
}
}
#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
void RunI64x2UnOpTest(ExecutionTier execution_tier, LowerSimd lower_simd,
WasmOpcode opcode, Int64UnOp expected_op) {
WasmRunner<int32_t, int64_t> r(execution_tier, lower_simd);
@ -969,6 +968,7 @@ WASM_SIMD_TEST_NO_LOWERING(I64x2Neg) {
base::NegateWithWraparound);
}
#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
void RunI64x2ShiftOpTest(ExecutionTier execution_tier, LowerSimd lower_simd,
WasmOpcode opcode, Int64ShiftOp expected_op) {
// Intentionally shift by 64, should be no-op.