AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity

[wasm-simd][x64] Add AVX codegen for all true ops

Browse Source 
Bug: v8:9561
Change-Id: Ic57b38cefbdc21045d71601c67995d3568634c27
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2069400
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Cr-Commit-Position: refs/heads/master@{#66479}
This commit is contained in:
Ng Zhi An 2020-02-27 08:45:39 +00:00 committed by Commit Bot
parent 8d1c5f3344
commit 63d1879d94
6 changed files with 16 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/codegen/x64/assembler-x64.h
View File

@ -985,7 +985,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
} }
SSE4_INSTRUCTION_LIST(DECLARE_SSE4_INSTRUCTION) SSE4_INSTRUCTION_LIST(DECLARE_SSE4_INSTRUCTION)
SSE4_PMOV_INSTRUCTION_LIST(DECLARE_SSE4_INSTRUCTION) SSE4_UNOP_INSTRUCTION_LIST(DECLARE_SSE4_INSTRUCTION)
DECLARE_SSE4_INSTRUCTION(blendvpd, 66, 0F, 38, 15) DECLARE_SSE4_INSTRUCTION(blendvpd, 66, 0F, 38, 15)
#undef DECLARE_SSE4_INSTRUCTION #undef DECLARE_SSE4_INSTRUCTION
@ -1061,7 +1061,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
void v##instruction(XMMRegister dst, Operand src) { \ void v##instruction(XMMRegister dst, Operand src) { \
vinstr(0x##opcode, dst, xmm0, src, k##prefix, k##escape1##escape2, kW0); \ vinstr(0x##opcode, dst, xmm0, src, k##prefix, k##escape1##escape2, kW0); \
} }
SSE4_PMOV_INSTRUCTION_LIST(DECLARE_SSE4_PMOV_AVX_INSTRUCTION) SSE4_UNOP_INSTRUCTION_LIST(DECLARE_SSE4_PMOV_AVX_INSTRUCTION)
#undef DECLARE_SSE4_PMOV_AVX_INSTRUCTION #undef DECLARE_SSE4_PMOV_AVX_INSTRUCTION
void movd(XMMRegister dst, Register src); void movd(XMMRegister dst, Register src);

3
src/codegen/x64/macro-assembler-x64.h
View File

@ -158,6 +158,8 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
AVX_OP(Movss, movss) AVX_OP(Movss, movss)
AVX_OP(Movsd, movsd) AVX_OP(Movsd, movsd)
AVX_OP(Movdqu, movdqu) AVX_OP(Movdqu, movdqu)
AVX_OP(Pcmpeqb, pcmpeqb)
AVX_OP(Pcmpeqw, pcmpeqw)
AVX_OP(Pcmpeqd, pcmpeqd) AVX_OP(Pcmpeqd, pcmpeqd)
AVX_OP(Addss, addss) AVX_OP(Addss, addss)
AVX_OP(Addsd, addsd) AVX_OP(Addsd, addsd)
@ -244,6 +246,7 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
AVX_OP_SSE4_1(Insertps, insertps) AVX_OP_SSE4_1(Insertps, insertps)
AVX_OP_SSE4_1(Pinsrq, pinsrq) AVX_OP_SSE4_1(Pinsrq, pinsrq)
AVX_OP_SSE4_1(Pblendw, pblendw) AVX_OP_SSE4_1(Pblendw, pblendw)
AVX_OP_SSE4_1(Ptest, ptest)
AVX_OP_SSE4_1(Pmovsxbw, pmovsxbw) AVX_OP_SSE4_1(Pmovsxbw, pmovsxbw)
AVX_OP_SSE4_1(Pmovsxwd, pmovsxwd) AVX_OP_SSE4_1(Pmovsxwd, pmovsxwd)
AVX_OP_SSE4_1(Pmovsxdq, pmovsxdq) AVX_OP_SSE4_1(Pmovsxdq, pmovsxdq)

4
src/codegen/x64/sse-instr.h
View File

@ -143,7 +143,6 @@
#define SSE4_INSTRUCTION_LIST(V) \ #define SSE4_INSTRUCTION_LIST(V) \
V(pcmpeqq, 66, 0F, 38, 29) \ V(pcmpeqq, 66, 0F, 38, 29) \
V(ptest, 66, 0F, 38, 17) \
V(packusdw, 66, 0F, 38, 2B) \ V(packusdw, 66, 0F, 38, 2B) \
V(pminsb, 66, 0F, 38, 38) \ V(pminsb, 66, 0F, 38, 38) \
V(pminsd, 66, 0F, 38, 39) \ V(pminsd, 66, 0F, 38, 39) \
@ -156,7 +155,8 @@
V(pmulld, 66, 0F, 38, 40) V(pmulld, 66, 0F, 38, 40)
// SSE instructions whose AVX version has two operands. // SSE instructions whose AVX version has two operands.
#define SSE4_PMOV_INSTRUCTION_LIST(V) \ #define SSE4_UNOP_INSTRUCTION_LIST(V) \
V(ptest, 66, 0F, 38, 17) \
V(pmovsxbw, 66, 0F, 38, 20) \ V(pmovsxbw, 66, 0F, 38, 20) \
V(pmovsxwd, 66, 0F, 38, 23) \ V(pmovsxwd, 66, 0F, 38, 23) \
V(pmovsxdq, 66, 0F, 38, 25) \ V(pmovsxdq, 66, 0F, 38, 25) \

10
src/compiler/backend/x64/code-generator-x64.cc
View File

@ -595,9 +595,9 @@ void EmitWordLoadPoisoningIfNeeded(CodeGenerator* codegen,
XMMRegister tmp2 = i.TempSimd128Register(1); \ XMMRegister tmp2 = i.TempSimd128Register(1); \
__ movq(tmp1, Immediate(1)); \ __ movq(tmp1, Immediate(1)); \
__ xorq(dst, dst); \ __ xorq(dst, dst); \
__ pxor(tmp2, tmp2); \ __ Pxor(tmp2, tmp2); \
__ opcode(tmp2, i.InputSimd128Register(0)); \ __ opcode(tmp2, i.InputSimd128Register(0)); \
__ ptest(tmp2, tmp2); \ __ Ptest(tmp2, tmp2); \
__ cmovq(zero, dst, tmp1); \ __ cmovq(zero, dst, tmp1); \
} while (false) } while (false)
@ -3941,15 +3941,15 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
case kX64S1x4AllTrue: { case kX64S1x4AllTrue: {
ASSEMBLE_SIMD_ALL_TRUE(pcmpeqd); ASSEMBLE_SIMD_ALL_TRUE(Pcmpeqd);
break; break;
} }
case kX64S1x8AllTrue: { case kX64S1x8AllTrue: {
ASSEMBLE_SIMD_ALL_TRUE(pcmpeqw); ASSEMBLE_SIMD_ALL_TRUE(Pcmpeqw);
break; break;
} }
case kX64S1x16AllTrue: { case kX64S1x16AllTrue: {
ASSEMBLE_SIMD_ALL_TRUE(pcmpeqb); ASSEMBLE_SIMD_ALL_TRUE(Pcmpeqb);
break; break;
} }
case kWord32AtomicExchangeInt8: { case kWord32AtomicExchangeInt8: {

4
src/diagnostics/x64/disasm-x64.cc
View File

@ -937,7 +937,7 @@ int DisassemblerX64::AVXInstruction(byte* data) {
break; \ break; \
} }
SSSE3_UNOP_INSTRUCTION_LIST(DECLARE_SSE_UNOP_AVX_DIS_CASE) SSSE3_UNOP_INSTRUCTION_LIST(DECLARE_SSE_UNOP_AVX_DIS_CASE)
SSE4_PMOV_INSTRUCTION_LIST(DECLARE_SSE_UNOP_AVX_DIS_CASE) SSE4_UNOP_INSTRUCTION_LIST(DECLARE_SSE_UNOP_AVX_DIS_CASE)
#undef DECLARE_SSE_UNOP_AVX_DIS_CASE #undef DECLARE_SSE_UNOP_AVX_DIS_CASE
default: default:
@ -1812,7 +1812,7 @@ int DisassemblerX64::TwoByteOpcodeInstruction(byte* data) {
SSSE3_INSTRUCTION_LIST(SSE34_DIS_CASE) SSSE3_INSTRUCTION_LIST(SSE34_DIS_CASE)
SSSE3_UNOP_INSTRUCTION_LIST(SSE34_DIS_CASE) SSSE3_UNOP_INSTRUCTION_LIST(SSE34_DIS_CASE)
SSE4_INSTRUCTION_LIST(SSE34_DIS_CASE) SSE4_INSTRUCTION_LIST(SSE34_DIS_CASE)
SSE4_PMOV_INSTRUCTION_LIST(SSE34_DIS_CASE) SSE4_UNOP_INSTRUCTION_LIST(SSE34_DIS_CASE)
SSE4_2_INSTRUCTION_LIST(SSE34_DIS_CASE) SSE4_2_INSTRUCTION_LIST(SSE34_DIS_CASE)
#undef SSE34_DIS_CASE #undef SSE34_DIS_CASE
default: default:

4
test/cctest/test-disasm-x64.cc
View File

@ -572,7 +572,7 @@ TEST(DisasmX64) {
__ blendvpd(xmm5, Operand(rdx, 4)); __ blendvpd(xmm5, Operand(rdx, 4));
SSE4_INSTRUCTION_LIST(EMIT_SSE34_INSTR) SSE4_INSTRUCTION_LIST(EMIT_SSE34_INSTR)
SSE4_PMOV_INSTRUCTION_LIST(EMIT_SSE34_INSTR) SSE4_UNOP_INSTRUCTION_LIST(EMIT_SSE34_INSTR)
SSE4_EXTRACT_INSTRUCTION_LIST(EMIT_SSE34_IMM_INSTR) SSE4_EXTRACT_INSTRUCTION_LIST(EMIT_SSE34_IMM_INSTR)
} }
} }
@ -751,7 +751,7 @@ TEST(DisasmX64) {
notUsed4) \ notUsed4) \
__ v##instruction(xmm10, xmm1); \ __ v##instruction(xmm10, xmm1); \
__ v##instruction(xmm10, Operand(rdx, 4)); __ v##instruction(xmm10, Operand(rdx, 4));
SSE4_PMOV_INSTRUCTION_LIST(EMIT_SSE4_PMOV_AVXINSTR) SSE4_UNOP_INSTRUCTION_LIST(EMIT_SSE4_PMOV_AVXINSTR)
#undef EMIT_SSE4_PMOV_AVXINSTR #undef EMIT_SSE4_PMOV_AVXINSTR
#define EMIT_SSE2_SHIFT_IMM_AVX(instruction, notUsed1, notUsed2, notUsed3, \ #define EMIT_SSE2_SHIFT_IMM_AVX(instruction, notUsed1, notUsed2, notUsed3, \