[riscv] Fix cctest/test-assembler-riscv*/RISCV_UTEST_FLOAT_WIDENING_vfwredosum_vv.

Correct the test expect result as the spec specifies the accumulator is 2*SEW
bits. Fix the simulator implementation as well.

R=qiuji@iscas.ac.cn

Change-Id: Ia5d11b3214cf32635c3767df75992b2a50ee6980
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3878452
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#83354}
This commit is contained in:
Ting Chou 2022-09-07 16:25:05 +08:00 committed by V8 LUCI CQ
parent 0d85646664
commit 831ef4e6c8
3 changed files with 7 additions and 3 deletions

View File

@ -6861,7 +6861,7 @@ void Simulator::DecodeRvvFVV() {
}
case E32: {
double& vd = Rvvelt<double>(rvv_vd_reg(), 0, true);
float vs1 = Rvvelt<float>(rvv_vs1_reg(), 0);
double vs1 = Rvvelt<double>(rvv_vs1_reg(), 0);
double alu_out = vs1;
for (uint64_t i = rvv_vstart(); i < rvv_vl(); ++i) {
double vs2 = static_cast<double>(Rvvelt<float>(rvv_vs2_reg(), i));

View File

@ -2314,7 +2314,9 @@ UTEST_RVV_FMA_VF_FORM_WITH_RES(vfnmsac_vf, ARRAY_FLOAT,
for (float rs1_fval : compiler::ValueHelper::GetVector<float>()) { \
std::vector<double> temp_arr(kRvvVLEN / 32, \
static_cast<double>(rs1_fval)); \
double expect_res = rs1_fval; \
double expect_res = base::bit_cast<double>( \
(uint64_t)base::bit_cast<uint32_t>(rs1_fval) << 32 | \
base::bit_cast<uint32_t>(rs1_fval)); \
for (double val : temp_arr) { \
expect_res += val; \
if (std::isnan(expect_res)) { \

View File

@ -2578,7 +2578,9 @@ UTEST_RVV_FMA_VF_FORM_WITH_RES(vfnmsac_vf, ARRAY_FLOAT,
for (float rs1_fval : compiler::ValueHelper::GetVector<float>()) { \
std::vector<double> temp_arr(kRvvVLEN / 32, \
static_cast<double>(rs1_fval)); \
double expect_res = rs1_fval; \
double expect_res = base::bit_cast<double>( \
(uint64_t)base::bit_cast<uint32_t>(rs1_fval) << 32 | \
base::bit_cast<uint32_t>(rs1_fval)); \
for (double val : temp_arr) { \
expect_res += val; \
if (std::isnan(expect_res)) { \