[riscv] Fix cctest/test-assembler-riscv*/RISCV_UTEST_FLOAT_WIDENING_vfwredosum_vv.
Correct the test expect result as the spec specifies the accumulator is 2*SEW bits. Fix the simulator implementation as well. R=qiuji@iscas.ac.cn Change-Id: Ia5d11b3214cf32635c3767df75992b2a50ee6980 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3878452 Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Reviewed-by: Yahan Lu <yahan@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#83354}
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@ -6861,7 +6861,7 @@ void Simulator::DecodeRvvFVV() {
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}
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case E32: {
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double& vd = Rvvelt<double>(rvv_vd_reg(), 0, true);
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float vs1 = Rvvelt<float>(rvv_vs1_reg(), 0);
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double vs1 = Rvvelt<double>(rvv_vs1_reg(), 0);
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double alu_out = vs1;
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for (uint64_t i = rvv_vstart(); i < rvv_vl(); ++i) {
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double vs2 = static_cast<double>(Rvvelt<float>(rvv_vs2_reg(), i));
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@ -2314,7 +2314,9 @@ UTEST_RVV_FMA_VF_FORM_WITH_RES(vfnmsac_vf, ARRAY_FLOAT,
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for (float rs1_fval : compiler::ValueHelper::GetVector<float>()) { \
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std::vector<double> temp_arr(kRvvVLEN / 32, \
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static_cast<double>(rs1_fval)); \
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double expect_res = rs1_fval; \
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double expect_res = base::bit_cast<double>( \
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(uint64_t)base::bit_cast<uint32_t>(rs1_fval) << 32 | \
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base::bit_cast<uint32_t>(rs1_fval)); \
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for (double val : temp_arr) { \
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expect_res += val; \
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if (std::isnan(expect_res)) { \
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@ -2578,7 +2578,9 @@ UTEST_RVV_FMA_VF_FORM_WITH_RES(vfnmsac_vf, ARRAY_FLOAT,
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for (float rs1_fval : compiler::ValueHelper::GetVector<float>()) { \
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std::vector<double> temp_arr(kRvvVLEN / 32, \
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static_cast<double>(rs1_fval)); \
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double expect_res = rs1_fval; \
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double expect_res = base::bit_cast<double>( \
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(uint64_t)base::bit_cast<uint32_t>(rs1_fval) << 32 | \
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base::bit_cast<uint32_t>(rs1_fval)); \
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for (double val : temp_arr) { \
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expect_res += val; \
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if (std::isnan(expect_res)) { \
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