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[arm] Drop SMMLS support.

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Apparently

 SMMLS r, b, c, a

computes

 r = ((a << 32) - b * c) >> 32

while the documentation is kinda misleading and states that it should
compute

 r = a - ((b * c) >> 32)

The actual behavior is kinda useless, so we drop the instruction again.

TEST=cctest,unittests
TBR=dcarney@chromium.org

Review URL: https://codereview.chromium.org/654653004

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24577 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
bmeurer@chromium.org 2014-10-14 07:47:27 +00:00
parent 8950e0a3de
commit 8a00950303
9 changed files with 0 additions and 82 deletions
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8
src/arm/assembler-arm.cc
View File

@ -1587,14 +1587,6 @@ void Assembler::smmla(Register dst, Register src1, Register src2, Register srcA,
}
void Assembler::smmls(Register dst, Register src1, Register src2, Register srcA,
Condition cond) {
DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc));
emit(cond | B26 | B25 | B24 | B22 | B20 | dst.code() * B16 |
srcA.code() * B12 | src2.code() * B8 | B7 | B6 | B4 | src1.code());
}
void Assembler::smmul(Register dst, Register src1, Register src2,
Condition cond) {
DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc));

3
src/arm/assembler-arm.h
View File

@ -978,9 +978,6 @@ class Assembler : public AssemblerBase {
void smmla(Register dst, Register src1, Register src2, Register srcA,
Condition cond = al);
void smmls(Register dst, Register src1, Register src2, Register srcA,
Condition cond = al);
void smmul(Register dst, Register src1, Register src2, Condition cond = al);
void smlal(Register dstL, Register dstH, Register src1, Register src2,

5
src/arm/disasm-arm.cc
View File

@ -1097,11 +1097,6 @@ void Decoder::DecodeType3(Instruction* instr) {
}
case db_x: {
if (instr->Bits(22, 20) == 0x5) {
if (instr->Bits(7, 4) == 0xd) {
// SMMLS (in V8 notation matching ARM ISA format)
Format(instr, "smmls'cond 'rn, 'rm, 'rs, 'rd");
break;
}
if (instr->Bits(7, 4) == 0x1) {
if (instr->Bits(15, 12) == 0xF) {
Format(instr, "smmul'cond 'rn, 'rm, 'rs");

13
src/arm/simulator-arm.cc
View File

@ -2711,19 +2711,6 @@ void Simulator::DecodeType3(Instruction* instr) {
}
case db_x: {
if (instr->Bits(22, 20) == 0x5) {
if (instr->Bits(7, 4) == 0xd) {
// SMMLS (in V8 notation matching ARM ISA format)
// Format(instr, "smmls'cond 'rn, 'rm, 'rs, 'rd");
int rm = instr->RmValue();
int32_t rm_val = get_register(rm);
int rs = instr->RsValue();
int32_t rs_val = get_register(rs);
int rd = instr->RdValue();
int32_t rd_val = get_register(rd);
rn_val = base::bits::SignedMulHighAndSub32(rm_val, rs_val, rd_val);
set_register(rn, rn_val);
return;
}
if (instr->Bits(7, 4) == 0x1) {
int rm = instr->RmValue();
int32_t rm_val = get_register(rm);

7
src/base/bits.cc
View File

@ -32,13 +32,6 @@ int32_t SignedMulHighAndAdd32(int32_t lhs, int32_t rhs, int32_t acc) {
bit_cast<uint32_t>(SignedMulHigh32(lhs, rhs)));
}
int32_t SignedMulHighAndSub32(int32_t lhs, int32_t rhs, int32_t acc) {
return bit_cast<int32_t>(bit_cast<uint32_t>(acc) -
bit_cast<uint32_t>(SignedMulHigh32(lhs, rhs)));
}
} // namespace bits
} // namespace base
} // namespace v8

6
src/base/bits.h
View File

@ -199,12 +199,6 @@ int32_t SignedMulHigh32(int32_t lhs, int32_t rhs);
// adds the accumulate value |acc|.
int32_t SignedMulHighAndAdd32(int32_t lhs, int32_t rhs, int32_t acc);
// SignedMulHighAndAdd32(lhs, rhs, acc) multiplies two signed 32-bit values
// |lhs| and |rhs|, extracts the most significant 32 bits of the result, and
// subtracts it from the accumulate value |acc|.
int32_t SignedMulHighAndSub32(int32_t lhs, int32_t rhs, int32_t acc);
} // namespace bits
} // namespace base
} // namespace v8

26
test/cctest/test-assembler-arm.cc
View File

@ -1524,32 +1524,6 @@ TEST(smmla) {
}
TEST(smmls) {
CcTest::InitializeVM();
Isolate* const isolate = CcTest::i_isolate();
HandleScope scope(isolate);
RandomNumberGenerator* const rng = isolate->random_number_generator();
Assembler assm(isolate, nullptr, 0);
__ smmls(r1, r1, r2, r3);
__ str(r1, MemOperand(r0));
__ bx(lr);
CodeDesc desc;
assm.GetCode(&desc);
Handle<Code> code = isolate->factory()->NewCode(
desc, Code::ComputeFlags(Code::STUB), Handle<Code>());
#ifdef OBJECT_PRINT
code->Print(std::cout);
#endif
F3 f = FUNCTION_CAST<F3>(code->entry());
for (size_t i = 0; i < 128; ++i) {
int32_t r, x = rng->NextInt(), y = rng->NextInt(), z = rng->NextInt();
Object* dummy = CALL_GENERATED_CODE(f, &r, x, y, z, 0);
CHECK_EQ(bits::SignedMulHighAndSub32(x, y, z), r);
USE(dummy);
}
}
TEST(smmul) {
CcTest::InitializeVM();
Isolate* const isolate = CcTest::i_isolate();

3
test/cctest/test-disasm-arm.cc
View File

@ -420,9 +420,6 @@ TEST(Type3) {
"e6cf3474 uxtb16 r3, r4, ror #8");
}
COMPARE(smmls(r0, r1, r2, r3), "e75032d1 smmls r0, r1, r2, r3");
COMPARE(smmls(r10, r9, r8, r7), "e75a78d9 smmls r10, r9, r8, r7");
COMPARE(smmla(r0, r1, r2, r3), "e7503211 smmla r0, r1, r2, r3");
COMPARE(smmla(r10, r9, r8, r7), "e75a7819 smmla r10, r9, r8, r7");

11
test/unittests/base/bits-unittest.cc
View File

@ -224,17 +224,6 @@ TEST(Bits, SignedMulHighAndAdd32) {
}
}
TEST(Bits, SignedMulHighAndSub32) {
TRACED_FORRANGE(int32_t, i, 1, 50) {
EXPECT_EQ(i, SignedMulHighAndSub32(0, 0, i));
TRACED_FORRANGE(int32_t, j, 1, i) {
EXPECT_EQ(i, SignedMulHighAndSub32(j, j, i));
}
EXPECT_EQ(i - 1, SignedMulHighAndSub32(1024 * 1024 * 1024, 4, i));
}
}
} // namespace bits
} // namespace base
} // namespace v8