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[turbofan]IA: ChangeFloat32ToFloat64 supports mem operand

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BUG=
R=titzer@chromium.org

Review URL: https://codereview.chromium.org/641153003

Patch from Jing Bao <jing.bao@intel.com>.

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24542 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
This commit is contained in:
dcarney@chromium.org 2014-10-13 07:42:35 +00:00
parent 3396c2badd
commit 907ad65dce
8 changed files with 47 additions and 9 deletions
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2
src/compiler/ia32/code-generator-ia32.cc
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@ -351,7 +351,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
__ sqrtsd(i.OutputDoubleRegister(), i.InputOperand(0)); __ sqrtsd(i.OutputDoubleRegister(), i.InputOperand(0));
break; break;
case kSSECvtss2sd: case kSSECvtss2sd:
__ cvtss2sd(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); __ cvtss2sd(i.OutputDoubleRegister(), i.InputOperand(0));
break; break;
case kSSECvtsd2ss: case kSSECvtsd2ss:
__ cvtsd2ss(i.OutputDoubleRegister(), i.InputOperand(0)); __ cvtsd2ss(i.OutputDoubleRegister(), i.InputOperand(0));

3
src/compiler/ia32/instruction-selector-ia32.cc
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@ -499,8 +499,7 @@ void InstructionSelector::VisitUint32Mod(Node* node) {
void InstructionSelector::VisitChangeFloat32ToFloat64(Node* node) { void InstructionSelector::VisitChangeFloat32ToFloat64(Node* node) {
IA32OperandGenerator g(this); IA32OperandGenerator g(this);
// TODO(turbofan): IA32 SSE conversions should take an operand. Emit(kSSECvtss2sd, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
Emit(kSSECvtss2sd, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)));
} }

4
src/compiler/x64/code-generator-x64.cc
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@ -405,7 +405,11 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
} }
break; break;
case kSSECvtss2sd: case kSSECvtss2sd:
if (instr->InputAt(0)->IsDoubleRegister()) {
__ cvtss2sd(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); __ cvtss2sd(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
} else {
__ cvtss2sd(i.OutputDoubleRegister(), i.InputOperand(0));
}
break; break;
case kSSECvtsd2ss: case kSSECvtsd2ss:
if (instr->InputAt(0)->IsDoubleRegister()) { if (instr->InputAt(0)->IsDoubleRegister()) {

3
src/compiler/x64/instruction-selector-x64.cc
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@ -608,8 +608,7 @@ void InstructionSelector::VisitUint64Mod(Node* node) {
void InstructionSelector::VisitChangeFloat32ToFloat64(Node* node) { void InstructionSelector::VisitChangeFloat32ToFloat64(Node* node) {
X64OperandGenerator g(this); X64OperandGenerator g(this);
// TODO(turbofan): X64 SSE conversions should take an operand. Emit(kSSECvtss2sd, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
Emit(kSSECvtss2sd, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)));
} }

2
src/ia32/assembler-ia32.cc
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@ -1951,7 +1951,7 @@ void Assembler::cvtsi2sd(XMMRegister dst, const Operand& src) {
} }
void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { void Assembler::cvtss2sd(XMMRegister dst, const Operand& src) {
EnsureSpace ensure_space(this); EnsureSpace ensure_space(this);
EMIT(0xF3); EMIT(0xF3);
EMIT(0x0F); EMIT(0x0F);

6
src/ia32/assembler-ia32.h
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@ -958,12 +958,14 @@ class Assembler : public AssemblerBase {
void cvtsi2sd(XMMRegister dst, Register src) { cvtsi2sd(dst, Operand(src)); } void cvtsi2sd(XMMRegister dst, Register src) { cvtsi2sd(dst, Operand(src)); }
void cvtsi2sd(XMMRegister dst, const Operand& src); void cvtsi2sd(XMMRegister dst, const Operand& src);
void cvtss2sd(XMMRegister dst, XMMRegister src); void cvtss2sd(XMMRegister dst, const Operand& src);
void cvtss2sd(XMMRegister dst, XMMRegister src) {
cvtss2sd(dst, Operand(src));
}
void cvtsd2ss(XMMRegister dst, const Operand& src); void cvtsd2ss(XMMRegister dst, const Operand& src);
void cvtsd2ss(XMMRegister dst, XMMRegister src) { void cvtsd2ss(XMMRegister dst, XMMRegister src) {
cvtsd2ss(dst, Operand(src)); cvtsd2ss(dst, Operand(src));
} }
void addsd(XMMRegister dst, XMMRegister src); void addsd(XMMRegister dst, XMMRegister src);
void addsd(XMMRegister dst, const Operand& src); void addsd(XMMRegister dst, const Operand& src);
void subsd(XMMRegister dst, XMMRegister src); void subsd(XMMRegister dst, XMMRegister src);

32
test/cctest/compiler/test-run-machops.cc
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@ -4339,6 +4339,38 @@ TEST(RunChangeFloat32ToFloat64) {
} }
TEST(RunChangeFloat32ToFloat64_spilled) {
RawMachineAssemblerTester<int32_t> m;
const int kNumInputs = 32;
int32_t magic = 0x786234;
float input[kNumInputs];
double result[kNumInputs];
Node* input_node[kNumInputs];
for (int i = 0; i < kNumInputs; i++) {
input_node[i] =
m.Load(kMachFloat32, m.PointerConstant(&input), m.Int32Constant(i * 4));
}
for (int i = 0; i < kNumInputs; i++) {
m.Store(kMachFloat64, m.PointerConstant(&result), m.Int32Constant(i * 8),
m.ChangeFloat32ToFloat64(input_node[i]));
}
m.Return(m.Int32Constant(magic));
for (int i = 0; i < kNumInputs; i++) {
input[i] = 100.9f + i;
}
CHECK_EQ(magic, m.Call());
for (int i = 0; i < kNumInputs; i++) {
CHECK_EQ(result[i], static_cast<double>(input[i]));
}
}
TEST(RunTruncateFloat64ToFloat32) { TEST(RunTruncateFloat64ToFloat32) {
float actual = 0.0f; float actual = 0.0f;
double input = 0.0; double input = 0.0;

2
test/cctest/test-disasm-ia32.cc
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@ -413,6 +413,8 @@ TEST(DisasmIa320) {
{ {
__ cvttss2si(edx, Operand(ebx, ecx, times_4, 10000)); __ cvttss2si(edx, Operand(ebx, ecx, times_4, 10000));
__ cvtsi2sd(xmm1, Operand(ebx, ecx, times_4, 10000)); __ cvtsi2sd(xmm1, Operand(ebx, ecx, times_4, 10000));
__ cvtss2sd(xmm1, Operand(ebx, ecx, times_4, 10000));
__ cvtss2sd(xmm1, xmm0);
__ movsd(xmm1, Operand(ebx, ecx, times_4, 10000)); __ movsd(xmm1, Operand(ebx, ecx, times_4, 10000));
__ movsd(Operand(ebx, ecx, times_4, 10000), xmm1); __ movsd(Operand(ebx, ecx, times_4, 10000), xmm1);
// 128 bit move instructions. // 128 bit move instructions.