[turbofan]IA: ChangeFloat32ToFloat64 supports mem operand
BUG= R=titzer@chromium.org Review URL: https://codereview.chromium.org/641153003 Patch from Jing Bao <jing.bao@intel.com>. git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24542 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
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@ -351,7 +351,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
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__ sqrtsd(i.OutputDoubleRegister(), i.InputOperand(0));
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break;
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case kSSECvtss2sd:
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__ cvtss2sd(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
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__ cvtss2sd(i.OutputDoubleRegister(), i.InputOperand(0));
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break;
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case kSSECvtsd2ss:
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__ cvtsd2ss(i.OutputDoubleRegister(), i.InputOperand(0));
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@ -499,8 +499,7 @@ void InstructionSelector::VisitUint32Mod(Node* node) {
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void InstructionSelector::VisitChangeFloat32ToFloat64(Node* node) {
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IA32OperandGenerator g(this);
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// TODO(turbofan): IA32 SSE conversions should take an operand.
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Emit(kSSECvtss2sd, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)));
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Emit(kSSECvtss2sd, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
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}
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@ -405,7 +405,11 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
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}
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break;
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case kSSECvtss2sd:
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if (instr->InputAt(0)->IsDoubleRegister()) {
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__ cvtss2sd(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
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} else {
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__ cvtss2sd(i.OutputDoubleRegister(), i.InputOperand(0));
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}
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break;
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case kSSECvtsd2ss:
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if (instr->InputAt(0)->IsDoubleRegister()) {
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@ -608,8 +608,7 @@ void InstructionSelector::VisitUint64Mod(Node* node) {
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void InstructionSelector::VisitChangeFloat32ToFloat64(Node* node) {
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X64OperandGenerator g(this);
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// TODO(turbofan): X64 SSE conversions should take an operand.
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Emit(kSSECvtss2sd, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)));
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Emit(kSSECvtss2sd, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
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}
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@ -1951,7 +1951,7 @@ void Assembler::cvtsi2sd(XMMRegister dst, const Operand& src) {
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}
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void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
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void Assembler::cvtss2sd(XMMRegister dst, const Operand& src) {
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EnsureSpace ensure_space(this);
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EMIT(0xF3);
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EMIT(0x0F);
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@ -958,12 +958,14 @@ class Assembler : public AssemblerBase {
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void cvtsi2sd(XMMRegister dst, Register src) { cvtsi2sd(dst, Operand(src)); }
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void cvtsi2sd(XMMRegister dst, const Operand& src);
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void cvtss2sd(XMMRegister dst, XMMRegister src);
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void cvtss2sd(XMMRegister dst, const Operand& src);
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void cvtss2sd(XMMRegister dst, XMMRegister src) {
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cvtss2sd(dst, Operand(src));
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}
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void cvtsd2ss(XMMRegister dst, const Operand& src);
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void cvtsd2ss(XMMRegister dst, XMMRegister src) {
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cvtsd2ss(dst, Operand(src));
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}
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void addsd(XMMRegister dst, XMMRegister src);
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void addsd(XMMRegister dst, const Operand& src);
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void subsd(XMMRegister dst, XMMRegister src);
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@ -4339,6 +4339,38 @@ TEST(RunChangeFloat32ToFloat64) {
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}
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TEST(RunChangeFloat32ToFloat64_spilled) {
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RawMachineAssemblerTester<int32_t> m;
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const int kNumInputs = 32;
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int32_t magic = 0x786234;
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float input[kNumInputs];
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double result[kNumInputs];
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Node* input_node[kNumInputs];
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for (int i = 0; i < kNumInputs; i++) {
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input_node[i] =
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m.Load(kMachFloat32, m.PointerConstant(&input), m.Int32Constant(i * 4));
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}
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for (int i = 0; i < kNumInputs; i++) {
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m.Store(kMachFloat64, m.PointerConstant(&result), m.Int32Constant(i * 8),
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m.ChangeFloat32ToFloat64(input_node[i]));
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}
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m.Return(m.Int32Constant(magic));
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for (int i = 0; i < kNumInputs; i++) {
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input[i] = 100.9f + i;
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}
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CHECK_EQ(magic, m.Call());
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for (int i = 0; i < kNumInputs; i++) {
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CHECK_EQ(result[i], static_cast<double>(input[i]));
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}
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}
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TEST(RunTruncateFloat64ToFloat32) {
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float actual = 0.0f;
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double input = 0.0;
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@ -413,6 +413,8 @@ TEST(DisasmIa320) {
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{
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__ cvttss2si(edx, Operand(ebx, ecx, times_4, 10000));
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__ cvtsi2sd(xmm1, Operand(ebx, ecx, times_4, 10000));
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__ cvtss2sd(xmm1, Operand(ebx, ecx, times_4, 10000));
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__ cvtss2sd(xmm1, xmm0);
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__ movsd(xmm1, Operand(ebx, ecx, times_4, 10000));
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__ movsd(Operand(ebx, ecx, times_4, 10000), xmm1);
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// 128 bit move instructions.
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