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[mips][wasm-simd] Implement I32x4DotI16x8S

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Change-Id: Ie187d6ec848414d725b18b9a20be3c65f94f86ba
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2477752
Reviewed-by: Zhi An Ng <zhin@chromium.org>
Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Cr-Commit-Position: refs/heads/master@{#70580}
This commit is contained in:
Zhao Jiazhong 2020-10-16 13:53:01 +08:00 committed by Commit Bot
parent 3aa1e67fc0
commit bb09b6acd5
8 changed files with 18 additions and 0 deletions
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6
src/compiler/backend/mips/code-generator-mips.cc
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@ -2585,6 +2585,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ copy_u_b(dst, scratch0, 0);
break;
}
case kMipsI32x4DotI16x8S: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ dotp_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMipsI16x8Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fill_h(i.OutputSimd128Register(), i.InputRegister(0));

1
src/compiler/backend/mips/instruction-codes-mips.h
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@ -217,6 +217,7 @@ namespace compiler {
V(MipsI32x4GeU) \
V(MipsI32x4Abs) \
V(MipsI32x4BitMask) \
V(MipsI32x4DotI16x8S) \
V(MipsI16x8Splat) \
V(MipsI16x8ExtractLaneU) \
V(MipsI16x8ExtractLaneS) \

1
src/compiler/backend/mips/instruction-scheduler-mips.cc
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@ -180,6 +180,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsI32x4UConvertI16x8Low:
case kMipsI32x4Abs:
case kMipsI32x4BitMask:
case kMipsI32x4DotI16x8S:
case kMipsI8x16Add:
case kMipsI8x16AddSatS:
case kMipsI8x16AddSatU:

1
src/compiler/backend/mips/instruction-selector-mips.cc
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@ -2191,6 +2191,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I32x4GeU, kMipsI32x4GeU) \
V(I32x4Abs, kMipsI32x4Abs) \
V(I32x4BitMask, kMipsI32x4BitMask) \
V(I32x4DotI16x8S, kMipsI32x4DotI16x8S) \
V(I16x8Add, kMipsI16x8Add) \
V(I16x8AddSatS, kMipsI16x8AddSatS) \
V(I16x8AddSatU, kMipsI16x8AddSatU) \

6
src/compiler/backend/mips64/code-generator-mips64.cc
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@ -2763,6 +2763,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ copy_u_b(dst, scratch0, 0);
break;
}
case kMips64I32x4DotI16x8S: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ dotp_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
case kMips64I16x8Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fill_h(i.OutputSimd128Register(), i.InputRegister(0));

1
src/compiler/backend/mips64/instruction-codes-mips64.h
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@ -252,6 +252,7 @@ namespace compiler {
V(Mips64I32x4GeU) \
V(Mips64I32x4Abs) \
V(Mips64I32x4BitMask) \
V(Mips64I32x4DotI16x8S) \
V(Mips64I16x8Splat) \
V(Mips64I16x8ExtractLaneU) \
V(Mips64I16x8ExtractLaneS) \

1
src/compiler/backend/mips64/instruction-scheduler-mips64.cc
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@ -213,6 +213,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64I32x4UConvertI16x8Low:
case kMips64I32x4Abs:
case kMips64I32x4BitMask:
case kMips64I32x4DotI16x8S:
case kMips64I8x16Add:
case kMips64I8x16AddSatS:
case kMips64I8x16AddSatU:

1
src/compiler/backend/mips64/instruction-selector-mips64.cc
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@ -2871,6 +2871,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I32x4GeS, kMips64I32x4GeS) \
V(I32x4GtU, kMips64I32x4GtU) \
V(I32x4GeU, kMips64I32x4GeU) \
V(I32x4DotI16x8S, kMips64I32x4DotI16x8S) \
V(I16x8Add, kMips64I16x8Add) \
V(I16x8AddSatS, kMips64I16x8AddSatS) \
V(I16x8AddSatU, kMips64I16x8AddSatU) \