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MIPS: Fix improper use of odd FP reg on mips32r6

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Odd numbered floating-point register shouldn't be used as compare register
on mips32r6 architecture. In case cpu switches to FRE mode, writes to odd
numbered single-precision fp register will update upper part of even
double-precision register, which will corrupt the even register.

BUG=

Review-Url: https://codereview.chromium.org/2591063003
Cr-Commit-Position: refs/heads/master@{#41916}
This commit is contained in:
dusan.simicic 2016-12-22 02:06:18 -08:00 committed by Commit bot
parent 1e994192d6
commit cc77bd8234
2 changed files with 3 additions and 4 deletions
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5
src/mips/assembler-mips.h
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@ -68,7 +68,7 @@ namespace internal {
#define ALLOCATABLE_DOUBLE_REGISTERS(V) \
V(f0) V(f2) V(f4) V(f6) V(f8) V(f10) V(f12) V(f14) \
V(f16) V(f18) V(f20) V(f22) V(f24) V(f26)
V(f16) V(f18) V(f20) V(f22) V(f24)
// clang-format on
// CPU Registers.
@ -282,8 +282,7 @@ const DoubleRegister f31 = {31};
#define kLithiumScratchDouble f30
#define kDoubleRegZero f28
// Used on mips32r6 for compare operations.
// We use the last non-callee saved odd register for O32 ABI
#define kDoubleCompareReg f19
#define kDoubleCompareReg f26
// FPU (coprocessor 1) control registers.
// Currently only FCSR (#31) is implemented.

2
test/cctest/test-macro-assembler-mips.cc
View File

@ -532,7 +532,7 @@ TEST(cvt_s_w_Trunc_uw_s) {
uint32_t input = *i;
auto fn = [](MacroAssembler* masm) {
__ cvt_s_w(f0, f4);
__ Trunc_uw_s(f2, f0, f1);
__ Trunc_uw_s(f2, f0, f6);
};
CHECK_EQ(static_cast<float>(input), run_Cvt<uint32_t>(input, fn));
}