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Unify assembler for packed double-precision floats

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We reuse PACKED_OP_LIST to generate *pd instructions. Introduce a new pd
base method, similar to ps and vps.

Bug: v8:9396
Change-Id: Id9d81c22c9110935484fd929ef7bf5cc20e9ae7e
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1834767
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64117}
This commit is contained in:
Ng Zhi An 2019-10-02 11:05:48 -07:00 committed by Commit Bot
parent fe78dd71a7
commit d05b2d3e3d
4 changed files with 79 additions and 51 deletions
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33
src/codegen/ia32/assembler-ia32.cc
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@ -2163,14 +2163,6 @@ void Assembler::divsd(XMMRegister dst, Operand src) {
emit_sse_operand(dst, src);
}
void Assembler::xorpd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
EMIT(0x57);
emit_sse_operand(dst, src);
}
void Assembler::rcpps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
@ -2217,22 +2209,6 @@ void Assembler::haddps(XMMRegister dst, Operand src) {
emit_sse_operand(dst, src);
}
void Assembler::andpd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
EMIT(0x54);
emit_sse_operand(dst, src);
}
void Assembler::orpd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
EMIT(0x56);
emit_sse_operand(dst, src);
}
void Assembler::ucomisd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x66);
@ -2731,6 +2707,15 @@ void Assembler::ps(byte opcode, XMMRegister dst, Operand src) {
emit_sse_operand(dst, src);
}
// Packed double-precision floating-point SSE instructions.
void Assembler::pd(byte opcode, XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
EMIT(opcode);
emit_sse_operand(dst, src);
}
// AVX instructions
void Assembler::vfmasd(byte op, XMMRegister dst, XMMRegister src1,
Operand src2) {

23
src/codegen/ia32/assembler-ia32.h
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@ -927,16 +927,9 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
void mulsd(XMMRegister dst, Operand src);
void divsd(XMMRegister dst, XMMRegister src) { divsd(dst, Operand(src)); }
void divsd(XMMRegister dst, Operand src);
void xorpd(XMMRegister dst, XMMRegister src) { xorpd(dst, Operand(src)); }
void xorpd(XMMRegister dst, Operand src);
void sqrtsd(XMMRegister dst, XMMRegister src) { sqrtsd(dst, Operand(src)); }
void sqrtsd(XMMRegister dst, Operand src);
void andpd(XMMRegister dst, XMMRegister src) { andpd(dst, Operand(src)); }
void andpd(XMMRegister dst, Operand src);
void orpd(XMMRegister dst, XMMRegister src) { orpd(dst, Operand(src)); }
void orpd(XMMRegister dst, Operand src);
void ucomisd(XMMRegister dst, XMMRegister src) { ucomisd(dst, Operand(src)); }
void ucomisd(XMMRegister dst, Operand src);
@ -1491,6 +1484,8 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
// Implementation of packed single-precision floating-point SSE instructions.
void ps(byte op, XMMRegister dst, Operand src);
// Implementation of packed double-precision floating-point SSE instructions.
void pd(byte op, XMMRegister dst, Operand src);
#define PACKED_OP_LIST(V) \
V(and, 0x54) \
@ -1504,11 +1499,15 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
V(div, 0x5e) \
V(max, 0x5f)
#define SSE_PACKED_OP_DECLARE(name, opcode) \
void name##ps(XMMRegister dst, XMMRegister src) { \
ps(opcode, dst, Operand(src)); \
} \
void name##ps(XMMRegister dst, Operand src) { ps(opcode, dst, src); }
#define SSE_PACKED_OP_DECLARE(name, opcode) \
void name##ps(XMMRegister dst, XMMRegister src) { \
ps(opcode, dst, Operand(src)); \
} \
void name##ps(XMMRegister dst, Operand src) { ps(opcode, dst, src); } \
void name##pd(XMMRegister dst, XMMRegister src) { \
pd(opcode, dst, Operand(src)); \
} \
void name##pd(XMMRegister dst, Operand src) { pd(opcode, dst, src); }
PACKED_OP_LIST(SSE_PACKED_OP_DECLARE)
#undef SSE_PACKED_OP_DECLARE

49
src/diagnostics/ia32/disasm-ia32.cc
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@ -1079,6 +1079,11 @@ int DisassemblerIA32::AVXInstruction(byte* data) {
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x56:
AppendToBuffer("vorps %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x57:
AppendToBuffer("vxorps %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
@ -1147,6 +1152,16 @@ int DisassemblerIA32::AVXInstruction(byte* data) {
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x55:
AppendToBuffer("vandnpd %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x56:
AppendToBuffer("vorpd %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x57:
AppendToBuffer("vxorpd %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
@ -2171,27 +2186,31 @@ int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer,
AppendToBuffer("movmskpd %s,%s", NameOfCPURegister(regop),
NameOfXMMRegister(rm));
data++;
} else if (*data == 0x54) {
} else if (*data >= 0x54 && *data <= 0x59) {
const char* const pseudo_op[] = {
"andpd", "andnpd", "orpd", "xorpd", "addpd", "mulpd",
};
byte op = *data;
data++;
int mod, regop, rm;
get_modrm(*data, &mod, &regop, &rm);
AppendToBuffer("andpd %s,%s", NameOfXMMRegister(regop),
NameOfXMMRegister(rm));
data++;
} else if (*data == 0x56) {
AppendToBuffer("%s %s,", pseudo_op[op - 0x54],
NameOfXMMRegister(regop));
data += PrintRightXMMOperand(data);
} else if (*data >= 0x5c && *data <= 0x5f) {
const char* const pseudo_op[] = {
"subpd",
"minpd",
"divpd",
"maxpd",
};
byte op = *data;
data++;
int mod, regop, rm;
get_modrm(*data, &mod, &regop, &rm);
AppendToBuffer("orpd %s,%s", NameOfXMMRegister(regop),
NameOfXMMRegister(rm));
data++;
} else if (*data == 0x57) {
data++;
int mod, regop, rm;
get_modrm(*data, &mod, &regop, &rm);
AppendToBuffer("xorpd %s,%s", NameOfXMMRegister(regop),
NameOfXMMRegister(rm));
data++;
AppendToBuffer("%s %s,", pseudo_op[op - 0x5c],
NameOfXMMRegister(regop));
data += PrintRightXMMOperand(data);
} else if (*data == 0x6E) {
data++;
int mod, regop, rm;

25
test/cctest/test-disasm-ia32.cc
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@ -492,6 +492,25 @@ TEST(DisasmIa320) {
__ cmpltsd(xmm0, xmm1);
__ andpd(xmm0, xmm1);
__ andpd(xmm0, Operand(ebx, ecx, times_4, 10000));
__ andnpd(xmm0, xmm1);
__ andnpd(xmm0, Operand(ebx, ecx, times_4, 10000));
__ orpd(xmm0, xmm1);
__ orpd(xmm0, Operand(ebx, ecx, times_4, 10000));
__ xorpd(xmm0, xmm1);
__ xorpd(xmm0, Operand(ebx, ecx, times_4, 10000));
__ addpd(xmm1, xmm0);
__ addpd(xmm1, Operand(ebx, ecx, times_4, 10000));
__ subpd(xmm1, xmm0);
__ subpd(xmm1, Operand(ebx, ecx, times_4, 10000));
__ mulpd(xmm1, xmm0);
__ mulpd(xmm1, Operand(ebx, ecx, times_4, 10000));
__ divpd(xmm1, xmm0);
__ divpd(xmm1, Operand(ebx, ecx, times_4, 10000));
__ minpd(xmm1, xmm0);
__ minpd(xmm1, Operand(ebx, ecx, times_4, 10000));
__ maxpd(xmm1, xmm0);
__ maxpd(xmm1, Operand(ebx, ecx, times_4, 10000));
__ psllw(xmm0, 17);
__ pslld(xmm0, 17);
@ -625,6 +644,8 @@ TEST(DisasmIa320) {
__ vandps(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vandnps(xmm0, xmm1, xmm2);
__ vandnps(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vorps(xmm0, xmm1, xmm2);
__ vorps(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vxorps(xmm0, xmm1, xmm2);
__ vxorps(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vaddps(xmm0, xmm1, xmm2);
@ -662,6 +683,10 @@ TEST(DisasmIa320) {
__ vandpd(xmm0, xmm1, xmm2);
__ vandpd(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vandnpd(xmm0, xmm1, xmm2);
__ vandnpd(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vorpd(xmm0, xmm1, xmm2);
__ vorpd(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vxorpd(xmm0, xmm1, xmm2);
__ vxorpd(xmm0, xmm1, Operand(ebx, ecx, times_4, 10000));
__ vaddpd(xmm0, xmm1, xmm2);