PPC: [wasm-simd] Implement simd comparisons
Change-Id: I782f5b0dd8ed374df406fb615f6e74efed8b5368 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2235658 Reviewed-by: Junliang Yan <jyan@ca.ibm.com> Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com> Cr-Commit-Position: refs/heads/master@{#68267}
This commit is contained in:
Milad Farazmand
Commit Bot
parent
2ef37fb675
commit
ea0a1561c1
@ -487,6 +487,21 @@ class Assembler : public AssemblerBase {
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PPC_VA_OPCODE_A_FORM_LIST(DECLARE_PPC_VA_INSTRUCTIONS_A_FORM)
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#undef DECLARE_PPC_VA_INSTRUCTIONS_A_FORM
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#define DECLARE_PPC_VC_INSTRUCTIONS(name, instr_name, instr_value) \
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inline void name(const Simd128Register rt, const Simd128Register ra, \
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const Simd128Register rb, const RCBit rc = LeaveRC) { \
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vc_form(instr_name, rt, ra, rb, rc); \
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}
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inline void vc_form(Instr instr, Simd128Register rt, Simd128Register ra,
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Simd128Register rb, int rc) {
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emit(instr | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 |
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rc * B10);
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}
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PPC_VC_OPCODE_LIST(DECLARE_PPC_VC_INSTRUCTIONS)
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#undef DECLARE_PPC_VC_INSTRUCTIONS
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RegList* GetScratchRegisterList() { return &scratch_register_list_; }
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// ---------------------------------------------------------------------------
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// Code generation
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@ -2610,6 +2610,206 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_F64x2Eq: {
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__ xvcmpeqdp(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_F64x2Ne: {
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__ xvcmpeqdp(kScratchDoubleReg, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vnor(i.OutputSimd128Register(), kScratchDoubleReg, kScratchDoubleReg);
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break;
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}
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case kPPC_F64x2Le: {
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__ xvcmpgedp(i.OutputSimd128Register(), i.InputSimd128Register(1),
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i.InputSimd128Register(0));
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break;
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}
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case kPPC_F64x2Lt: {
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__ xvcmpgtdp(i.OutputSimd128Register(), i.InputSimd128Register(1),
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i.InputSimd128Register(0));
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break;
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}
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case kPPC_F32x4Eq: {
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__ xvcmpeqsp(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_I64x2Eq: {
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__ vcmpequd(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_I32x4Eq: {
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__ vcmpequw(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_I16x8Eq: {
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__ vcmpequh(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_I8x16Eq: {
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__ vcmpequb(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_F32x4Ne: {
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__ xvcmpeqsp(kScratchDoubleReg, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vnor(i.OutputSimd128Register(), kScratchDoubleReg, kScratchDoubleReg);
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break;
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}
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case kPPC_I64x2Ne: {
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__ vcmpequd(kScratchDoubleReg, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vnor(i.OutputSimd128Register(), kScratchDoubleReg, kScratchDoubleReg);
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break;
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}
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case kPPC_I32x4Ne: {
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__ vcmpequw(kScratchDoubleReg, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vnor(i.OutputSimd128Register(), kScratchDoubleReg, kScratchDoubleReg);
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break;
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}
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case kPPC_I16x8Ne: {
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__ vcmpequh(kScratchDoubleReg, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vnor(i.OutputSimd128Register(), kScratchDoubleReg, kScratchDoubleReg);
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break;
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}
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case kPPC_I8x16Ne: {
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__ vcmpequb(kScratchDoubleReg, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vnor(i.OutputSimd128Register(), kScratchDoubleReg, kScratchDoubleReg);
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break;
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}
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case kPPC_F32x4Lt: {
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__ xvcmpgtsp(i.OutputSimd128Register(), i.InputSimd128Register(1),
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i.InputSimd128Register(0));
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break;
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}
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case kPPC_F32x4Le: {
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__ xvcmpgesp(i.OutputSimd128Register(), i.InputSimd128Register(1),
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i.InputSimd128Register(0));
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break;
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}
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case kPPC_I64x2GtS: {
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__ vcmpgtsd(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_I32x4GtS: {
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__ vcmpgtsw(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_I64x2GeS: {
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__ vcmpequd(kScratchDoubleReg, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vcmpgtsd(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vor(i.OutputSimd128Register(), i.OutputSimd128Register(),
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kScratchDoubleReg);
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break;
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}
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case kPPC_I32x4GeS: {
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__ vcmpequw(kScratchDoubleReg, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vcmpgtsw(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vor(i.OutputSimd128Register(), i.OutputSimd128Register(),
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kScratchDoubleReg);
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break;
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}
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case kPPC_I64x2GtU: {
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__ vcmpgtud(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_I32x4GtU: {
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__ vcmpgtuw(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_I64x2GeU: {
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__ vcmpequd(kScratchDoubleReg, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vcmpgtud(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vor(i.OutputSimd128Register(), i.OutputSimd128Register(),
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kScratchDoubleReg);
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break;
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}
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case kPPC_I32x4GeU: {
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__ vcmpequw(kScratchDoubleReg, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vcmpgtuw(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vor(i.OutputSimd128Register(), i.OutputSimd128Register(),
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kScratchDoubleReg);
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break;
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}
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case kPPC_I16x8GtS: {
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__ vcmpgtsh(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_I16x8GeS: {
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__ vcmpequh(kScratchDoubleReg, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vcmpgtsh(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vor(i.OutputSimd128Register(), i.OutputSimd128Register(),
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kScratchDoubleReg);
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break;
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}
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case kPPC_I16x8GtU: {
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__ vcmpgtuh(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_I16x8GeU: {
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__ vcmpequh(kScratchDoubleReg, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vcmpgtuh(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vor(i.OutputSimd128Register(), i.OutputSimd128Register(),
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kScratchDoubleReg);
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break;
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}
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case kPPC_I8x16GtS: {
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__ vcmpgtsb(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_I8x16GeS: {
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__ vcmpequb(kScratchDoubleReg, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vcmpgtsb(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vor(i.OutputSimd128Register(), i.OutputSimd128Register(),
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kScratchDoubleReg);
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break;
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}
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case kPPC_I8x16GtU: {
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__ vcmpgtub(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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break;
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}
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case kPPC_I8x16GeU: {
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__ vcmpequb(kScratchDoubleReg, i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vcmpgtub(i.OutputSimd128Register(), i.InputSimd128Register(0),
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i.InputSimd128Register(1));
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__ vor(i.OutputSimd128Register(), i.OutputSimd128Register(),
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kScratchDoubleReg);
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break;
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}
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case kPPC_StoreCompressTagged: {
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ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX);
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break;
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@ -196,6 +196,10 @@ namespace compiler {
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V(PPC_F64x2Add) \
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V(PPC_F64x2Sub) \
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V(PPC_F64x2Mul) \
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V(PPC_F64x2Eq) \
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V(PPC_F64x2Ne) \
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V(PPC_F64x2Le) \
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V(PPC_F64x2Lt) \
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V(PPC_F32x4Splat) \
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V(PPC_F32x4ExtractLane) \
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V(PPC_F32x4ReplaceLane) \
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@ -203,6 +207,10 @@ namespace compiler {
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V(PPC_F32x4AddHoriz) \
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V(PPC_F32x4Sub) \
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V(PPC_F32x4Mul) \
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V(PPC_F32x4Eq) \
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V(PPC_F32x4Ne) \
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V(PPC_F32x4Lt) \
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V(PPC_F32x4Le) \
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V(PPC_I64x2Splat) \
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V(PPC_I64x2ExtractLane) \
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V(PPC_I64x2ReplaceLane) \
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@ -213,6 +221,12 @@ namespace compiler {
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V(PPC_I64x2MinU) \
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V(PPC_I64x2MaxS) \
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V(PPC_I64x2MaxU) \
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V(PPC_I64x2Eq) \
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V(PPC_I64x2Ne) \
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V(PPC_I64x2GtS) \
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V(PPC_I64x2GtU) \
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V(PPC_I64x2GeU) \
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V(PPC_I64x2GeS) \
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V(PPC_I32x4Splat) \
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V(PPC_I32x4ExtractLane) \
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V(PPC_I32x4ReplaceLane) \
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@ -224,6 +238,12 @@ namespace compiler {
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V(PPC_I32x4MinU) \
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V(PPC_I32x4MaxS) \
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V(PPC_I32x4MaxU) \
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V(PPC_I32x4Eq) \
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V(PPC_I32x4Ne) \
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V(PPC_I32x4GtS) \
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V(PPC_I32x4GeS) \
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V(PPC_I32x4GtU) \
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V(PPC_I32x4GeU) \
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V(PPC_I16x8Splat) \
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V(PPC_I16x8ExtractLaneU) \
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V(PPC_I16x8ExtractLaneS) \
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@ -236,6 +256,12 @@ namespace compiler {
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V(PPC_I16x8MinU) \
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V(PPC_I16x8MaxS) \
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V(PPC_I16x8MaxU) \
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V(PPC_I16x8Eq) \
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V(PPC_I16x8Ne) \
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V(PPC_I16x8GtS) \
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V(PPC_I16x8GeS) \
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V(PPC_I16x8GtU) \
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V(PPC_I16x8GeU) \
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V(PPC_I8x16Splat) \
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V(PPC_I8x16ExtractLaneU) \
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V(PPC_I8x16ExtractLaneS) \
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@ -247,6 +273,12 @@ namespace compiler {
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V(PPC_I8x16MinU) \
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V(PPC_I8x16MaxS) \
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V(PPC_I8x16MaxU) \
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V(PPC_I8x16Eq) \
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V(PPC_I8x16Ne) \
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V(PPC_I8x16GtS) \
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V(PPC_I8x16GeS) \
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V(PPC_I8x16GtU) \
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V(PPC_I8x16GeU) \
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V(PPC_StoreCompressTagged) \
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V(PPC_LoadDecompressTaggedSigned) \
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V(PPC_LoadDecompressTaggedPointer) \
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@ -119,6 +119,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kPPC_F64x2Add:
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case kPPC_F64x2Sub:
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case kPPC_F64x2Mul:
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case kPPC_F64x2Eq:
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case kPPC_F64x2Ne:
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case kPPC_F64x2Le:
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case kPPC_F64x2Lt:
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case kPPC_F32x4Splat:
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case kPPC_F32x4ExtractLane:
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case kPPC_F32x4ReplaceLane:
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@ -126,6 +130,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kPPC_F32x4AddHoriz:
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case kPPC_F32x4Sub:
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case kPPC_F32x4Mul:
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case kPPC_F32x4Eq:
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case kPPC_F32x4Ne:
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case kPPC_F32x4Lt:
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case kPPC_F32x4Le:
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case kPPC_I64x2Splat:
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case kPPC_I64x2ExtractLane:
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case kPPC_I64x2ReplaceLane:
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@ -136,6 +144,12 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kPPC_I64x2MinU:
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case kPPC_I64x2MaxS:
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case kPPC_I64x2MaxU:
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case kPPC_I64x2Eq:
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case kPPC_I64x2Ne:
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case kPPC_I64x2GtS:
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case kPPC_I64x2GtU:
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case kPPC_I64x2GeU:
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case kPPC_I64x2GeS:
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case kPPC_I32x4Splat:
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case kPPC_I32x4ExtractLane:
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case kPPC_I32x4ReplaceLane:
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@ -147,6 +161,12 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kPPC_I32x4MinU:
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case kPPC_I32x4MaxS:
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case kPPC_I32x4MaxU:
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case kPPC_I32x4Eq:
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case kPPC_I32x4Ne:
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case kPPC_I32x4GtS:
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case kPPC_I32x4GeS:
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case kPPC_I32x4GtU:
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case kPPC_I32x4GeU:
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case kPPC_I16x8Splat:
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case kPPC_I16x8ExtractLaneU:
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case kPPC_I16x8ExtractLaneS:
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@ -159,6 +179,12 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kPPC_I16x8MinU:
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case kPPC_I16x8MaxS:
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case kPPC_I16x8MaxU:
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case kPPC_I16x8Eq:
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case kPPC_I16x8Ne:
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case kPPC_I16x8GtS:
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case kPPC_I16x8GeS:
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case kPPC_I16x8GtU:
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case kPPC_I16x8GeU:
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case kPPC_I8x16Splat:
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case kPPC_I8x16ExtractLaneU:
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case kPPC_I8x16ExtractLaneS:
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@ -170,6 +196,12 @@ int InstructionScheduler::GetTargetInstructionFlags(
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case kPPC_I8x16MinU:
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case kPPC_I8x16MaxS:
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case kPPC_I8x16MaxU:
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case kPPC_I8x16Eq:
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case kPPC_I8x16Ne:
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case kPPC_I8x16GtS:
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case kPPC_I8x16GeS:
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case kPPC_I8x16GtU:
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case kPPC_I8x16GeU:
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return kNoOpcodeFlags;
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case kPPC_LoadWordS8:
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@ -2131,10 +2131,18 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
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V(F64x2Add) \
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V(F64x2Sub) \
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V(F64x2Mul) \
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V(F64x2Eq) \
|
||||
V(F64x2Ne) \
|
||||
V(F64x2Le) \
|
||||
V(F64x2Lt) \
|
||||
V(F32x4Add) \
|
||||
V(F32x4AddHoriz) \
|
||||
V(F32x4Sub) \
|
||||
V(F32x4Mul) \
|
||||
V(F32x4Eq) \
|
||||
V(F32x4Ne) \
|
||||
V(F32x4Lt) \
|
||||
V(F32x4Le) \
|
||||
V(I64x2Add) \
|
||||
V(I64x2Sub) \
|
||||
V(I64x2Mul) \
|
||||
@ -2146,6 +2154,12 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
|
||||
V(I32x4MinU) \
|
||||
V(I32x4MaxS) \
|
||||
V(I32x4MaxU) \
|
||||
V(I32x4Eq) \
|
||||
V(I32x4Ne) \
|
||||
V(I32x4GtS) \
|
||||
V(I32x4GeS) \
|
||||
V(I32x4GtU) \
|
||||
V(I32x4GeU) \
|
||||
V(I16x8Add) \
|
||||
V(I16x8AddHoriz) \
|
||||
V(I16x8Sub) \
|
||||
@ -2154,13 +2168,25 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
|
||||
V(I16x8MinU) \
|
||||
V(I16x8MaxS) \
|
||||
V(I16x8MaxU) \
|
||||
V(I16x8Eq) \
|
||||
V(I16x8Ne) \
|
||||
V(I16x8GtS) \
|
||||
V(I16x8GeS) \
|
||||
V(I16x8GtU) \
|
||||
V(I16x8GeU) \
|
||||
V(I8x16Add) \
|
||||
V(I8x16Sub) \
|
||||
V(I8x16Mul) \
|
||||
V(I8x16MinS) \
|
||||
V(I8x16MinU) \
|
||||
V(I8x16MaxS) \
|
||||
V(I8x16MaxU)
|
||||
V(I8x16MaxU) \
|
||||
V(I8x16Eq) \
|
||||
V(I8x16Ne) \
|
||||
V(I8x16GtS) \
|
||||
V(I8x16GeS) \
|
||||
V(I8x16GtU) \
|
||||
V(I8x16GeU)
|
||||
|
||||
#define SIMD_VISIT_SPLAT(Type) \
|
||||
void InstructionSelector::Visit##Type##Splat(Node* node) { \
|
||||
@ -2216,22 +2242,10 @@ void InstructionSelector::VisitI32x4Shl(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI32x4ShrS(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI32x4Eq(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI32x4Ne(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI32x4ShrU(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI32x4Neg(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI32x4GtS(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI32x4GeS(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI32x4GtU(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI32x4GeU(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI16x8Shl(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI16x8ShrS(Node* node) { UNIMPLEMENTED(); }
|
||||
@ -2246,10 +2260,6 @@ void InstructionSelector::VisitI16x8SubSaturateS(Node* node) {
|
||||
UNIMPLEMENTED();
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitI16x8Eq(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI16x8Ne(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI16x8AddSaturateU(Node* node) {
|
||||
UNIMPLEMENTED();
|
||||
}
|
||||
@ -2260,14 +2270,6 @@ void InstructionSelector::VisitI16x8SubSaturateU(Node* node) {
|
||||
|
||||
void InstructionSelector::VisitI16x8Neg(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI16x8GtS(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI16x8GeS(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI16x8GtU(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI16x8GeU(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI16x8RoundingAverageU(Node* node) {
|
||||
UNIMPLEMENTED();
|
||||
}
|
||||
@ -2286,14 +2288,6 @@ void InstructionSelector::VisitI8x16SubSaturateS(Node* node) {
|
||||
UNIMPLEMENTED();
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitI8x16Eq(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI8x16Ne(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI8x16GtS(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI8x16GeS(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI8x16AddSaturateU(Node* node) {
|
||||
UNIMPLEMENTED();
|
||||
}
|
||||
@ -2302,10 +2296,6 @@ void InstructionSelector::VisitI8x16SubSaturateU(Node* node) {
|
||||
UNIMPLEMENTED();
|
||||
}
|
||||
|
||||
void InstructionSelector::VisitI8x16GtU(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI8x16GeU(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitS128And(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitS128Or(Node* node) { UNIMPLEMENTED(); }
|
||||
@ -2318,14 +2308,6 @@ void InstructionSelector::VisitS128AndNot(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitS128Zero(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitF32x4Eq(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitF32x4Ne(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitF32x4Lt(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitF32x4Le(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::EmitPrepareResults(
|
||||
ZoneVector<PushParameter>* results, const CallDescriptor* call_descriptor,
|
||||
Node* node) {
|
||||
@ -2462,14 +2444,6 @@ void InstructionSelector::VisitF64x2Sqrt(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitF64x2Div(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitF64x2Eq(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitF64x2Ne(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitF64x2Lt(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitF64x2Le(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI64x2Neg(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
void InstructionSelector::VisitI64x2Shl(Node* node) { UNIMPLEMENTED(); }
|
||||
|
||||
Loading…
Reference in New Issue
Block a user