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[mips64][wasm-simd] Implement v128.load32_zero v128.load64_zero

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Port 9124b7f973
https://chromium-review.googlesource.com/c/v8/v8/+/2485250

Port f89869a213
https://chromium-review.googlesource.com/c/v8/v8/+/2486236

Bug: v8:11038
Change-Id: Ia524e6ca11650b35916f1a78e7c859a570146a50
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2513870
Reviewed-by: Zhi An Ng <zhin@chromium.org>
Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Cr-Commit-Position: refs/heads/master@{#70937}
This commit is contained in:
Zhao Jiazhong 2020-11-02 14:13:44 +08:00 committed by Commit Bot
parent a63243f8f6
commit efff3d18ec
5 changed files with 36 additions and 0 deletions
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16
src/compiler/backend/mips64/code-generator-mips64.cc
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@ -1949,6 +1949,22 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ ilvr_w(dst, kSimd128RegZero, dst); __ ilvr_w(dst, kSimd128RegZero, dst);
break; break;
} }
case kMips64S128Load32Zero: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register dst = i.OutputSimd128Register();
__ xor_v(dst, dst, dst);
__ Lwu(kScratchReg, i.MemoryOperand());
__ insert_w(dst, 0, kScratchReg);
break;
}
case kMips64S128Load64Zero: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register dst = i.OutputSimd128Register();
__ xor_v(dst, dst, dst);
__ Ld(kScratchReg, i.MemoryOperand());
__ insert_d(dst, 0, kScratchReg);
break;
}
case kWord32AtomicLoadInt8: case kWord32AtomicLoadInt8:
ASSEMBLE_ATOMIC_LOAD_INTEGER(Lb); ASSEMBLE_ATOMIC_LOAD_INTEGER(Lb);
break; break;

2
src/compiler/backend/mips64/instruction-codes-mips64.h
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@ -359,6 +359,8 @@ namespace compiler {
V(Mips64S128Load16x4U) \ V(Mips64S128Load16x4U) \
V(Mips64S128Load32x2S) \ V(Mips64S128Load32x2S) \
V(Mips64S128Load32x2U) \ V(Mips64S128Load32x2U) \
V(Mips64S128Load32Zero) \
V(Mips64S128Load64Zero) \
V(Mips64MsaLd) \ V(Mips64MsaLd) \
V(Mips64MsaSt) \ V(Mips64MsaSt) \
V(Mips64I32x4SConvertI16x8Low) \ V(Mips64I32x4SConvertI16x8Low) \

2
src/compiler/backend/mips64/instruction-scheduler-mips64.cc
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@ -359,6 +359,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64S128Load16x4U: case kMips64S128Load16x4U:
case kMips64S128Load32x2S: case kMips64S128Load32x2S:
case kMips64S128Load32x2U: case kMips64S128Load32x2U:
case kMips64S128Load32Zero:
case kMips64S128Load64Zero:
case kMips64Word64AtomicLoadUint8: case kMips64Word64AtomicLoadUint8:
case kMips64Word64AtomicLoadUint16: case kMips64Word64AtomicLoadUint16:
case kMips64Word64AtomicLoadUint32: case kMips64Word64AtomicLoadUint32:

6
src/compiler/backend/mips64/instruction-selector-mips64.cc
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@ -416,6 +416,12 @@ void InstructionSelector::VisitLoadTransform(Node* node) {
case LoadTransformation::kS128Load32x2U: case LoadTransformation::kS128Load32x2U:
opcode = kMips64S128Load32x2U; opcode = kMips64S128Load32x2U;
break; break;
case LoadTransformation::kS128Load32Zero:
opcode = kMips64S128Load32Zero;
break;
case LoadTransformation::kS128Load64Zero:
opcode = kMips64S128Load64Zero;
break;
default: default:
UNIMPLEMENTED(); UNIMPLEMENTED();
} }

10
src/wasm/baseline/mips64/liftoff-assembler-mips64.h
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@ -1509,6 +1509,16 @@ void LiftoffAssembler::LoadTransform(LiftoffRegister dst, Register src_addr,
fill_d(dst_msa, scratch); fill_d(dst_msa, scratch);
ilvr_w(dst_msa, kSimd128RegZero, dst_msa); ilvr_w(dst_msa, kSimd128RegZero, dst_msa);
} }
} else if (transform == LoadTransformationKind::kZeroExtend) {
xor_v(dst_msa, dst_msa, dst_msa);
if (memtype == MachineType::Int32()) {
Lwu(scratch, src_op);
insert_w(dst_msa, 0, scratch);
} else {
DCHECK_EQ(MachineType::Int64(), memtype);
Ld(scratch, src_op);
insert_d(dst_msa, 0, scratch);
}
} else { } else {
DCHECK_EQ(LoadTransformationKind::kSplat, transform); DCHECK_EQ(LoadTransformationKind::kSplat, transform);
if (memtype == MachineType::Int8()) { if (memtype == MachineType::Int8()) {