Commit Graph

28 Commits

Author SHA1 Message Date
jarin
56673804e0 [turbofan] Store nodes use only MachineRepresentation, not MachineType.
Review URL: https://codereview.chromium.org/1513383003

Cr-Commit-Position: refs/heads/master@{#32803}
2015-12-11 15:34:16 +00:00
jarin
bb2a830deb [turbofan] Make MachineType a pair of enums.
MachineType is now a class with two enum fields:
- MachineRepresentation
- MachineSemantic

Both enums are usable on their own, and this change switches some places from using MachineType to use just MachineRepresentation. Most notably:
- register allocator now uses just the representation.
- Phi and Select nodes only refer to representations.

Review URL: https://codereview.chromium.org/1513543003

Cr-Commit-Position: refs/heads/master@{#32738}
2015-12-10 09:03:53 +00:00
mstarzinger
26fc85aae3 [turbofan] Cleanup RawMachineAssembler::Store interface.
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/1424983003

Cr-Commit-Position: refs/heads/master@{#31646}
2015-10-29 09:22:25 +00:00
rmcilroy
c0c214daa8 [Interpreter] Add support for loading from / storing to outer context variables.
Adds support for loading from and storing to outer context
variables. Also adds support for declaring functions on contexts and
locals. Finally, fixes a couple of issues with StaContextSlot where
we weren't emitting the write barrier and therefore would crash in the
GC.

Also added code so that --print-bytecode will output the
function name before the bytecodes, and replaces MachineType with StoreRepresentation in RawMachineAssembler::Store and updates tests.

BUG=v8:4280
LOG=N

Review URL: https://codereview.chromium.org/1425633002

Cr-Commit-Position: refs/heads/master@{#31584}
2015-10-26 18:11:35 +00:00
Weiliang Lin
38e764f7ac [x86] Introduce vandps/vandpd/vxorps/vxorpd.
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/1072343002

Cr-Commit-Position: refs/heads/master@{#27768}
2015-04-11 00:58:38 +00:00
Benedikt Meurer
9af9f1d026 [turbofan] Add new Float32Abs and Float64Abs operators.
These operators compute the absolute floating point value of some
arbitrary input, and are implemented without any branches (i.e. using
vabs on arm, and andps/andpd on x86).

R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/1066393002

Cr-Commit-Position: refs/heads/master@{#27662}
2015-04-08 11:55:04 +00:00
bmeurer
a1b2c275b7 [x64] Match -0 - x with sign bit flip.
We can use xorps/xorpd on Intel CPUs to flip the sign bit. Ideally we'd
use a RIP-relative 128-bit constant in the code object, as OCaml/GCC
does, however that requires 128-bit alignment for code objects, which is
not yet implemented. So for now we materialize the mask inline.

R=dcarney@chromium.org

Review URL: https://codereview.chromium.org/1046893002

Cr-Commit-Position: refs/heads/master@{#27611}
2015-04-07 07:35:03 +00:00
bmeurer
8dad78cdbd [turbofan] Add backend support for float32 operations.
This adds the basics necessary to support float32 operations in TurboFan.
The actual functionality required to detect safe float32 operations will
be added based on this later. Therefore this does not affect production
code except for some cleanup/refactoring.

In detail, this patchset contains the following features:
- Add support for float32 operations to arm, arm64, ia32 and x64
  backends.
- Add float32 machine operators.
- Add support for float32 constants to simplified lowering.
- Handle float32 representation for phis in simplified lowering.

In addition, contains the following (related) cleanups:
- Fix/unify naming of backend instructions.
- Use AVX comparisons when available.
- Extend ArchOpcodeField to 9 bits (required for arm64).
- Refactor some code duplication in instruction selectors.

BUG=v8:3589
LOG=n
R=dcarney@chromium.org

Review URL: https://codereview.chromium.org/1044793002

Cr-Commit-Position: refs/heads/master@{#27509}
2015-03-30 07:34:04 +00:00
Benedikt Meurer
3aa206b865 [turbofan] Turn Math.clz32 into an inlinable builtin.
R=dcarney@chromium.org, yangguo@chromium.org
BUG=v8:3952
LOG=n

Review URL: https://codereview.chromium.org/1021183002

Cr-Commit-Position: refs/heads/master@{#27329}
2015-03-20 08:37:34 +00:00
Benedikt Meurer
d18bfa1130 [x86] Faster/shorter code for stack checks.
Avoid loading the stack pointer and the stack limit into allocatable
registers first, but generate a cmp rsp,[limit] instead.

R=dcarney@chromium.org

Review URL: https://codereview.chromium.org/989203002

Cr-Commit-Position: refs/heads/master@{#27065}
2015-03-09 11:06:45 +00:00
bmeurer
61ac461330 Revert of [x64] Improve instruction selection for TruncateInt64ToInt32. (patchset #1 id:1 of https://codereview.chromium.org/936323004/)
Reason for revert:
Breaks SQLite

Original issue's description:
> [x64] Improve instruction selection for TruncateInt64ToInt32.
>
> R=svenpanne@chromium.org
>
> Committed: https://crrev.com/64a2717529e2197f3a789adabf86ca36f5eb764c
> Cr-Commit-Position: refs/heads/master@{#26739}

TBR=svenpanne@chromium.org
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true

Review URL: https://codereview.chromium.org/928723003

Cr-Commit-Position: refs/heads/master@{#26791}
2015-02-23 07:09:26 +00:00
Benedikt Meurer
64a2717529 [x64] Improve instruction selection for TruncateInt64ToInt32.
R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/936323004

Cr-Commit-Position: refs/heads/master@{#26739}
2015-02-19 09:41:53 +00:00
bmeurer
39515a685a [x64] Recognize zero extension of 8-bit and 16-bit values.
R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/938513003

Cr-Commit-Position: refs/heads/master@{#26712}
2015-02-18 07:06:16 +00:00
danno
85d2db8781 [turbofan] Use "leal" in even more situations
Achieve more than parity with modes currently handled on ia32 in preparation for
porting the entire mechanism to ia32, including supporting mul of constants 3,
5 and 9 with "leal" instructions.

TEST=unittests

Review URL: https://codereview.chromium.org/774193003

Cr-Commit-Position: refs/heads/master@{#25677}
2014-12-05 10:54:40 +00:00
Weiliang Lin
50c4d8826b [x64] introduce vex prefix version of float64 arithmetic binop
BUG=
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/764863002

Patch from Weiliang Lin <weiliang.lin@intel.com>.

Cr-Commit-Position: refs/heads/master@{#25582}
2014-12-01 10:45:18 +00:00
danno
91ec654bf9 [turbofan]: Use "leal" more prevasively on x64
Only use "addl" and "subl" in cases that have been measured to be
faster (currently only immediate operations).

Review URL: https://codereview.chromium.org/735293004

Cr-Commit-Position: refs/heads/master@{#25580}
2014-12-01 10:04:42 +00:00
jarin
d9cabb9b22 [turbofan] Fix matching of the lea instruction.
Resets the scaled exponent to 0 when the scaling match fails.

BUG=

Review URL: https://codereview.chromium.org/756643002

Cr-Commit-Position: refs/heads/master@{#25491}
2014-11-24 17:45:33 +00:00
danno
4f1cc51555 [turbofan]: remove optimization of adds/subs to inc and dec
They generally cause regressions on most modern Intel chips. Replace them with
addl/subl.

Review URL: https://codereview.chromium.org/737153003

Cr-Commit-Position: refs/heads/master@{#25466}
2014-11-21 13:18:46 +00:00
Daniel Clifford
5a494cf00c [turbofan]: More optimizations to add and subtract operations on x64
- Use "leal" for subtraction of integer constant when non-constant input to
  subtract is used more than once.
- Use "incl", "decl", and "addl" when they are smaller/cheaper than their
  leal/addl/subl equivalant.

R=titzer@chromium.org

Review URL: https://codereview.chromium.org/738073002

Cr-Commit-Position: refs/heads/master@{#25439}
2014-11-20 13:48:46 +00:00
danno@chromium.org
9a58807030 [turbofan] Optimize add operations to use 'leal' instruction on x64
Add MemoryOperandMatcher that recognizes node clusters in the form
[%r1 + %r2*SCALE + OFFSET] and explicit support in the x64 Int32Add
selector to use it to translate complex adds to 'leal' instructions.

R=titzer@chromium.org

Review URL: https://codereview.chromium.org/704713003

Cr-Commit-Position: refs/heads/master@{#25223}
git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25223 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-11-07 16:47:45 +00:00
bmeurer@chromium.org
1ef9e22900 [x64] 64-bit shift left by 32 or more covers sign/zero extend.
TEST=unittests
R=jarin@chromium.org

Review URL: https://codereview.chromium.org/704703002

Cr-Commit-Position: refs/heads/master@{#25123}
git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25123 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-11-05 05:58:15 +00:00
bmeurer@chromium.org
498920f91c [turbofan] Also optimize unsigned division by constant.
TEST=cctest,mjsunit,unittests
R=jarin@chromium.org

Review URL: https://codereview.chromium.org/697663003

Cr-Commit-Position: refs/heads/master@{#25061}
git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25061 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-11-03 10:05:46 +00:00
bmeurer@chromium.org
948ce2141e [turbofan] First step towards correctified 64-bit addressing.
Also remove the LEA matching from x64, since it was never really
effective. We'll optimize that once we're correct.

TEST=cctest,unittests
R=dcarney@chromium.org

Review URL: https://codereview.chromium.org/652363006

Cr-Commit-Position: refs/heads/master@{#25024}
git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25024 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-10-31 06:41:41 +00:00
bmeurer@chromium.org
548fb46331 [x86] Fix register constraints for multiply-high.
TEST=mjsunit/compiler,unittests
R=titzer@chromium.org

Review URL: https://codereview.chromium.org/671393002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24862 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-10-24 09:36:40 +00:00
bmeurer@chromium.org
81877a6440 [turbofan] Optimize division/modulus by constant.
TEST=cctest,mjsunit,unittests
R=dcarney@chromium.org, svenpanne@chromium.org

Review URL: https://codereview.chromium.org/654833002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24595 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-10-14 11:57:06 +00:00
dcarney@chromium.org
e7a635c853 [turbofan] fix vreg mapping for instruction selector tests
BUG=
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/636543002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24418 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-10-06 14:30:55 +00:00
dcarney@chromium.org
b3d426889d [turbofan] intel lea add multiply matchers
R=bmeurer@chromium.org

BUG=

Review URL: https://codereview.chromium.org/614013002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24357 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-10-01 10:47:14 +00:00
bmeurer@chromium.org
bfd37ab267 Move unit tests to test/unittests.
As per discussion on the V8 team, this is the place we want them to live,
not following the Chrome Style Guide for this.

BUG=v8:3489
LOG=y
R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/615393002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24350 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-10-01 08:34:25 +00:00