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Author SHA1 Message Date
sigurds@chromium.org
15ce82722d Add vrint{a,n,p,m,z} instructions to arm assembler. These instructions are only available on ARMv8. 
R=rodolph.perfetta@gmail.com, ulan@chromium.org, bmeurer@chromium.org, rodolph.perfetta@arm.com

Review URL: https://codereview.chromium.org/682643002

Cr-Commit-Position: refs/heads/master@{#25013}
git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25013 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-10-30 11:01:12 +00:00
bmeurer@chromium.org
8a00950303 [arm] Drop SMMLS support. 
Apparently

 SMMLS r, b, c, a

computes

 r = ((a << 32) - b * c) >> 32

while the documentation is kinda misleading and states that it should
compute

 r = a - ((b * c) >> 32)

The actual behavior is kinda useless, so we drop the instruction again.

TEST=cctest,unittests
TBR=dcarney@chromium.org

Review URL: https://codereview.chromium.org/654653004

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24577 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-10-14 07:47:27 +00:00
bmeurer@chromium.org
8950e0a3de [arm] Add support for SMMLA, SMMLS and SMMUL. 
TEST=cctest,unittests
R=hpayer@chromium.org

Review URL: https://codereview.chromium.org/648283002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24575 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-10-14 05:03:04 +00:00
jochen@chromium.org
56a486c322 Use full include paths everywhere 
- this avoids using relative include paths which are forbidden by the style guide
- makes the code more readable since it's clear which header is meant
- allows for starting to use checkdeps

BUG=none
R=jkummerow@chromium.org, danno@chromium.org
LOG=n

Review URL: https://codereview.chromium.org/304153016

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21625 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-06-03 08:12:43 +00:00
rmcilroy@chromium.org
3eb418df78 Fix fixed-point vcvt_f64_s32 immediate value encoding 
The (32 - fraction_bits) value should be encoded so that the least
significant bit is set to bit 5 and the four next bits to bits 0-3. Fix
the previously incorrect encoding. This bug did not cause behavioral
issues before, since in existing uses of the function the order of the
bits in the immediate value does not matter, as they are all 1.

BUG=3256
LOG=N
R=ulan@chromium.org

Review URL: https://codereview.chromium.org/223623003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20508 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-04-04 11:12:40 +00:00
rodolph.perfetta@arm.com
d5753f27d9 ARM: fix assertions for uxtb and co. 
Allow operands with ROR #0. Behind the scene they are mapped to LSL #0.

BUG=v8:3209
LOG=N
R=ulan@chromium.org

Review URL: https://codereview.chromium.org/198053014

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20171 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-03-21 15:59:45 +00:00
m.m.capewell@googlemail.com
6c4178330d ARM: Fix Q register encoding 
Fix Q register encoding for registers other than Q0. Also, fix value in NeonSize
enumeration.

BUG=
R=ulan@chromium.org

Review URL: https://codereview.chromium.org/207523005

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20163 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-03-21 13:04:20 +00:00
rmcilroy@chromium.org
fadc74ec04 Clean up ARM mov 32bit immediate code in preparation for out of line constant pool. 
R=rodolph.perfetta@arm.com, ulan@chromium.org

Review URL: https://codereview.chromium.org/138503002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@19823 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-03-11 20:17:02 +00:00
dcarney@chromium.org
baf6add9f0 bulk replace Isolate::Current in tests 
R=svenpanne@chromium.org
BUG=

Review URL: https://codereview.chromium.org/23534067

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16817 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-09-19 09:17:13 +00:00
m.m.capewell@googlemail.com
cc9398cd42 ARM: Make double registers low/high safe 
This patch prevents taking the low/high part of a double-precision VFP register that has no corresponding single-precision VFP registers.

BUG=none
TEST=Added to test-disasm-arm.cc, test-assembler-arm.cc

Review URL: https://codereview.chromium.org/19560003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15885 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-07-25 15:04:38 +00:00
rodolph.perfetta@gmail.com
762157d697 ARM: Implement memcpy using NEON. 
Add support for a few NEON and ARM SIMD instructions and use them for various
memcpy operations.

BUG=none
TEST=none

Review URL: https://chromiumcodereview.appspot.com/17858002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@15602 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-07-10 15:32:39 +00:00
dcarney@chromium.org
ff2a76b5d5 remove most V8_ALLOW_ACCESS_TO_* defines from test classes 
R=svenpanne@chromium.org
BUG=

Review URL: https://codereview.chromium.org/15964004

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14849 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-05-28 11:54:52 +00:00
rodolph.perfetta@gmail.com
45ec481659 ARM: Smi refactoring and improvements. 
Refactoring:
 * consistent use of SmiTag/Untag
 * added a few Smi macros and helpers
Improvements
 * small optimisations (e.g. merging untag and cmp #0)
 * added fixed point to double conversion instructions for simpler conversions

More on the last point: a Smi can be seen as a fixed point number with the
a one bit fractional part. Fixed to double instructions allow us to convert
a Smi to a double without untagging.

BUG=none
TEST=none

Review URL: https://chromiumcodereview.appspot.com/15085026

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14724 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-05-17 15:38:14 +00:00
dcarney@chromium.org
cf5ff5a14c first step to remove unsafe handles 
R=svenpanne@chromium.org
BUG=

Review URL: https://codereview.chromium.org/12729023

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14530 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-05-02 20:18:42 +00:00
mstarzinger@chromium.org
dd70ce29d1 Unify the way cctest initalizes the VM for each test case. 
R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/13483017

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14199 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-04-10 08:29:39 +00:00
svenpanne@chromium.org
53310ac152 Added a version of the v8::HandleScope constructor with an Isolate and use that consistently. 
I tried to limit the use of v8::Isolate::GetCurrent() and v8::internal::Isolate::Current() as much as possible, but sometimes this would have involved restructuring tests quite a bit, which is better left for a separate CL.

BUG=v8:2487

Review URL: https://codereview.chromium.org/12716010

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13953 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-03-15 12:06:53 +00:00
svenpanne@chromium.org
e4edbb0535 Cleaned up CpuFeature scope handling. 
First of all, it has nothing to do with Isolates, it is related to the assembler
at hand. Furthermore, the saving/restoring is platform-independent. Cleaned up
some platform-specific stuff on the way.

Note that there are some things which still need some cleanup, like e.g. using
EnumSet instead of uint64_t, making Probe() more uniform across platforms etc.,
but the CL is already big enough.

BUG=v8:2487

Review URL: https://codereview.chromium.org/12391055

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13823 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-03-05 10:48:16 +00:00
ulan@chromium.org
d18e118f17 ARM: Fix disassembly of some VFP instructions with condition codes 
Previously, we would disassemble some VFP instructions like this:

  vmla.f64eq d16, d17, d18

This patch moves the condition to the right place:

  vmlaeq.f64 d16, d17, d18

Spotted by Rodolph Perfetta!

BUG=none

Review URL: https://chromiumcodereview.appspot.com/12335129
Patch from Hans Wennborg <hans@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13752 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-02-27 11:52:45 +00:00
ulan@chromium.org
87265114c4 Emit VMLS for multiply-subtract on ARM. 
BUG=none

Review URL: https://chromiumcodereview.appspot.com/12319113
Patch from Hans Wennborg <hans@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13748 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-02-27 10:24:40 +00:00
ulan@chromium.org
250ebdc2be ARM: Change signature for vmov.32 function in the assembler 
The assembler has 8 different vmov variants. The one for vmov.32 and for moving
an immediate into a double reg only differs in the type of the second
paremeter: vmov.32 takes an int, the other takes a double.

The situation is dangerous because C++ will happily implicitly convert between
int and double.

This patch changes the signature of the vmov.32 assembler function so that it
cannot be confused with the other vmovs.

BUG=none

Review URL: https://chromiumcodereview.appspot.com/12255031
Patch from Hans Wennborg <hans@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13668 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-02-14 12:28:02 +00:00
ulan@chromium.org
bed569b548 ARM: Make use of d16-d31 when available. 
Review URL: https://chromiumcodereview.appspot.com/11428137
Patch from Hans Wennborg <hans@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13484 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2013-01-23 16:29:48 +00:00
ulan@chromium.org
74492ab2d4 Emit VMLA for multiply-add on ARM 
Review URL: https://chromiumcodereview.appspot.com/11293061
Patch from Hans Wennborg <hans@chromium.org>.

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@12958 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2012-11-14 11:01:18 +00:00
svenpanne@chromium.org
1ea5db0ed3 Martyn Capewell <m.m.capewell@googlemail.com> 
Review URL: https://chromiumcodereview.appspot.com/10451037

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@11784 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2012-06-12 17:26:28 +00:00
erik.corry@gmail.com
b3e0761e38 Cosmetic changes ("set up" is a verb, "setup" is a noun). 
Review URL: http://codereview.chromium.org/9139051

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10399 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2012-01-13 13:09:52 +00:00
karlklose@chromium.org
b606195012 ARM: Fix disasm for strh, vabs, vneg. Add load/store tests. 
Patch from ARM Ltd.

BUG=none
TEST=added to test/cctest/test-disasm-arm.cc

Original review at http://codereview.chromium.org/7013024/.

Review URL: http://codereview.chromium.org/7013027

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7875 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-05-12 14:44:49 +00:00
sgjesse@chromium.org
6255476028 ARM: Add support load/store multiple VFP registers 
Enter/exit frames with save doubles use these instructions instead of generating 16 load/store instructions.

R=karlklose@chromium.org, rodolph.perfetta@gmail.com

BUG=
TEST=

Review URL: http://codereview.chromium.org//6691057

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7509 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-04-06 09:06:23 +00:00
vitalyr@chromium.org
179aef2b8f VM initialization refactoring. 
This patch introduces global once per-process initialization and moves
the OS and CPU setup there. This makes CPU features isolate-independent.

Review URL: http://codereview.chromium.org/6670119

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7462 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-31 16:17:37 +00:00
vitalyr@chromium.org
7976ca2cbc Merge isolates to bleeding_edge. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7271 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-18 20:35:07 +00:00
vitalyr@chromium.org
76e226f832 Revert r7268: it borked the history. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7269 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-18 19:41:05 +00:00
vitalyr@chromium.org
6ff7fdebd3 Merge isolates to bleeding_edge. 
Review URL: http://codereview.chromium.org/6685088

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7268 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-18 18:49:56 +00:00
karlklose@chromium.org
984135cb32 ARM: Improved double to integer truncation. 
Patch from ARM Ltd.

BUG=none
TEST=Added to cctest/test-assembler-arm.cc and cctest/test-disasm-arm.cc

Review URL: http://codereview.chromium.org/6625084

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@7174 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-03-15 11:19:13 +00:00
ager@chromium.org
8198db7934 ARM: Add support for DoMathAbs with double inputs. 
Adds vabs instruction to simulator, assembler, disassembler and tests.

BUG=none
TEST=Added to cctest.

Review URL: http://codereview.chromium.org/6366016

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6531 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-31 10:16:28 +00:00
erik.corry@gmail.com
ca7a438713 Improve support for vmrs/vmsr in ARM disassembler. This is a commit of http://codereview.chromium.org/4904001 for Martyn Capewell. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5824 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-11-15 10:21:57 +00:00
erik.corry@gmail.com
66d13be5f9 Fix incorrect encoding of single and double precision registers for some VFP instructions. Also fix incorrect disassembling of vldr/vstr. This is a commit of http://codereview.chromium.org/3107027 for Rodolph Perfetta. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5352 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-08-26 08:53:00 +00:00
ager@chromium.org
74f9789f61 Landing for Rodolph Perfetta. 
Add support for saturation instruction (ARMv6 or above).
The byte array clamping code has been updated accordingly.

Review URL: http://codereview.chromium.org/3036008/show

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5106 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-07-21 07:42:51 +00:00
erik.corry@gmail.com
8c767e02f9 ARM: Add support for the VFP mov literal instruction and mov 
between single VFP registers.  Math.pow implementation has
been updated with the new instructions.  This is a commit
of http://codereview.chromium.org/2813046/show for Rodolph
Perfetta.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5037 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-07-08 12:38:02 +00:00
sgjesse@chromium.org
ff6c4fe680 ARM: Special code for raising to the power of an integer 
When calculating Math.pow where the exponent is a smi use a simple loop to calculate the result.

Added support for the vmov instruction moving from one doubleword extension register to another.

Added some Math.pow tests which partially covers what is in the Sputnik tests.
Review URL: http://codereview.chromium.org/2804033

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4990 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-30 12:22:15 +00:00
sgjesse@chromium.org
fd5a7b37a2 ARM: Fix disassembly of double registers 
Added a few disassembler tests for vadd, vsub, vmul and vdiv.
Review URL: http://codereview.chromium.org/2823036

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4986 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-30 08:46:19 +00:00
sgjesse@chromium.org
65018d9123 ARM: Use the vsqrt instruction when available 
vsqrt is used to calculate Math.sqrt(x), Math.pow(x, 0.5) and Math.pow(x, -0.5). Code size doesn't matter, as %_MathSqrt and %_MathPow are only called in one place each.
Review URL: http://codereview.chromium.org/2885002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4974 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-29 09:40:36 +00:00
erik.corry@gmail.com
53340b2624 Add movw and movt support for ARMv7. This includes some code from 
Zhang Kun.  For now we only emit movw and movt in places where no
relocation is needed.  Small performance boost (around 0.5%).
Also adds support for turning ALU operations (eor etc.) with
large immediates into mvn or movw followed by a register-based
ALU operation.
Review URL: http://codereview.chromium.org/2821014

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4913 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-22 08:38:32 +00:00
erik.corry@gmail.com
142de62819 ARM: Be more smart about switching instructions when immediates 
don't fit in the instruction.  Use ubfx and sbfx more.
Review URL: http://codereview.chromium.org/2826001

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4855 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-14 11:20:36 +00:00
erik.corry@gmail.com
67c0ec6f17 Update and improve support for ARMv7 bitfield instructions. 
This is a commit of http://codereview.chromium.org/2124022
for Rodolph Perfetta.  I changed the test in
test-assembler-arm.cc so it only runs if ARMv7 is supported.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4744 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-05-27 13:46:18 +00:00
sgjesse@chromium.org
de69f5beba Add support for bkpt instruction 
The bkpt instruction is now supported by both the disassembler and the simulator. In the simulator it breaks to the native debugger if any like int3 on Intel.

Moved the handling of the miscellaneous instructions to a separate part.

Review URL: http://codereview.chromium.org/1576026


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4360 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-04-08 13:30:48 +00:00
erik.corry@gmail.com
038f9074bc Reapply ARM root array change to reduce const pool size 
by using r10 to point to a list of common root objects.
This time we also disable a debugger test on ARM that
has never worked, but with this change sometimes
crashes.
Review URL: http://codereview.chromium.org/174317

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2744 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2009-08-24 11:57:57 +00:00
feng@chromium.org
33fb11c12f Revert commit 2701 per Erik Corry's request. 
Original CL:

http://codereview.chromium.org/171041
Review URL: http://codereview.chromium.org/171089

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2702 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2009-08-18 00:12:26 +00:00
whesse@chromium.org
349dc04a5d Use root array to load roots in generated ARM code. 
This cuts down on code size and reloc work.
Review URL: http://codereview.chromium.org/171041

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2701 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2009-08-17 14:31:49 +00:00
kasperl@chromium.org
d8c56a7fc4 Fix ARM build. 
TBR=olehougaard@chromium.org
Review URL: http://codereview.chromium.org/28115

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@1366 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2009-02-25 16:13:57 +00:00
iposva@chromium.org
779af439ec Backport the changes from the readability review. 
Review URL: http://codereview.chromium.org/8939

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@700 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2008-11-05 19:18:10 +00:00
christian.plesner.hansen@gmail.com
66b18b9975 Fixed arm disassembler build problems. 
Fixed lint issue in platform-macos.

Review URL: http://codereview.chromium.org/1941

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@287 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2008-09-11 16:41:19 +00:00
christian.plesner.hansen@gmail.com
9bed566bdb Changed copyright header from google inc. to v8 project authors. 
Added presubmit step to check copyright.



git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@242 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2008-09-09 20:08:45 +00:00