Commit Graph

12 Commits

Author SHA1 Message Date
Yuxiang Cao
a29eca72d8 [riscv64] Add RVV Float-Point Widening Instructions
Implement vector widening floating-point instructions:
add/subtract/multiply/multiply-add/reduction instructions,
eg. `vfwadd.vf`, `vfwmacc.vf`, `vfwredosum.vs`.
Add tests and simulator support for all newly added instructions.

Bug: v8:11976
Change-Id: I0909eeab24ba075c5a21743bb49538f154ce8aa2
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3442257
Reviewed-by: ji qiu <qiuji@iscas.ac.cn>
Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#79205}
2022-02-22 10:59:25 +00:00
Yujie Wang
8861ca7b74 [riscv64] Add RISCV64 support for wasm-relaxed-simd
- Implement `kRiscvF32x4RecipApprox`, `kRiscvF32x4RecipSqrtApprox`,
  `kRiscvF32x4Qfma`, `kRiscvF32x4Qfms`, `kRiscvF64x2Qfma` and `kRiscvF64x2Qfms`
  in `code-generator-riscv64.cc`

- Reuse lane-select, min-max and trunc instrctions in
  `instruction-selector-riscv64.cc`

Bug: v8:11976
Change-Id: I8566f7e082a3d7071ec9fc64c742da82425a4d4d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3364077
Reviewed-by: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Reviewed-by: Tobias Tebbi <tebbi@chromium.org>
Cr-Commit-Position: refs/heads/main@{#78524}
2022-01-10 01:40:22 +00:00
Yujie Wang
4b7921ac99 [riscv64] Add I8x16_Popcnt for WASM SIMD
- Add I8x16_Popcnt for WASM SIMD

- Add vcpop_m and vfirst_m for riscv64 simulator

Bug: v8:11976
Change-Id: I2b945bb947da0998663cac86f867f09d386b81a4
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3356201
Reviewed-by: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#78444}
2021-12-27 08:15:49 +00:00
Lu Yahan
2384c94140 [riscv64] Check ervey lane in rvv
Change-Id: Ice5b9a09d4c4c1a8013cf5c0993c4ec6111f6c51
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3353070
Reviewed-by: ji qiu <qiuji@iscas.ac.cn>
Commit-Queue: ji qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#78435}
2021-12-23 09:07:25 +00:00
Yujie Wang
fa76b5c99d [riscv64] Add packing and unpacking instructions for WebAssembly SIMD
- Add Wasm SIMD packing instruction:
  `LiftoffAssembler::emit_i8x16_{s,u}convert_i16x8`

- Add Wasm SIMD unpacking instructions:
  `LiftoffAssembler::emit_i64x2_{s,u}convert_i32x4_{low,high}`
  `LiftoffAssembler::emit_i32x4_{s,u}convert_i16x8_{low,high}`
  `LiftoffAssembler::emit_i64x2_{s,u}convert_i32x4_{low,high}`

- Add RVV instrucions: `vzext_vf{2,4,8}` and `vsext_vf{2,4,8}`

- Fixed simulator for `vslidedown_vi`

Bug: v8:11976
Change-Id: Idd383bc566589ce183f4fcef2201d2ccfe03519f
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3273812
Reviewed-by: ji qiu <qiuji@iscas.ac.cn>
Reviewed-by: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: ji qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#77865}
2021-11-12 08:00:05 +00:00
Yujie Wang
4240985a1e [riscv64] Add tests for RVV VI VF instructions
Implement `LiftoffAssembler::emit_i16x8_sconvert_i32x4` for riscv.
Add tests for rvv integer and floating-point instructions.
Add simulator support for rvv instructions, e.g. `vfmadd`, `vnclip`.
Fixed order of operands for `vfdiv.vv`.

Bug: v8:11976
Change-Id: I0691ac66771468533c5994be1fc8a86b09d3c738
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3225319
Reviewed-by: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: Michael Lippautz <mlippautz@chromium.org>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#77595}
2021-10-28 13:57:31 +00:00
Lu Yahan
fcd3ef4821 [riscv64][wasm]Add Vector instrs
- Add vsetivli/I8x16Add/vl/vse8
 - In Rvv, Vector regs is different from Float Regs. But in this cl, in order to facilitate modification, it is assumed that the vector register and float register share a set of register codes.
 - Because v0 is mask reg, we can't allocate it . And transfer float into vector reg, so i delete ft0 from AllocateReg.

Bug: v8:11976
Change-Id: I66185d1f5ead985489bcbdf671b131f02a6bd7c2
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3005768
Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Thibaud Michaud <thibaudm@chromium.org>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Cr-Commit-Position: refs/heads/main@{#76700}
2021-09-07 16:11:22 +00:00
Dan Elphick
7f5383e8ad [base] Move utils/vector.h to base/vector.h
The adding of base:: was mostly prepared using git grep and sed:
git grep -l <pattern> | grep -v base/vector.h | \
  xargs sed -i 's/\b<pattern>\b/base::<pattern>/
with lots of manual clean-ups due to the resulting
v8::internal::base::Vectors.

#includes were fixed using:
git grep -l "src/utils/vector.h" | \
  axargs sed -i 's!src/utils/vector.h!src/base/vector.h!'

Bug: v8:11879
Change-Id: I3e6d622987fee4478089c40539724c19735bd625
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2968412
Reviewed-by: Clemens Backes <clemensb@chromium.org>
Reviewed-by: Hannes Payer <hpayer@chromium.org>
Commit-Queue: Dan Elphick <delphick@chromium.org>
Cr-Commit-Position: refs/heads/master@{#75243}
2021-06-18 13:33:13 +00:00
Zheng Liu
6ac9c652fa [riscv64] Fix decode error of neg instruction.
The disassembler cannot decode neg instruction correctly because a single
quote is missed.

Bug: v8:11833
Change-Id: I43f12e8e8e3f1e51244dc891e9bfb611a95f393b
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2934617
Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Reviewed-by: Brice Dobry <brice.dobry@futurewei.com>
Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
Commit-Queue: Brice Dobry <brice.dobry@futurewei.com>
Cr-Commit-Position: refs/heads/master@{#75046}
2021-06-09 13:34:18 +00:00
Derek Tu
115db49c25 [riscv64] Add RVC Instr CB and fix some RVC Instr CA
Adds the following CB type RISC-V instructions to the assembler:
c.beqz, c.bnez, c.andi, c.srai, c.srli. Also removes sext_xlen
from RVC instructions c.xor, c.or, c.and.

Change-Id: I96ce4693019c28235ccd4f85d0a68ca89a3f4096
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2912922
Reviewed-by: Brice Dobry <brice.dobry@futurewei.com>
Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Commit-Queue: Brice Dobry <brice.dobry@futurewei.com>
Cr-Commit-Position: refs/heads/master@{#74801}
2021-05-27 01:52:40 +00:00
QiuJi
c7d8556355 [riscv64] Add flag to control disassembling of C-ext
Also handling kArchStackPointerGreaterThan in AssembleArchBoolean

Change-Id: I253c1a6cb924364eead3b9fe58c7cf7d6f0696af
Bug: v8:11737
Bug: v8:11747
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2876854
Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Reviewed-by: Brice Dobry <brice.dobry@futurewei.com>
Commit-Queue: Brice Dobry <brice.dobry@futurewei.com>
Cr-Commit-Position: refs/heads/master@{#74543}
2021-05-12 22:04:43 +00:00
Brice Dobry
ffd9e82dd5 Add RISC-V backend
This very large changeset adds support for RISC-V.

Bug: v8:10991
Change-Id: Ic997c94cc12bba6881bc208e66526f423dd0679c
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2571344
Commit-Queue: Brice Dobry <brice.dobry@futurewei.com>
Commit-Queue: Georg Neis <neis@chromium.org>
Reviewed-by: Georg Neis <neis@chromium.org>
Reviewed-by: Hannes Payer <hpayer@chromium.org>
Reviewed-by: Michael Achenbach <machenbach@chromium.org>
Reviewed-by: Michael Stanton <mvstanton@chromium.org>
Cr-Commit-Position: refs/heads/master@{#72598}
2021-02-09 17:06:36 +00:00