Commit Graph

44 Commits

Author SHA1 Message Date
Clemens Hammacher
8161d6b40c [compiler] Remove SpeculationFence
It's not being used, and causes compile errors on windows because of a
name clash (see referenced bugs).

R=mstarzinger@chromium.org
CC=tebbi@chromium.org, jarin@chromium.org

Bug: v8:8953
Change-Id: I22dcdbcbe92f92c390a2f2cdd289dda7f7dc4eb1
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1505794
Reviewed-by: Michael Starzinger <mstarzinger@chromium.org>
Commit-Queue: Clemens Hammacher <clemensh@chromium.org>
Cr-Commit-Position: refs/heads/master@{#60117}
2019-03-08 11:11:21 +00:00
Victor Costan
4d9381baa6 test: Replace _TEST_CASE_ with _TEST_SUITE_.
Googletest is (at last) converging with industry-standard terminology
[1]. We previously called test suites "test cases", which was rather
confusing for folks coming from any other testing framework.

Chrome now has a googletest version that supports _TEST_SUITE_ macros
instead of _TEST_CASE_, so this CL cleans up some of the outdated usage.

[1] https://github.com/google/googletest/blob/master/googletest/docs/primer.md#beware-of-the-nomenclature

Bug: chromium:925652
Change-Id: I3cd02b9fa6dbece1594bbfd50a21ad7503c2aab9
Reviewed-on: https://chromium-review.googlesource.com/c/1475654
Reviewed-by: Jaroslav Sevcik <jarin@chromium.org>
Commit-Queue: Victor Costan <pwnall@chromium.org>
Cr-Commit-Position: refs/heads/master@{#59666}
2019-02-18 21:36:56 +00:00
Ben L. Titzer
0227b62fdb [compiler] Move some files to backend/ directory
This CL splits the backend of TurboFan off into its own directory,
without changing namespaces. This makes ownership management a bit
more fine-grained with a logical separation.

R=mstarzinger@chromium.org,jarin@chromium.org,adamk@chromium.org

Change-Id: I2ac40d6ca2c4f04b8474b630aae0286ecf79ef42
Reviewed-on: https://chromium-review.googlesource.com/c/1308333
Commit-Queue: Ben Titzer <titzer@chromium.org>
Reviewed-by: Adam Klein <adamk@chromium.org>
Reviewed-by: Jaroslav Sevcik <jarin@chromium.org>
Reviewed-by: Michael Starzinger <mstarzinger@chromium.org>
Cr-Commit-Position: refs/heads/master@{#57437}
2018-11-12 15:06:56 +00:00
Benedikt Meurer
1e586c3c70 [turbofan][x64] Match memory operand comparisons with zero.
The InstructionSelector on x64 was missing the ability to properly match
comparisons of memory operands with zero, i.e. it used to turn something
like

  Word32Equal(Load[Uint8](o, i), Int32Constant(0))

into

  movzbl reg, [o,i]
  cmp 0, reg

even requiring a temporary register. Now with this change it generates
the proper

  cmpb [o,i], 0

sequence.

R=sigurds@chromium.org

Bug: v8:8238
Change-Id: I52a71bbf95c85e11cb275f0f4a5726a6873cde95
Reviewed-on: https://chromium-review.googlesource.com/c/1281342
Reviewed-by: Sigurd Schneider <sigurds@chromium.org>
Commit-Queue: Benedikt Meurer <bmeurer@chromium.org>
Cr-Commit-Position: refs/heads/master@{#56677}
2018-10-16 09:29:25 +00:00
jgruber
9ff644ae67 Fix stack check pattern matching for CSA code
The stack check instruction sequence is pattern-matched in
instruction-selector-{ia32,x64}.cc and replaced with its own specialized
opcode, for which we later generate an efficient stack check in a single
instruction.

But this pattern matching has never worked for CSA-generated code. The
matcher expected LoadStackPointer in the right operand and the external
reference load in the left operand. CSA generated exactly vice-versa.

This CL does a few things; it
1. reverts the recent change to load the
limit from smi roots:

Revert "[csa] Load the stack limit from smi roots"
This reverts commit 507c29c940.

2. tweaks the CSA instruction sequence to output what the matcher
expects.
3. refactors stack check matching into a new StackCheckMatcher class.
4. typifies CSA::PerformStackCheck as a drive-by.

Bug: v8:6666,v8:7844
Change-Id: I9bb879ac10bfe7187750c5f9e7834dc4accf28b5
Reviewed-on: https://chromium-review.googlesource.com/1099068
Reviewed-by: Leszek Swirski <leszeks@chromium.org>
Reviewed-by: Sigurd Schneider <sigurds@chromium.org>
Reviewed-by: Jaroslav Sevcik <jarin@chromium.org>
Commit-Queue: Jakob Gruber <jgruber@chromium.org>
Cr-Commit-Position: refs/heads/master@{#53737}
2018-06-14 15:21:53 +00:00
Jaroslav Sevcik
ff394b4453 [turbofan] Remove unused instruction continuation handling for stack checks.
Bug: v8:5267
Change-Id: I649554733fdbd00c8e82b09aca35b0ff1f823560
Reviewed-on: https://chromium-review.googlesource.com/890262
Reviewed-by: Benedikt Meurer <bmeurer@chromium.org>
Commit-Queue: Jaroslav Sevcik <jarin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#50919}
2018-01-29 09:07:07 +00:00
Tobias Tebbi
7a3dec45df [x64 ia32] add SpeculationFence instruction, lowered to lfence
Bug: 
Change-Id: Icf0c43ef5bd3b3d3055d9606f22d3126b31016e3
Reviewed-on: https://chromium-review.googlesource.com/866930
Commit-Queue: Tobias Tebbi <tebbi@chromium.org>
Reviewed-by: Michael Starzinger <mstarzinger@chromium.org>
Reviewed-by: Jaroslav Sevcik <jarin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#50595}
2018-01-15 23:15:40 +00:00
Mathias Bynens
822be9b238 Normalize casing of hexadecimal digits
This patch normalizes the casing of hexadecimal digits in escape
sequences of the form `\xNN` and integer literals of the form
`0xNNNN`.

Previously, the V8 code base used an inconsistent mixture of uppercase
and lowercase.

Google’s C++ style guide uses uppercase in its examples:
https://google.github.io/styleguide/cppguide.html#Non-ASCII_Characters

Moreover, uppercase letters more clearly stand out from the lowercase
`x` (or `u`) characters at the start, as well as lowercase letters
elsewhere in strings.

BUG=v8:7109
TBR=marja@chromium.org,titzer@chromium.org,mtrofin@chromium.org,mstarzinger@chromium.org,rossberg@chromium.org,yangguo@chromium.org,mlippautz@chromium.org
NOPRESUBMIT=true

Cq-Include-Trybots: master.tryserver.blink:linux_trusty_blink_rel;master.tryserver.chromium.linux:linux_chromium_rel_ng
Change-Id: I790e21c25d96ad5d95c8229724eb45d2aa9e22d6
Reviewed-on: https://chromium-review.googlesource.com/804294
Commit-Queue: Mathias Bynens <mathias@chromium.org>
Reviewed-by: Jakob Kummerow <jkummerow@chromium.org>
Cr-Commit-Position: refs/heads/master@{#49810}
2017-12-02 01:24:40 +00:00
shiyu.zhang
78199ce5e0 [turbofan] Enable complex memory operands for binops on ia32/x64
With this change, on ia32 and x64, a load from memory into a register can be replaced by a memory operand for integer binops if it makes sense.

BUG=

Review-Url: https://codereview.chromium.org/2728533003
Cr-Commit-Position: refs/heads/master@{#43739}
2017-03-13 08:50:54 +00:00
Marja Hölttä
83849da70f [iwyu] Pre-work for removing unallowed include macro-assembler.h -> assembler-inl.h
BUG=v8:5294

Change-Id: If45f25aae8de526027b7851cb4efe0ccf4a7c4b1
Reviewed-on: https://chromium-review.googlesource.com/444226
Commit-Queue: Marja Hölttä <marja@chromium.org>
Reviewed-by: Benedikt Meurer <bmeurer@chromium.org>
Reviewed-by: Andreas Haas <ahaas@chromium.org>
Reviewed-by: Yang Guo <yangguo@chromium.org>
Reviewed-by: Michael Starzinger <mstarzinger@chromium.org>
Cr-Commit-Position: refs/heads/master@{#43388}
2017-02-23 12:10:21 +00:00
zhengxing.li
3145befb3d [turbofan][X64] Movzxbl/Movsxbl/Movzxwl/Movsxwl also zero extend to 64bit.
movzxbl/movsxbl/movzxwl/movsxwl operations implicitly zero-extend to 64-bit on x64, So It's not necessary to generate a "movl" instruction to zero-extend.

  For example, movzxbl/movl instruction sequence occurs frequently in v8 interpreter bytecode handler.
  such as:
  kind = BYTECODE_HANDLER
  name = LdaSmi
  compiler = turbofan
  Instructions (size = 76)
  0x184870a3ce40 0 430fbe442601 movsxbl rax,[r14+r12*1+0x1]
  0x184870a3ce46 6 48c1e020 REX.W shlq rax, 32
  0x184870a3ce4a 10 498d5c2402 REX.W leaq rbx,[r12+0x2]
  0x184870a3ce4f 15 420fb61433 movzxbl rdx,[rbx+r14*1]
  0x184870a3ce54 20 8bd2 movl rdx,rdx          <---------------------- here is a redundant "movl"
  0x184870a3ce56 22 4883fa1e REX.W cmpq rdx,0x1e
  0x184870a3ce5a 26 0f8518000000 jnz 56 (0x184870a3ce78)

  This CL also referenced to CL #36038 (https://codereview.chromium.org/1950013003 ) for adding test cases.

BUG=

Review-Url: https://codereview.chromium.org/2427483002
Cr-Commit-Position: refs/heads/master@{#40375}
2016-10-18 03:40:37 +00:00
epertoso
06cde13e7c [turbofan/x64] Load word64 followed by a shift right 32 -> load (and sign-extend if necessary) high 32bit.
We were missing this optimization in a few cases because TruncateInt64ToInt32 was also interfering.
Also removed the equivalent from simplified-lowering.cc, as the arm64 instruction selector has a similar optimization.

R=jarin@chromium.org

Review-Url: https://codereview.chromium.org/2252333002
Cr-Commit-Position: refs/heads/master@{#38711}
2016-08-18 11:24:56 +00:00
ahaas
f8938e5096 [turbofan] Remove the FloatXXSubPreserveNan operators.
This CL changes the semantics of FloatXXSub to match the semantics of
the semantics of FloatXXSubPreserveNan. Therefore there is no need
anymore for the FloatXXSubPreserveNan operators.

The optimizations in VisitFloatXXSub which are removed in this CL have
already been moved to machine-operator-reducer.cc in
https://codereview.chromium.org/2226663002

R=bmeurer@chromium.org

Review-Url: https://codereview.chromium.org/2220973002
Cr-Commit-Position: refs/heads/master@{#38437}
2016-08-08 12:09:50 +00:00
epertoso
b79d7b0486 [x64] Zero/sign-extend loads to 64-bit registers.
Before this change we would first load an 8/16/32-bit value from memory into a 32-bit register, then zero/sign-extend from that register to a 64-bit one. Now we replace that pattern with a single movsx/movzx.

Ported from http://crrev.com/2183923003

R=bmeurer@chromium.org

Committed: https://crrev.com/4abecb7a27bd5fa073d0ff5fadb0c2bb248ef9f4
Review-Url: https://codereview.chromium.org/2220483003
Cr-Original-Commit-Position: refs/heads/master@{#38388}
Cr-Commit-Position: refs/heads/master@{#38428}
2016-08-08 10:00:45 +00:00
machenbach
0f4468b4a6 Revert of [x64] Zero/sign-extend loads to 64-bit registers. (patchset #1 id:20001 of https://codereview.chromium.org/2220483003/ )
Reason for revert:
Breaks tree:
https://build.chromium.org/p/client.v8/builders/V8%20Linux64%20-%20debug/builds/10969

Original issue's description:
> [x64] Zero/sign-extend loads to 64-bit registers.
>
> Before this change we would first load an 8/16/32-bit value from memory into a 32-bit register, then zero/sign-extend from that register to a 64-bit one. Now we replace that pattern with a single movsx/movzx.
>
> Ported from http://crrev.com/2183923003
>
> R=bmeurer@chromium.org
>
> Committed: https://crrev.com/4abecb7a27bd5fa073d0ff5fadb0c2bb248ef9f4
> Cr-Commit-Position: refs/heads/master@{#38388}

TBR=bmeurer@chromium.org,epertoso@chromium.org
# Skipping CQ checks because original CL landed less than 1 days ago.
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true

Review-Url: https://codereview.chromium.org/2221473002
Cr-Commit-Position: refs/heads/master@{#38389}
2016-08-05 14:30:11 +00:00
epertoso
4abecb7a27 [x64] Zero/sign-extend loads to 64-bit registers.
Before this change we would first load an 8/16/32-bit value from memory into a 32-bit register, then zero/sign-extend from that register to a 64-bit one. Now we replace that pattern with a single movsx/movzx.

Ported from http://crrev.com/2183923003

R=bmeurer@chromium.org

Review-Url: https://codereview.chromium.org/2220483003
Cr-Commit-Position: refs/heads/master@{#38388}
2016-08-05 13:34:24 +00:00
jarin
56673804e0 [turbofan] Store nodes use only MachineRepresentation, not MachineType.
Review URL: https://codereview.chromium.org/1513383003

Cr-Commit-Position: refs/heads/master@{#32803}
2015-12-11 15:34:16 +00:00
jarin
bb2a830deb [turbofan] Make MachineType a pair of enums.
MachineType is now a class with two enum fields:
- MachineRepresentation
- MachineSemantic

Both enums are usable on their own, and this change switches some places from using MachineType to use just MachineRepresentation. Most notably:
- register allocator now uses just the representation.
- Phi and Select nodes only refer to representations.

Review URL: https://codereview.chromium.org/1513543003

Cr-Commit-Position: refs/heads/master@{#32738}
2015-12-10 09:03:53 +00:00
mstarzinger
26fc85aae3 [turbofan] Cleanup RawMachineAssembler::Store interface.
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/1424983003

Cr-Commit-Position: refs/heads/master@{#31646}
2015-10-29 09:22:25 +00:00
rmcilroy
c0c214daa8 [Interpreter] Add support for loading from / storing to outer context variables.
Adds support for loading from and storing to outer context
variables. Also adds support for declaring functions on contexts and
locals. Finally, fixes a couple of issues with StaContextSlot where
we weren't emitting the write barrier and therefore would crash in the
GC.

Also added code so that --print-bytecode will output the
function name before the bytecodes, and replaces MachineType with StoreRepresentation in RawMachineAssembler::Store and updates tests.

BUG=v8:4280
LOG=N

Review URL: https://codereview.chromium.org/1425633002

Cr-Commit-Position: refs/heads/master@{#31584}
2015-10-26 18:11:35 +00:00
Weiliang Lin
38e764f7ac [x86] Introduce vandps/vandpd/vxorps/vxorpd.
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/1072343002

Cr-Commit-Position: refs/heads/master@{#27768}
2015-04-11 00:58:38 +00:00
Benedikt Meurer
9af9f1d026 [turbofan] Add new Float32Abs and Float64Abs operators.
These operators compute the absolute floating point value of some
arbitrary input, and are implemented without any branches (i.e. using
vabs on arm, and andps/andpd on x86).

R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/1066393002

Cr-Commit-Position: refs/heads/master@{#27662}
2015-04-08 11:55:04 +00:00
bmeurer
a1b2c275b7 [x64] Match -0 - x with sign bit flip.
We can use xorps/xorpd on Intel CPUs to flip the sign bit. Ideally we'd
use a RIP-relative 128-bit constant in the code object, as OCaml/GCC
does, however that requires 128-bit alignment for code objects, which is
not yet implemented. So for now we materialize the mask inline.

R=dcarney@chromium.org

Review URL: https://codereview.chromium.org/1046893002

Cr-Commit-Position: refs/heads/master@{#27611}
2015-04-07 07:35:03 +00:00
bmeurer
8dad78cdbd [turbofan] Add backend support for float32 operations.
This adds the basics necessary to support float32 operations in TurboFan.
The actual functionality required to detect safe float32 operations will
be added based on this later. Therefore this does not affect production
code except for some cleanup/refactoring.

In detail, this patchset contains the following features:
- Add support for float32 operations to arm, arm64, ia32 and x64
  backends.
- Add float32 machine operators.
- Add support for float32 constants to simplified lowering.
- Handle float32 representation for phis in simplified lowering.

In addition, contains the following (related) cleanups:
- Fix/unify naming of backend instructions.
- Use AVX comparisons when available.
- Extend ArchOpcodeField to 9 bits (required for arm64).
- Refactor some code duplication in instruction selectors.

BUG=v8:3589
LOG=n
R=dcarney@chromium.org

Review URL: https://codereview.chromium.org/1044793002

Cr-Commit-Position: refs/heads/master@{#27509}
2015-03-30 07:34:04 +00:00
Benedikt Meurer
3aa206b865 [turbofan] Turn Math.clz32 into an inlinable builtin.
R=dcarney@chromium.org, yangguo@chromium.org
BUG=v8:3952
LOG=n

Review URL: https://codereview.chromium.org/1021183002

Cr-Commit-Position: refs/heads/master@{#27329}
2015-03-20 08:37:34 +00:00
Benedikt Meurer
d18bfa1130 [x86] Faster/shorter code for stack checks.
Avoid loading the stack pointer and the stack limit into allocatable
registers first, but generate a cmp rsp,[limit] instead.

R=dcarney@chromium.org

Review URL: https://codereview.chromium.org/989203002

Cr-Commit-Position: refs/heads/master@{#27065}
2015-03-09 11:06:45 +00:00
bmeurer
61ac461330 Revert of [x64] Improve instruction selection for TruncateInt64ToInt32. (patchset #1 id:1 of https://codereview.chromium.org/936323004/)
Reason for revert:
Breaks SQLite

Original issue's description:
> [x64] Improve instruction selection for TruncateInt64ToInt32.
>
> R=svenpanne@chromium.org
>
> Committed: https://crrev.com/64a2717529e2197f3a789adabf86ca36f5eb764c
> Cr-Commit-Position: refs/heads/master@{#26739}

TBR=svenpanne@chromium.org
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true

Review URL: https://codereview.chromium.org/928723003

Cr-Commit-Position: refs/heads/master@{#26791}
2015-02-23 07:09:26 +00:00
Benedikt Meurer
64a2717529 [x64] Improve instruction selection for TruncateInt64ToInt32.
R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/936323004

Cr-Commit-Position: refs/heads/master@{#26739}
2015-02-19 09:41:53 +00:00
bmeurer
39515a685a [x64] Recognize zero extension of 8-bit and 16-bit values.
R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/938513003

Cr-Commit-Position: refs/heads/master@{#26712}
2015-02-18 07:06:16 +00:00
danno
85d2db8781 [turbofan] Use "leal" in even more situations
Achieve more than parity with modes currently handled on ia32 in preparation for
porting the entire mechanism to ia32, including supporting mul of constants 3,
5 and 9 with "leal" instructions.

TEST=unittests

Review URL: https://codereview.chromium.org/774193003

Cr-Commit-Position: refs/heads/master@{#25677}
2014-12-05 10:54:40 +00:00
Weiliang Lin
50c4d8826b [x64] introduce vex prefix version of float64 arithmetic binop
BUG=
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/764863002

Patch from Weiliang Lin <weiliang.lin@intel.com>.

Cr-Commit-Position: refs/heads/master@{#25582}
2014-12-01 10:45:18 +00:00
danno
91ec654bf9 [turbofan]: Use "leal" more prevasively on x64
Only use "addl" and "subl" in cases that have been measured to be
faster (currently only immediate operations).

Review URL: https://codereview.chromium.org/735293004

Cr-Commit-Position: refs/heads/master@{#25580}
2014-12-01 10:04:42 +00:00
jarin
d9cabb9b22 [turbofan] Fix matching of the lea instruction.
Resets the scaled exponent to 0 when the scaling match fails.

BUG=

Review URL: https://codereview.chromium.org/756643002

Cr-Commit-Position: refs/heads/master@{#25491}
2014-11-24 17:45:33 +00:00
danno
4f1cc51555 [turbofan]: remove optimization of adds/subs to inc and dec
They generally cause regressions on most modern Intel chips. Replace them with
addl/subl.

Review URL: https://codereview.chromium.org/737153003

Cr-Commit-Position: refs/heads/master@{#25466}
2014-11-21 13:18:46 +00:00
Daniel Clifford
5a494cf00c [turbofan]: More optimizations to add and subtract operations on x64
- Use "leal" for subtraction of integer constant when non-constant input to
  subtract is used more than once.
- Use "incl", "decl", and "addl" when they are smaller/cheaper than their
  leal/addl/subl equivalant.

R=titzer@chromium.org

Review URL: https://codereview.chromium.org/738073002

Cr-Commit-Position: refs/heads/master@{#25439}
2014-11-20 13:48:46 +00:00
danno@chromium.org
9a58807030 [turbofan] Optimize add operations to use 'leal' instruction on x64
Add MemoryOperandMatcher that recognizes node clusters in the form
[%r1 + %r2*SCALE + OFFSET] and explicit support in the x64 Int32Add
selector to use it to translate complex adds to 'leal' instructions.

R=titzer@chromium.org

Review URL: https://codereview.chromium.org/704713003

Cr-Commit-Position: refs/heads/master@{#25223}
git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25223 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-11-07 16:47:45 +00:00
bmeurer@chromium.org
1ef9e22900 [x64] 64-bit shift left by 32 or more covers sign/zero extend.
TEST=unittests
R=jarin@chromium.org

Review URL: https://codereview.chromium.org/704703002

Cr-Commit-Position: refs/heads/master@{#25123}
git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25123 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-11-05 05:58:15 +00:00
bmeurer@chromium.org
498920f91c [turbofan] Also optimize unsigned division by constant.
TEST=cctest,mjsunit,unittests
R=jarin@chromium.org

Review URL: https://codereview.chromium.org/697663003

Cr-Commit-Position: refs/heads/master@{#25061}
git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25061 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-11-03 10:05:46 +00:00
bmeurer@chromium.org
948ce2141e [turbofan] First step towards correctified 64-bit addressing.
Also remove the LEA matching from x64, since it was never really
effective. We'll optimize that once we're correct.

TEST=cctest,unittests
R=dcarney@chromium.org

Review URL: https://codereview.chromium.org/652363006

Cr-Commit-Position: refs/heads/master@{#25024}
git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25024 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-10-31 06:41:41 +00:00
bmeurer@chromium.org
548fb46331 [x86] Fix register constraints for multiply-high.
TEST=mjsunit/compiler,unittests
R=titzer@chromium.org

Review URL: https://codereview.chromium.org/671393002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24862 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-10-24 09:36:40 +00:00
bmeurer@chromium.org
81877a6440 [turbofan] Optimize division/modulus by constant.
TEST=cctest,mjsunit,unittests
R=dcarney@chromium.org, svenpanne@chromium.org

Review URL: https://codereview.chromium.org/654833002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24595 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-10-14 11:57:06 +00:00
dcarney@chromium.org
e7a635c853 [turbofan] fix vreg mapping for instruction selector tests
BUG=
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/636543002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24418 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-10-06 14:30:55 +00:00
dcarney@chromium.org
b3d426889d [turbofan] intel lea add multiply matchers
R=bmeurer@chromium.org

BUG=

Review URL: https://codereview.chromium.org/614013002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24357 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-10-01 10:47:14 +00:00
bmeurer@chromium.org
bfd37ab267 Move unit tests to test/unittests.
As per discussion on the V8 team, this is the place we want them to live,
not following the Chrome Style Guide for this.

BUG=v8:3489
LOG=y
R=svenpanne@chromium.org

Review URL: https://codereview.chromium.org/615393002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24350 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-10-01 08:34:25 +00:00