AuroraMiddleware/v8
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20 Commits

Author SHA1 Message Date
dusan.m.milosavljevic
7bc8fac472 MIPS: [turbofan] Optimize Float32 to Int32 rep. changes with Float32 round ops. 
TEST=unittests/InstructionSelectorTest.CombineChangeFloat32ToInt32WithRoundFloat32,
     ChangeFloat64ToInt32OfChangeFloat32ToFloat64, TruncateFloat64ToFloat32OfChangeInt32ToFloat64
BUG=

Review URL: https://codereview.chromium.org/1520503002

Cr-Commit-Position: refs/heads/master@{#32969}
 2015-12-18 16:12:51 +00:00
paul.lind
a0c7e25f99 Update MIPS owners. 
Add Ivica B.

NOTRY=true

Review URL: https://codereview.chromium.org/1525413003

Cr-Commit-Position: refs/heads/master@{#32933}
 2015-12-17 09:07:00 +00:00
jarin
56673804e0 [turbofan] Store nodes use only MachineRepresentation, not MachineType. 
Review URL: https://codereview.chromium.org/1513383003

Cr-Commit-Position: refs/heads/master@{#32803}
 2015-12-11 15:34:16 +00:00
jarin
bb2a830deb [turbofan] Make MachineType a pair of enums. 
MachineType is now a class with two enum fields:
- MachineRepresentation
- MachineSemantic

Both enums are usable on their own, and this change switches some places from using MachineType to use just MachineRepresentation. Most notably:
- register allocator now uses just the representation.
- Phi and Select nodes only refer to representations.

Review URL: https://codereview.chromium.org/1513543003

Cr-Commit-Position: refs/heads/master@{#32738}
 2015-12-10 09:03:53 +00:00
dusan.m.milosavljevic
0d4f8a913d MIPS: [turbofan] Combine ChangeFloat64ToInt32 with Float64Round ops. 
TEST=unittests/InstructionSlectorTest.CombineChangeFloat64ToInt32WithRoundFloat64
BUG=

Review URL: https://codereview.chromium.org/1510493002

Cr-Commit-Position: refs/heads/master@{#32668}
 2015-12-07 23:36:30 +00:00
dusan.m.milosavljevic
472e2ba9b9 MIPS:[turbofan] Match shift left and bitwise And with mask when possible. 
TEST=unittests/InstructionSelectorTest.Word(32|64)ShlWithWord(32|64)And
BUG=

Review URL: https://codereview.chromium.org/1496013003

Cr-Commit-Position: refs/heads/master@{#32612}
 2015-12-04 13:13:04 +00:00
dusan.m.milosavljevic
2d0e9abebf MIPS:[turbofan] Use Ins, Dins to clear bits instead of And with inverted immediate. 
TEST=unittests/InstructionSelectorTest.Word(32|64)AndToClearBits
BUG=

Review URL: https://codereview.chromium.org/1485023004

Cr-Commit-Position: refs/heads/master@{#32479}
 2015-12-01 22:16:48 +00:00
dusan.m.milosavljevic
6b11cc830b MIPS:[turbofan] Use Nor instruction for bit negation instead of xori. 
Xori instruction can only have unisgned 16-bit immediates for right input,
as such it is not suitable for bit negation on mips.

TEST=unittests/InstructionSecetorTest.Word(32|64)XorMinusOneWithParameter
BUG=

Review URL: https://codereview.chromium.org/1485833003

Cr-Commit-Position: refs/heads/master@{#32478}
 2015-12-01 21:58:43 +00:00
dusan.m.milosavljevic
40a501a26a MIPS: [turbofan] Add matching rule to use Nor instruction. 
TEST=unittests/InstructionSelectorTest.Word32XorMinusOneWithWord32Or,
     Word64XorMinusOneWithWord64Or
BUG=

Review URL: https://codereview.chromium.org/1459723002

Cr-Commit-Position: refs/heads/master@{#32149}
 2015-11-20 14:00:29 +00:00
dusan.m.milosavljevic
74145470dd MIPS: Enable logical shift right and bitwise And matching to Ext, Dext. 
TEST=unittests/InstructionSelectorTest/Word32ShrWithWord32AndWithImmediate,
     Word32AndWithImmediateWithWord32Shr, Word64AndWithImmediateWithWord64Shr,
     Word64AndWithImmediateWithWord64Shr
BUG=

Review URL: https://codereview.chromium.org/1457523002

Cr-Commit-Position: refs/heads/master@{#32062}
 2015-11-17 23:10:59 +00:00
dusan.m.milosavljevic
8ae7c9abc3 MIPS: [turbofan] Properly implement Float64/32 Min/Max instructions. 
TEST=cctest/test-run-machops/Float(64|32)MaxP, Float(64|32)MinP,
       unittests/InstructionSelectorTest.Float64Min|Max
BUG=v8:4206
LOG=N

Review URL: https://codereview.chromium.org/1419753008

Cr-Commit-Position: refs/heads/master@{#31806}
 2015-11-04 21:03:25 +00:00
mstarzinger
26fc85aae3 [turbofan] Cleanup RawMachineAssembler::Store interface. 
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/1424983003

Cr-Commit-Position: refs/heads/master@{#31646}
 2015-10-29 09:22:25 +00:00
rmcilroy
c0c214daa8 [Interpreter] Add support for loading from / storing to outer context variables. 
Adds support for loading from and storing to outer context
variables. Also adds support for declaring functions on contexts and
locals. Finally, fixes a couple of issues with StaContextSlot where
we weren't emitting the write barrier and therefore would crash in the
GC.

Also added code so that --print-bytecode will output the
function name before the bytecodes, and replaces MachineType with StoreRepresentation in RawMachineAssembler::Store and updates tests.

BUG=v8:4280
LOG=N

Review URL: https://codereview.chromium.org/1425633002

Cr-Commit-Position: refs/heads/master@{#31584}
 2015-10-26 18:11:35 +00:00
jarin
edf6d2adbd [mips] Fix mips unittests (to not use invalid load representation). 
Review URL: https://codereview.chromium.org/1340303002

Cr-Commit-Position: refs/heads/master@{#30753}
 2015-09-15 15:50:44 +00:00
balazs.kilvady
8c3af6ca03 MIPS: [turbofan] Add new Float32Abs and Float64Abs operators. 
Port 9af9f1d026

Original commit message:
These operators compute the absolute floating point value of some
arbitrary input, and are implemented without any branches (i.e. using
vabs on arm, and andps/andpd on x86).

BUG=

Review URL: https://codereview.chromium.org/1073463003

Cr-Commit-Position: refs/heads/master@{#27679}
 2015-04-08 19:30:11 +00:00
balazs.kilvady
86a6b6ff91 MIPS: [turbofan] Turn Math.clz32 into an inlinable builtin. 
Port 3aa206b865

BUG=v8:3952
LOG=n

Review URL: https://codereview.chromium.org/1020223002

Cr-Commit-Position: refs/heads/master@{#27343}
 2015-03-20 14:05:36 +00:00
balazs.kilvady
3da5a729e8 MIPS: [turbofan] Improve code generation for unordered comparisons. 
Port c24220c0c1

TEST=cctest,unittests
BUG=

Review URL: https://codereview.chromium.org/850733004

Cr-Commit-Position: refs/heads/master@{#26045}
 2015-01-13 20:28:13 +00:00
dusan.milosavljevic@imgtec.com
032ae8e876 MIPS: Fix instruction selection test expectations after r25120. 
TEST=unittests/InstructionSelectorCmpTest.Parameter,
     InstructionSelectorTest.Word32EqualWithZero
BUG=
R=paul.lind@imgtec.com

Review URL: https://codereview.chromium.org/706633003

Cr-Commit-Position: refs/heads/master@{#25167}
git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25167 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-11-05 18:51:43 +00:00
bmeurer@chromium.org
b472d9a045 MIPS: Add OWNERS file for compiler unittests. 
BUG=
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/648413003

Patch from Paul Lind <paul.lind@imgtec.com>.

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24574 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-10-14 03:55:43 +00:00
paul.lind@imgtec.com
f9b39f29fb MIPS: Add turbofan support for mips32. 
BUG=
R=bmeurer@chromium.org, dusan.milosavljevic@imgtec.com

Review URL: https://codereview.chromium.org/601723002

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24397 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2014-10-02 15:48:48 +00:00