Commit Graph

21 Commits

Author SHA1 Message Date
bbudge
5c4298a0ae [Turbofan] Allow FP operands and vregs in InstructionSequenceTest.
- Adds an optional representation field to VReg and TestOperand structs.
- Adds a simple FP allocation test to register-allocator-unittest.cc.
- Adds some simple FP tests to move-optimizer-unittest.cc.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2400513002
Cr-Commit-Position: refs/heads/master@{#40117}
2016-10-10 11:07:01 +00:00
bbudge
257336d26a [RegisterConfiguration] Streamline access to arch defaults, simplify Registers.
Replaces ArchDefault method with Crankshaft and Turbofan getters.
Eliminates IsAllocated method on Register, FloatRegister, DoubleRegister.
Eliminates ToString method too.
Changes call sites to access appropriate arch default RegisterConfiguration.

LOG=N
BUG=

Review-Url: https://codereview.chromium.org/2092413002
Cr-Commit-Position: refs/heads/master@{#37297}
2016-06-27 15:31:31 +00:00
mtrofin
1ecf58f409 [turbofan] fine grained in-block move optimization
So far, we've been moving down gaps wholesale. This change moves
individual move operations instead. This improves some benchmarks,
and should overall reduce code size, because it improves the chance of
reducing the number of moves.

For example, there are improvements on x64 in Emscripten (Bullet, in
particular) , JetStream geomean, Embenchen (zlib).

In the process of making this change, I noticed we can separate the
tasks performed by the move optimizer, as follows:

- group gaps into 1
- push gaps down, jumping instructions (these 2 were together before)
- merge blocks (and then push gaps down)
- finalize

We can do without a finalization list. This avoids duplicating storage -
we already have the list of instructions; it also simplifies the logic, since,
with this change, we may process an instruction's gap twice.

Compile time doesn't regress much (see pathological cases), but we
may want to avoid the allocations of the few sets used in the new code.
I'll do that in a subsequent change.

BUG=

Review URL: https://codereview.chromium.org/1634093002

Cr-Commit-Position: refs/heads/master@{#33715}
2016-02-04 06:30:34 +00:00
mtrofin
78b55f2ebc If all the predecessors of a node have, at the last gap, the exact same
moves, we move those to the node, and remove them from the
predecessors ("merge" them to the common node).

If only some of the moves are common, we don't do anything. This is
what this change addresses.

The bug linked below should be addressed by this change. The only
difference in codegen before/after the change that introduced the bug
was un-merged moves.

BUG=chromium:549262
LOG=N

Review URL: https://codereview.chromium.org/1527203002

Cr-Commit-Position: refs/heads/master@{#33481}
2016-01-25 06:33:14 +00:00
jarin
bb2a830deb [turbofan] Make MachineType a pair of enums.
MachineType is now a class with two enum fields:
- MachineRepresentation
- MachineSemantic

Both enums are usable on their own, and this change switches some places from using MachineType to use just MachineRepresentation. Most notably:
- register allocator now uses just the representation.
- Phi and Select nodes only refer to representations.

Review URL: https://codereview.chromium.org/1513543003

Cr-Commit-Position: refs/heads/master@{#32738}
2015-12-10 09:03:53 +00:00
mtrofin
46878c1da1 When we split above an instruction (for example because of splintering),
we may introduce moves that are redundant in the context of
moves on subsequent instructions. Currently, we only detect such
redundancies by allowing moves to skip over Nop instructions (true
nops, with no input/output). We can also skip over other cases, for
example over constant definitions (nop with an output), since whatever
moves happen above it do not influence the instruction's outcome.

We may be able to handle other cases, too - in subsequent CLs.

BUG=

Review URL: https://codereview.chromium.org/1422333003

Cr-Commit-Position: refs/heads/master@{#31662}
2015-10-29 16:12:54 +00:00
akos.palfi
8eabcb3fb6 Fix debug mode test failures on MIPS and PPC after f1aa5562.
TEST=cctest/test-gap-resolver/FuzzResolver,unittests/MoveOptimizerTest.RemovesRedundantExplicit
BUG=

Review URL: https://codereview.chromium.org/1403373016

Cr-Commit-Position: refs/heads/master@{#31629}
2015-10-28 13:04:43 +00:00
danno
f1aa556278 [turbofan] Create ExplicitOperands to specify operands without virtual registers
Up until now, if one wanted to specify an explicit stack location                                                                                                                                                                                                or register as an operand for an instruction, it had to also be
explicitly associated with a virtual register as a so-called
FixedRegister or FixedStackSlot.

For the implementation of tail calls, the plan is to use the gap
resolver needs to shuffle stack locations from the caller to the
tail-called callee. In order to do this, it must be possible to
explicitly address operand locations on the stack that are not
associated with virtual registers.

This CL introduces ExplictOperands, which can specify a specific
register or stack location that is not associated with virtual
register. This will allow tail calls to specify the target
locations for the necessary stack moves in the gap for the tail
call without the core register allocation having to know about
the target of the stack moves at all.

In the process this CL:
* creates a new Operand kind, ExplicitOperand, with which
  instructions can specify register and stack slots without an
  associated virtual register.
* creates a LocationOperand class from which AllocatedOperand and
  ExplicitOperand are derived and provides a common interface to
  get Register, DoubleRegister and spill slot information.
* removes RegisterOperand, DoubleRegisterOperand,
  StackSlotOperand and DoubleStackSlotOperand, they are subsumed
  by LocationOperand.
* addresses a cleanup TODO in AllocatedOperand to reduce the
  redundancy of AllocatedOperand::Kind by using machine_type() to
  determine if an operand corresponds to a general purpose or
  double register.

BUG=v8:4076
LOG=n

Review URL: https://codereview.chromium.org/1389373002

Cr-Commit-Position: refs/heads/master@{#31603}
2015-10-27 13:27:00 +00:00
dcarney
4fe546c785 [test] make instruction sequence test emit cfgs more like the scheduler
BUG=

Review URL: https://codereview.chromium.org/1116923002

Cr-Commit-Position: refs/heads/master@{#28167}
2015-04-30 13:39:16 +00:00
dcarney
81345f1a2c Reland: [turbofan] add MachineType to AllocatedOperand
- allows the optimization of emitted gap move code since the representation of the value in the register is known
- necessary preparation for vector register allocation
- prepare for slot sharing for any value of the same byte width

TBR=jarin@chromium.org
BUG=

Review URL: https://codereview.chromium.org/1111323003

Cr-Commit-Position: refs/heads/master@{#28140}
2015-04-29 19:36:25 +00:00
machenbach
7eccb18148 Revert of [turbofan] add MachineType to AllocatedOperand (patchset #17 id:310001 of https://codereview.chromium.org/1087793002/)
Reason for revert:
[Sheriff] Breaks compile on chromium asan and v8 msan:
http://build.chromium.org/p/client.v8/builders/Linux%20ASAN%20Builder/builds/3446
http://build.chromium.org/p/client.v8/builders/V8%20Linux%20-%20arm64%20-%20sim%20-%20MSAN/builds/2085

Original issue's description:
> [turbofan] add MachineType to AllocatedOperand
>
> - allows the optimization of emitted gap move code since the representation of the value in the register is known
> - necessary preparation for vector register allocation
> - prepare for slot sharing for any value of the same byte width
>
> BUG=
>
> Committed: https://crrev.com/3a025d1ab6437559f86a464767aa03d2d9789f6f
> Cr-Commit-Position: refs/heads/master@{#28137}

TBR=jarin@chromium.org,dcarney@chromium.org
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true
BUG=

Review URL: https://codereview.chromium.org/1119483003

Cr-Commit-Position: refs/heads/master@{#28139}
2015-04-29 18:28:47 +00:00
dcarney
3a025d1ab6 [turbofan] add MachineType to AllocatedOperand
- allows the optimization of emitted gap move code since the representation of the value in the register is known
- necessary preparation for vector register allocation
- prepare for slot sharing for any value of the same byte width

BUG=

Review URL: https://codereview.chromium.org/1087793002

Cr-Commit-Position: refs/heads/master@{#28137}
2015-04-29 14:46:19 +00:00
dcarney
00aec79079 [turbofan] cleanup ParallelMove
- make ParallelMove into a ZoneVector, removing an annoying level of indirection
- make MoveOperands hold InstructionOperands instead of pointers, so there's no more operand aliasing for moves
- opens up possibility of storing MachineType in allocated operands

R=bmeurer@chromium.org
BUG=

Review URL: https://codereview.chromium.org/1081373002

Cr-Commit-Position: refs/heads/master@{#27842}
2015-04-15 12:36:27 +00:00
dcarney
07ff6d9f22 [turbofan] cleanup InstructionOperand a little
- ConstantOperand was using a too-small field too store its virtual register
- drop ConvertTo, replace it with simple copy
- split AllocatedOperand off from Immediate and Constant to make assignment clearer, also paving the way for small Immediates
- put zone first in *Operand::New
- driveby: drop delayed ssa deconstruction experiment

R=titzer@chromium.org
BUG=

Review URL: https://codereview.chromium.org/1050803002

Cr-Commit-Position: refs/heads/master@{#27692}
2015-04-09 09:15:32 +00:00
dcarney
e39750a26e [turbofan] smash GapInstruction into Instruction
R=titzer@chromium.org
BUG=

Review URL: https://codereview.chromium.org/1041163002

Cr-Commit-Position: refs/heads/master@{#27538}
2015-03-31 13:06:43 +00:00
dcarney
95df1bc266 [turbofan] optimize moves into merges
BUG=

Review URL: https://codereview.chromium.org/755323011

Cr-Commit-Position: refs/heads/master@{#26819}
2015-02-24 12:49:33 +00:00
dcarney
996fa7d36e [turbofan] Remove global InstructionOperand caches.
Review URL: https://codereview.chromium.org/904693002

Cr-Commit-Position: refs/heads/master@{#26479}
2015-02-06 09:00:50 +00:00
dcarney
e6552d4917 Reland "[turbofan] simplify gap ordering"
BUG=

Review URL: https://codereview.chromium.org/854703002

Cr-Commit-Position: refs/heads/master@{#26069}
2015-01-15 09:06:05 +00:00
machenbach
1f44e7267e Revert of [turbofan] simplify gap ordering (patchset #2 id:20001 of https://codereview.chromium.org/810013002/)
Reason for revert:
Revert for breaking emscripten bullet with turbofan on android arm64.

Original issue's description:
> [turbofan] simplify gap ordering
>
> BUG=
>
> Committed: https://crrev.com/70b5eb47b39acbf31746f4a116a9b3ce2730218a
> Cr-Commit-Position: refs/heads/master@{#25865}

TBR=bmeurer@chromium.org,dcarney@chromium.org
NOTREECHECKS=true
NOTRY=true
BUG=

Review URL: https://codereview.chromium.org/815743002

Cr-Commit-Position: refs/heads/master@{#25888}
2014-12-18 15:49:58 +00:00
dcarney
70b5eb47b3 [turbofan] simplify gap ordering
BUG=

Review URL: https://codereview.chromium.org/810013002

Cr-Commit-Position: refs/heads/master@{#25865}
2014-12-17 13:37:56 +00:00
dcarney
60af073ad8 [turbofan] add initial move optimizer
R=bmeurer@chromium.org

BUG=

Review URL: https://codereview.chromium.org/750813004

Cr-Commit-Position: refs/heads/master@{#25533}
2014-11-27 09:21:06 +00:00