AuroraMiddleware/v8
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22 Commits

Author SHA1 Message Date
dusan.m.milosavljevic
7bc8fac472 MIPS: [turbofan] Optimize Float32 to Int32 rep. changes with Float32 round ops. 
TEST=unittests/InstructionSelectorTest.CombineChangeFloat32ToInt32WithRoundFloat32,
     ChangeFloat64ToInt32OfChangeFloat32ToFloat64, TruncateFloat64ToFloat32OfChangeInt32ToFloat64
BUG=

Review URL: https://codereview.chromium.org/1520503002

Cr-Commit-Position: refs/heads/master@{#32969}
 2015-12-18 16:12:51 +00:00
paul.lind
a0c7e25f99 Update MIPS owners. 
Add Ivica B.

NOTRY=true

Review URL: https://codereview.chromium.org/1525413003

Cr-Commit-Position: refs/heads/master@{#32933}
 2015-12-17 09:07:00 +00:00
jarin
56673804e0 [turbofan] Store nodes use only MachineRepresentation, not MachineType. 
Review URL: https://codereview.chromium.org/1513383003

Cr-Commit-Position: refs/heads/master@{#32803}
 2015-12-11 15:34:16 +00:00
jarin
bb2a830deb [turbofan] Make MachineType a pair of enums. 
MachineType is now a class with two enum fields:
- MachineRepresentation
- MachineSemantic

Both enums are usable on their own, and this change switches some places from using MachineType to use just MachineRepresentation. Most notably:
- register allocator now uses just the representation.
- Phi and Select nodes only refer to representations.

Review URL: https://codereview.chromium.org/1513543003

Cr-Commit-Position: refs/heads/master@{#32738}
 2015-12-10 09:03:53 +00:00
dusan.m.milosavljevic
0d4f8a913d MIPS: [turbofan] Combine ChangeFloat64ToInt32 with Float64Round ops. 
TEST=unittests/InstructionSlectorTest.CombineChangeFloat64ToInt32WithRoundFloat64
BUG=

Review URL: https://codereview.chromium.org/1510493002

Cr-Commit-Position: refs/heads/master@{#32668}
 2015-12-07 23:36:30 +00:00
dusan.m.milosavljevic
472e2ba9b9 MIPS:[turbofan] Match shift left and bitwise And with mask when possible. 
TEST=unittests/InstructionSelectorTest.Word(32|64)ShlWithWord(32|64)And
BUG=

Review URL: https://codereview.chromium.org/1496013003

Cr-Commit-Position: refs/heads/master@{#32612}
 2015-12-04 13:13:04 +00:00
dusan.m.milosavljevic
2d0e9abebf MIPS:[turbofan] Use Ins, Dins to clear bits instead of And with inverted immediate. 
TEST=unittests/InstructionSelectorTest.Word(32|64)AndToClearBits
BUG=

Review URL: https://codereview.chromium.org/1485023004

Cr-Commit-Position: refs/heads/master@{#32479}
 2015-12-01 22:16:48 +00:00
dusan.m.milosavljevic
6b11cc830b MIPS:[turbofan] Use Nor instruction for bit negation instead of xori. 
Xori instruction can only have unisgned 16-bit immediates for right input,
as such it is not suitable for bit negation on mips.

TEST=unittests/InstructionSecetorTest.Word(32|64)XorMinusOneWithParameter
BUG=

Review URL: https://codereview.chromium.org/1485833003

Cr-Commit-Position: refs/heads/master@{#32478}
 2015-12-01 21:58:43 +00:00
dusan.m.milosavljevic
40a501a26a MIPS: [turbofan] Add matching rule to use Nor instruction. 
TEST=unittests/InstructionSelectorTest.Word32XorMinusOneWithWord32Or,
     Word64XorMinusOneWithWord64Or
BUG=

Review URL: https://codereview.chromium.org/1459723002

Cr-Commit-Position: refs/heads/master@{#32149}
 2015-11-20 14:00:29 +00:00
dusan.m.milosavljevic
74145470dd MIPS: Enable logical shift right and bitwise And matching to Ext, Dext. 
TEST=unittests/InstructionSelectorTest/Word32ShrWithWord32AndWithImmediate,
     Word32AndWithImmediateWithWord32Shr, Word64AndWithImmediateWithWord64Shr,
     Word64AndWithImmediateWithWord64Shr
BUG=

Review URL: https://codereview.chromium.org/1457523002

Cr-Commit-Position: refs/heads/master@{#32062}
 2015-11-17 23:10:59 +00:00
dusan.m.milosavljevic
5d843f26a9 MIPS64: [turbofan] Combine untagging shifts with Mul, Div and Mod. 
TEST=unittests/InstructionSelectorTest.CombineShiftsWithMul,
     InstructionSelectorTest.CombineShiftsWithDivMod
BUG=

Review URL: https://codereview.chromium.org/1444423002

Cr-Commit-Position: refs/heads/master@{#32061}
 2015-11-17 22:52:54 +00:00
ahaas
39ed694bbd Implemented the Word64Clz TurboFan operator for x64, arm64, and mips64. 
R=titzer@chromium.org

Review URL: https://codereview.chromium.org/1413463009

Cr-Commit-Position: refs/heads/master@{#31858}
 2015-11-06 14:51:20 +00:00
dusan.m.milosavljevic
8ae7c9abc3 MIPS: [turbofan] Properly implement Float64/32 Min/Max instructions. 
TEST=cctest/test-run-machops/Float(64|32)MaxP, Float(64|32)MinP,
       unittests/InstructionSelectorTest.Float64Min|Max
BUG=v8:4206
LOG=N

Review URL: https://codereview.chromium.org/1419753008

Cr-Commit-Position: refs/heads/master@{#31806}
 2015-11-04 21:03:25 +00:00
mstarzinger
26fc85aae3 [turbofan] Cleanup RawMachineAssembler::Store interface. 
R=bmeurer@chromium.org

Review URL: https://codereview.chromium.org/1424983003

Cr-Commit-Position: refs/heads/master@{#31646}
 2015-10-29 09:22:25 +00:00
rmcilroy
c0c214daa8 [Interpreter] Add support for loading from / storing to outer context variables. 
Adds support for loading from and storing to outer context
variables. Also adds support for declaring functions on contexts and
locals. Finally, fixes a couple of issues with StaContextSlot where
we weren't emitting the write barrier and therefore would crash in the
GC.

Also added code so that --print-bytecode will output the
function name before the bytecodes, and replaces MachineType with StoreRepresentation in RawMachineAssembler::Store and updates tests.

BUG=v8:4280
LOG=N

Review URL: https://codereview.chromium.org/1425633002

Cr-Commit-Position: refs/heads/master@{#31584}
 2015-10-26 18:11:35 +00:00
paul.lind
b4f9a95e6c MIPS64: Fix unittests (to not use invalid load representation). 
Same as https://codereview.chromium.org/1340303002/

BUG=

Review URL: https://codereview.chromium.org/1339763005

Cr-Commit-Position: refs/heads/master@{#30756}
 2015-09-15 21:28:30 +00:00
dusan.m.milosavljevic
4329a7c2cf MIPS64: [turbofan] Improve changes from and to Smi. 
The instruction selection for following sequences is
improved:

  113: Word64Sar(107, 91) : Internal/Any
  114: TruncateInt64ToInt32(113) : Signed32/UntaggedSigned32
  115: ChangeInt32ToFloat64(114) : Signed32/UntaggedFloat64

TEST=unittests/InstructionSelectorTest.ChangesFromToSmi
BUG=

Review URL: https://codereview.chromium.org/1318153006

Cr-Commit-Position: refs/heads/master@{#30645}
 2015-09-08 21:55:00 +00:00
balazs.kilvady
8c3af6ca03 MIPS: [turbofan] Add new Float32Abs and Float64Abs operators. 
Port 9af9f1d026

Original commit message:
These operators compute the absolute floating point value of some
arbitrary input, and are implemented without any branches (i.e. using
vabs on arm, and andps/andpd on x86).

BUG=

Review URL: https://codereview.chromium.org/1073463003

Cr-Commit-Position: refs/heads/master@{#27679}
 2015-04-08 19:30:11 +00:00
balazs.kilvady
86a6b6ff91 MIPS: [turbofan] Turn Math.clz32 into an inlinable builtin. 
Port 3aa206b865

BUG=v8:3952
LOG=n

Review URL: https://codereview.chromium.org/1020223002

Cr-Commit-Position: refs/heads/master@{#27343}
 2015-03-20 14:05:36 +00:00
dusan.milosavljevic
17ada20c17 MIPS64: Unify and improve Word32 compares to use same instructions as Word64 compares. 
The CL enables the same instructions are selected for Word32 and Word64 compare
operations which is possible due to a fact 32-bit inputs and produced values
are always sign-extended.

TEST=
BUG=

Review URL: https://codereview.chromium.org/1005123002

Cr-Commit-Position: refs/heads/master@{#27212}
 2015-03-16 11:00:12 +00:00
balazs.kilvady
3da5a729e8 MIPS: [turbofan] Improve code generation for unordered comparisons. 
Port c24220c0c1

TEST=cctest,unittests
BUG=

Review URL: https://codereview.chromium.org/850733004

Cr-Commit-Position: refs/heads/master@{#26045}
 2015-01-13 20:28:13 +00:00
Dusan Milosavljevic
ae9130ebbb MIPS64: Add turbofan support for mips64. 
TEST=
BUG=
R=danno@chromium.org, paul.lind@imgtec.com

Review URL: https://codereview.chromium.org/732403002

Cr-Commit-Position: refs/heads/master@{#25424}
 2014-11-19 15:44:46 +00:00