0e183035a2
First stab at a general ARM cleanup patch. It merges ARM constants so that they can be used across simulator, assembler and disassembler, and tidies up some syntax and ambiguities. BUG=none TEST=none Review URL: http://codereview.chromium.org/6274009 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6483 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
153 lines
4.8 KiB
C++
153 lines
4.8 KiB
C++
// Copyright 2009 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include "v8.h"
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#if defined(V8_TARGET_ARCH_ARM)
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#include "constants-arm.h"
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namespace v8 {
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namespace internal {
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double Instruction::DoubleImmedVmov() const {
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// Reconstruct a double from the immediate encoded in the vmov instruction.
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//
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// instruction: [xxxxxxxx,xxxxabcd,xxxxxxxx,xxxxefgh]
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// double: [aBbbbbbb,bbcdefgh,00000000,00000000,
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// 00000000,00000000,00000000,00000000]
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//
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// where B = ~b. Only the high 16 bits are affected.
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uint64_t high16;
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high16 = (Bits(17, 16) << 4) | Bits(3, 0); // xxxxxxxx,xxcdefgh.
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high16 |= (0xff * Bit(18)) << 6; // xxbbbbbb,bbxxxxxx.
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high16 |= (Bit(18) ^ 1) << 14; // xBxxxxxx,xxxxxxxx.
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high16 |= Bit(19) << 15; // axxxxxxx,xxxxxxxx.
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uint64_t imm = high16 << 48;
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double d;
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memcpy(&d, &imm, 8);
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return d;
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}
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// These register names are defined in a way to match the native disassembler
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// formatting. See for example the command "objdump -d <binary file>".
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const char* Registers::names_[kNumRegisters] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "fp", "ip", "sp", "lr", "pc",
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};
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// List of alias names which can be used when referring to ARM registers.
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const Registers::RegisterAlias Registers::aliases_[] = {
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{10, "sl"},
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{11, "r11"},
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{12, "r12"},
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{13, "r13"},
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{14, "r14"},
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{15, "r15"},
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{kNoRegister, NULL}
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};
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const char* Registers::Name(int reg) {
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const char* result;
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if ((0 <= reg) && (reg < kNumRegisters)) {
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result = names_[reg];
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} else {
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result = "noreg";
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}
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return result;
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}
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// Support for VFP registers s0 to s31 (d0 to d15).
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// Note that "sN:sM" is the same as "dN/2"
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// These register names are defined in a way to match the native disassembler
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// formatting. See for example the command "objdump -d <binary file>".
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const char* VFPRegisters::names_[kNumVFPRegisters] = {
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"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
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"s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
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"s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
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"s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
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"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
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"d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15"
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};
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const char* VFPRegisters::Name(int reg, bool is_double) {
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ASSERT((0 <= reg) && (reg < kNumVFPRegisters));
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return names_[reg + (is_double ? kNumVFPSingleRegisters : 0)];
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}
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int VFPRegisters::Number(const char* name, bool* is_double) {
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for (int i = 0; i < kNumVFPRegisters; i++) {
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if (strcmp(names_[i], name) == 0) {
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if (i < kNumVFPSingleRegisters) {
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*is_double = false;
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return i;
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} else {
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*is_double = true;
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return i - kNumVFPSingleRegisters;
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}
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}
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}
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// No register with the requested name found.
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return kNoRegister;
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}
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int Registers::Number(const char* name) {
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// Look through the canonical names.
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for (int i = 0; i < kNumRegisters; i++) {
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if (strcmp(names_[i], name) == 0) {
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return i;
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}
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}
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// Look through the alias names.
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int i = 0;
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while (aliases_[i].reg != kNoRegister) {
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if (strcmp(aliases_[i].name, name) == 0) {
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return aliases_[i].reg;
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}
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i++;
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}
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// No register with the requested name found.
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return kNoRegister;
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}
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} } // namespace v8::internal
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#endif // V8_TARGET_ARCH_ARM
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