74145470dd
TEST=unittests/InstructionSelectorTest/Word32ShrWithWord32AndWithImmediate,
Word32AndWithImmediateWithWord32Shr, Word64AndWithImmediateWithWord64Shr,
Word64AndWithImmediateWithWord64Shr
BUG=
Review URL: https://codereview.chromium.org/1457523002
Cr-Commit-Position: refs/heads/master@{#32062}
1157 lines
42 KiB
C++
1157 lines
42 KiB
C++
// Copyright 2014 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file
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#include "test/unittests/compiler/instruction-selector-unittest.h"
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namespace v8 {
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namespace internal {
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namespace compiler {
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namespace {
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template <typename T>
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struct MachInst {
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T constructor;
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const char* constructor_name;
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ArchOpcode arch_opcode;
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MachineType machine_type;
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};
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template <typename T>
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std::ostream& operator<<(std::ostream& os, const MachInst<T>& mi) {
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return os << mi.constructor_name;
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}
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typedef MachInst<Node* (RawMachineAssembler::*)(Node*)> MachInst1;
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typedef MachInst<Node* (RawMachineAssembler::*)(Node*, Node*)> MachInst2;
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// To avoid duplicated code IntCmp helper structure
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// is created. It contains MachInst2 with two nodes and expected_size
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// because different cmp instructions have different size.
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struct IntCmp {
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MachInst2 mi;
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uint32_t expected_size;
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};
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struct FPCmp {
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MachInst2 mi;
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FlagsCondition cond;
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};
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const FPCmp kFPCmpInstructions[] = {
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{{&RawMachineAssembler::Float64Equal, "Float64Equal", kMips64CmpD,
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kMachFloat64},
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kEqual},
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{{&RawMachineAssembler::Float64LessThan, "Float64LessThan", kMips64CmpD,
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kMachFloat64},
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kUnsignedLessThan},
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{{&RawMachineAssembler::Float64LessThanOrEqual, "Float64LessThanOrEqual",
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kMips64CmpD, kMachFloat64},
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kUnsignedLessThanOrEqual},
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{{&RawMachineAssembler::Float64GreaterThan, "Float64GreaterThan",
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kMips64CmpD, kMachFloat64},
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kUnsignedLessThan},
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{{&RawMachineAssembler::Float64GreaterThanOrEqual,
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"Float64GreaterThanOrEqual", kMips64CmpD, kMachFloat64},
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kUnsignedLessThanOrEqual}};
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struct Conversion {
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// The machine_type field in MachInst1 represents the destination type.
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MachInst1 mi;
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MachineType src_machine_type;
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};
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// ----------------------------------------------------------------------------
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// Logical instructions.
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// ----------------------------------------------------------------------------
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const MachInst2 kLogicalInstructions[] = {
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{&RawMachineAssembler::Word32And, "Word32And", kMips64And, kMachInt32},
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{&RawMachineAssembler::Word64And, "Word64And", kMips64And, kMachInt64},
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{&RawMachineAssembler::Word32Or, "Word32Or", kMips64Or, kMachInt32},
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{&RawMachineAssembler::Word64Or, "Word64Or", kMips64Or, kMachInt64},
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{&RawMachineAssembler::Word32Xor, "Word32Xor", kMips64Xor, kMachInt32},
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{&RawMachineAssembler::Word64Xor, "Word64Xor", kMips64Xor, kMachInt64}};
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// ----------------------------------------------------------------------------
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// Shift instructions.
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// ----------------------------------------------------------------------------
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const MachInst2 kShiftInstructions[] = {
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{&RawMachineAssembler::Word32Shl, "Word32Shl", kMips64Shl, kMachInt32},
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{&RawMachineAssembler::Word64Shl, "Word64Shl", kMips64Dshl, kMachInt64},
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{&RawMachineAssembler::Word32Shr, "Word32Shr", kMips64Shr, kMachInt32},
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{&RawMachineAssembler::Word64Shr, "Word64Shr", kMips64Dshr, kMachInt64},
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{&RawMachineAssembler::Word32Sar, "Word32Sar", kMips64Sar, kMachInt32},
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{&RawMachineAssembler::Word64Sar, "Word64Sar", kMips64Dsar, kMachInt64},
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{&RawMachineAssembler::Word32Ror, "Word32Ror", kMips64Ror, kMachInt32},
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{&RawMachineAssembler::Word64Ror, "Word64Ror", kMips64Dror, kMachInt64}};
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// ----------------------------------------------------------------------------
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// MUL/DIV instructions.
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// ----------------------------------------------------------------------------
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const MachInst2 kMulDivInstructions[] = {
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{&RawMachineAssembler::Int32Mul, "Int32Mul", kMips64Mul, kMachInt32},
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{&RawMachineAssembler::Int32Div, "Int32Div", kMips64Div, kMachInt32},
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{&RawMachineAssembler::Uint32Div, "Uint32Div", kMips64DivU, kMachUint32},
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{&RawMachineAssembler::Int64Mul, "Int64Mul", kMips64Dmul, kMachInt64},
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{&RawMachineAssembler::Int64Div, "Int64Div", kMips64Ddiv, kMachInt64},
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{&RawMachineAssembler::Uint64Div, "Uint64Div", kMips64DdivU, kMachUint64},
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{&RawMachineAssembler::Float64Mul, "Float64Mul", kMips64MulD, kMachFloat64},
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{&RawMachineAssembler::Float64Div, "Float64Div", kMips64DivD,
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kMachFloat64}};
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// ----------------------------------------------------------------------------
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// MOD instructions.
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// ----------------------------------------------------------------------------
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const MachInst2 kModInstructions[] = {
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{&RawMachineAssembler::Int32Mod, "Int32Mod", kMips64Mod, kMachInt32},
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{&RawMachineAssembler::Uint32Mod, "Uint32Mod", kMips64ModU, kMachInt32},
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{&RawMachineAssembler::Float64Mod, "Float64Mod", kMips64ModD,
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kMachFloat64}};
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// ----------------------------------------------------------------------------
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// Arithmetic FPU instructions.
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// ----------------------------------------------------------------------------
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const MachInst2 kFPArithInstructions[] = {
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{&RawMachineAssembler::Float64Add, "Float64Add", kMips64AddD, kMachFloat64},
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{&RawMachineAssembler::Float64Sub, "Float64Sub", kMips64SubD,
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kMachFloat64}};
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// ----------------------------------------------------------------------------
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// IntArithTest instructions, two nodes.
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// ----------------------------------------------------------------------------
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const MachInst2 kAddSubInstructions[] = {
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{&RawMachineAssembler::Int32Add, "Int32Add", kMips64Add, kMachInt32},
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{&RawMachineAssembler::Int64Add, "Int64Add", kMips64Dadd, kMachInt64},
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{&RawMachineAssembler::Int32Sub, "Int32Sub", kMips64Sub, kMachInt32},
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{&RawMachineAssembler::Int64Sub, "Int64Sub", kMips64Dsub, kMachInt64}};
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// ----------------------------------------------------------------------------
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// IntArithTest instructions, one node.
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// ----------------------------------------------------------------------------
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const MachInst1 kAddSubOneInstructions[] = {
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{&RawMachineAssembler::Int32Neg, "Int32Neg", kMips64Sub, kMachInt32},
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{&RawMachineAssembler::Int64Neg, "Int64Neg", kMips64Dsub, kMachInt64}};
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// ----------------------------------------------------------------------------
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// Arithmetic compare instructions.
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// ----------------------------------------------------------------------------
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const IntCmp kCmpInstructions[] = {
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{{&RawMachineAssembler::WordEqual, "WordEqual", kMips64Cmp, kMachInt64},
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1U},
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{{&RawMachineAssembler::WordNotEqual, "WordNotEqual", kMips64Cmp,
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kMachInt64},
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1U},
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{{&RawMachineAssembler::Word32Equal, "Word32Equal", kMips64Cmp, kMachInt32},
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1U},
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{{&RawMachineAssembler::Word32NotEqual, "Word32NotEqual", kMips64Cmp,
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kMachInt32},
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1U},
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{{&RawMachineAssembler::Int32LessThan, "Int32LessThan", kMips64Cmp,
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kMachInt32},
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1U},
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{{&RawMachineAssembler::Int32LessThanOrEqual, "Int32LessThanOrEqual",
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kMips64Cmp, kMachInt32},
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1U},
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{{&RawMachineAssembler::Int32GreaterThan, "Int32GreaterThan", kMips64Cmp,
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kMachInt32},
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1U},
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{{&RawMachineAssembler::Int32GreaterThanOrEqual, "Int32GreaterThanOrEqual",
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kMips64Cmp, kMachInt32},
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1U},
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{{&RawMachineAssembler::Uint32LessThan, "Uint32LessThan", kMips64Cmp,
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kMachUint32},
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1U},
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{{&RawMachineAssembler::Uint32LessThanOrEqual, "Uint32LessThanOrEqual",
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kMips64Cmp, kMachUint32},
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1U}};
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// ----------------------------------------------------------------------------
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// Conversion instructions.
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// ----------------------------------------------------------------------------
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const Conversion kConversionInstructions[] = {
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// Conversion instructions are related to machine_operator.h:
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// FPU conversions:
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// Convert representation of integers between float64 and int32/uint32.
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// The precise rounding mode and handling of out of range inputs are *not*
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// defined for these operators, since they are intended only for use with
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// integers.
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// mips instructions:
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// mtc1, cvt.d.w
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{{&RawMachineAssembler::ChangeInt32ToFloat64, "ChangeInt32ToFloat64",
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kMips64CvtDW, kMachFloat64},
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kMachInt32},
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// mips instructions:
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// cvt.d.uw
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{{&RawMachineAssembler::ChangeUint32ToFloat64, "ChangeUint32ToFloat64",
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kMips64CvtDUw, kMachFloat64},
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kMachInt32},
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// mips instructions:
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// mfc1, trunc double to word, for more details look at mips macro
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// asm and mips asm file
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{{&RawMachineAssembler::ChangeFloat64ToInt32, "ChangeFloat64ToInt32",
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kMips64TruncWD, kMachFloat64},
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kMachInt32},
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// mips instructions:
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// trunc double to unsigned word, for more details look at mips macro
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// asm and mips asm file
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{{&RawMachineAssembler::ChangeFloat64ToUint32, "ChangeFloat64ToUint32",
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kMips64TruncUwD, kMachFloat64},
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kMachInt32}};
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} // namespace
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typedef InstructionSelectorTestWithParam<FPCmp> InstructionSelectorFPCmpTest;
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TEST_P(InstructionSelectorFPCmpTest, Parameter) {
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const FPCmp cmp = GetParam();
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StreamBuilder m(this, kMachInt32, cmp.mi.machine_type, cmp.mi.machine_type);
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m.Return((m.*cmp.mi.constructor)(m.Parameter(0), m.Parameter(1)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(cmp.mi.arch_opcode, s[0]->arch_opcode());
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EXPECT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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EXPECT_EQ(kFlags_set, s[0]->flags_mode());
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EXPECT_EQ(cmp.cond, s[0]->flags_condition());
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}
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INSTANTIATE_TEST_CASE_P(InstructionSelectorTest, InstructionSelectorFPCmpTest,
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::testing::ValuesIn(kFPCmpInstructions));
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// ----------------------------------------------------------------------------
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// Arithmetic compare instructions integers
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// ----------------------------------------------------------------------------
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typedef InstructionSelectorTestWithParam<IntCmp> InstructionSelectorCmpTest;
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TEST_P(InstructionSelectorCmpTest, Parameter) {
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const IntCmp cmp = GetParam();
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const MachineType type = cmp.mi.machine_type;
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StreamBuilder m(this, type, type, type);
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m.Return((m.*cmp.mi.constructor)(m.Parameter(0), m.Parameter(1)));
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Stream s = m.Build();
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ASSERT_EQ(cmp.expected_size, s.size());
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EXPECT_EQ(cmp.mi.arch_opcode, s[0]->arch_opcode());
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EXPECT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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INSTANTIATE_TEST_CASE_P(InstructionSelectorTest, InstructionSelectorCmpTest,
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::testing::ValuesIn(kCmpInstructions));
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// ----------------------------------------------------------------------------
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// Shift instructions.
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// ----------------------------------------------------------------------------
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typedef InstructionSelectorTestWithParam<MachInst2>
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InstructionSelectorShiftTest;
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TEST_P(InstructionSelectorShiftTest, Immediate) {
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const MachInst2 dpi = GetParam();
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const MachineType type = dpi.machine_type;
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TRACED_FORRANGE(int32_t, imm, 0, (ElementSizeOf(type) * 8) - 1) {
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StreamBuilder m(this, type, type);
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m.Return((m.*dpi.constructor)(m.Parameter(0), m.Int32Constant(imm)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(dpi.arch_opcode, s[0]->arch_opcode());
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EXPECT_EQ(2U, s[0]->InputCount());
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EXPECT_TRUE(s[0]->InputAt(1)->IsImmediate());
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EXPECT_EQ(imm, s.ToInt32(s[0]->InputAt(1)));
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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}
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INSTANTIATE_TEST_CASE_P(InstructionSelectorTest, InstructionSelectorShiftTest,
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::testing::ValuesIn(kShiftInstructions));
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TEST_F(InstructionSelectorTest, Word32ShrWithWord32AndWithImmediate) {
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// The available shift operand range is `0 <= imm < 32`, but we also test
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// that immediates outside this range are handled properly (modulo-32).
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TRACED_FORRANGE(int32_t, shift, -32, 63) {
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int32_t lsb = shift & 0x1f;
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TRACED_FORRANGE(int32_t, width, 1, 32 - lsb) {
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uint32_t jnk = rng()->NextInt();
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jnk = (lsb > 0) ? (jnk >> (32 - lsb)) : 0;
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uint32_t msk = ((0xffffffffu >> (32 - width)) << lsb) | jnk;
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StreamBuilder m(this, kMachInt32, kMachInt32);
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m.Return(m.Word32Shr(m.Word32And(m.Parameter(0), m.Int32Constant(msk)),
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m.Int32Constant(shift)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMips64Ext, s[0]->arch_opcode());
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ASSERT_EQ(3U, s[0]->InputCount());
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EXPECT_EQ(lsb, s.ToInt32(s[0]->InputAt(1)));
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EXPECT_EQ(width, s.ToInt32(s[0]->InputAt(2)));
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}
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}
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TRACED_FORRANGE(int32_t, shift, -32, 63) {
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int32_t lsb = shift & 0x1f;
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TRACED_FORRANGE(int32_t, width, 1, 32 - lsb) {
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uint32_t jnk = rng()->NextInt();
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jnk = (lsb > 0) ? (jnk >> (32 - lsb)) : 0;
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uint32_t msk = ((0xffffffffu >> (32 - width)) << lsb) | jnk;
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StreamBuilder m(this, kMachInt32, kMachInt32);
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m.Return(m.Word32Shr(m.Word32And(m.Int32Constant(msk), m.Parameter(0)),
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m.Int32Constant(shift)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMips64Ext, s[0]->arch_opcode());
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ASSERT_EQ(3U, s[0]->InputCount());
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EXPECT_EQ(lsb, s.ToInt32(s[0]->InputAt(1)));
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EXPECT_EQ(width, s.ToInt32(s[0]->InputAt(2)));
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}
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}
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}
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TEST_F(InstructionSelectorTest, Word64ShrWithWord64AndWithImmediate) {
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// The available shift operand range is `0 <= imm < 64`, but we also test
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// that immediates outside this range are handled properly (modulo-64).
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TRACED_FORRANGE(int32_t, shift, -64, 127) {
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int32_t lsb = shift & 0x3f;
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TRACED_FORRANGE(int32_t, width, 1, 64 - lsb) {
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uint64_t jnk = rng()->NextInt64();
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jnk = (lsb > 0) ? (jnk >> (64 - lsb)) : 0;
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uint64_t msk =
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((V8_UINT64_C(0xffffffffffffffff) >> (64 - width)) << lsb) | jnk;
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StreamBuilder m(this, kMachInt64, kMachInt64);
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m.Return(m.Word64Shr(m.Word64And(m.Parameter(0), m.Int64Constant(msk)),
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m.Int64Constant(shift)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMips64Dext, s[0]->arch_opcode());
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ASSERT_EQ(3U, s[0]->InputCount());
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EXPECT_EQ(lsb, s.ToInt64(s[0]->InputAt(1)));
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EXPECT_EQ(width, s.ToInt64(s[0]->InputAt(2)));
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}
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}
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TRACED_FORRANGE(int32_t, shift, -64, 127) {
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int32_t lsb = shift & 0x3f;
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TRACED_FORRANGE(int32_t, width, 1, 64 - lsb) {
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uint64_t jnk = rng()->NextInt64();
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jnk = (lsb > 0) ? (jnk >> (64 - lsb)) : 0;
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uint64_t msk =
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((V8_UINT64_C(0xffffffffffffffff) >> (64 - width)) << lsb) | jnk;
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StreamBuilder m(this, kMachInt64, kMachInt64);
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m.Return(m.Word64Shr(m.Word64And(m.Int64Constant(msk), m.Parameter(0)),
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m.Int64Constant(shift)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMips64Dext, s[0]->arch_opcode());
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ASSERT_EQ(3U, s[0]->InputCount());
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EXPECT_EQ(lsb, s.ToInt64(s[0]->InputAt(1)));
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EXPECT_EQ(width, s.ToInt64(s[0]->InputAt(2)));
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}
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}
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}
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// ----------------------------------------------------------------------------
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// Logical instructions.
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// ----------------------------------------------------------------------------
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typedef InstructionSelectorTestWithParam<MachInst2>
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InstructionSelectorLogicalTest;
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TEST_P(InstructionSelectorLogicalTest, Parameter) {
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const MachInst2 dpi = GetParam();
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const MachineType type = dpi.machine_type;
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StreamBuilder m(this, type, type, type);
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m.Return((m.*dpi.constructor)(m.Parameter(0), m.Parameter(1)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(dpi.arch_opcode, s[0]->arch_opcode());
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EXPECT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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INSTANTIATE_TEST_CASE_P(InstructionSelectorTest, InstructionSelectorLogicalTest,
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::testing::ValuesIn(kLogicalInstructions));
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TEST_F(InstructionSelectorTest, Word32AndWithImmediateWithWord32Shr) {
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// The available shift operand range is `0 <= imm < 32`, but we also test
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// that immediates outside this range are handled properly (modulo-32).
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TRACED_FORRANGE(int32_t, shift, -32, 63) {
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int32_t lsb = shift & 0x1f;
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TRACED_FORRANGE(int32_t, width, 1, 31) {
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uint32_t msk = (1 << width) - 1;
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StreamBuilder m(this, kMachInt32, kMachInt32);
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m.Return(m.Word32And(m.Word32Shr(m.Parameter(0), m.Int32Constant(shift)),
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m.Int32Constant(msk)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMips64Ext, s[0]->arch_opcode());
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ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(lsb, s.ToInt32(s[0]->InputAt(1)));
|
|
int32_t actual_width = (lsb + width > 32) ? (32 - lsb) : width;
|
|
EXPECT_EQ(actual_width, s.ToInt32(s[0]->InputAt(2)));
|
|
}
|
|
}
|
|
TRACED_FORRANGE(int32_t, shift, -32, 63) {
|
|
int32_t lsb = shift & 0x1f;
|
|
TRACED_FORRANGE(int32_t, width, 1, 31) {
|
|
uint32_t msk = (1 << width) - 1;
|
|
StreamBuilder m(this, kMachInt32, kMachInt32);
|
|
m.Return(
|
|
m.Word32And(m.Int32Constant(msk),
|
|
m.Word32Shr(m.Parameter(0), m.Int32Constant(shift))));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMips64Ext, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(lsb, s.ToInt32(s[0]->InputAt(1)));
|
|
int32_t actual_width = (lsb + width > 32) ? (32 - lsb) : width;
|
|
EXPECT_EQ(actual_width, s.ToInt32(s[0]->InputAt(2)));
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Word64AndWithImmediateWithWord64Shr) {
|
|
// The available shift operand range is `0 <= imm < 64`, but we also test
|
|
// that immediates outside this range are handled properly (modulo-64).
|
|
TRACED_FORRANGE(int64_t, shift, -64, 127) {
|
|
int64_t lsb = shift & 0x3f;
|
|
TRACED_FORRANGE(int64_t, width, 1, 63) {
|
|
uint64_t msk = (V8_UINT64_C(1) << width) - 1;
|
|
StreamBuilder m(this, kMachInt64, kMachInt64);
|
|
m.Return(m.Word64And(m.Word64Shr(m.Parameter(0), m.Int64Constant(shift)),
|
|
m.Int64Constant(msk)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMips64Dext, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(lsb, s.ToInt64(s[0]->InputAt(1)));
|
|
int64_t actual_width = (lsb + width > 64) ? (64 - lsb) : width;
|
|
EXPECT_EQ(actual_width, s.ToInt64(s[0]->InputAt(2)));
|
|
}
|
|
}
|
|
TRACED_FORRANGE(int64_t, shift, -64, 127) {
|
|
int64_t lsb = shift & 0x3f;
|
|
TRACED_FORRANGE(int64_t, width, 1, 63) {
|
|
uint64_t msk = (V8_UINT64_C(1) << width) - 1;
|
|
StreamBuilder m(this, kMachInt64, kMachInt64);
|
|
m.Return(
|
|
m.Word64And(m.Int64Constant(msk),
|
|
m.Word64Shr(m.Parameter(0), m.Int64Constant(shift))));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMips64Dext, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(lsb, s.ToInt64(s[0]->InputAt(1)));
|
|
int64_t actual_width = (lsb + width > 64) ? (64 - lsb) : width;
|
|
EXPECT_EQ(actual_width, s.ToInt64(s[0]->InputAt(2)));
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// MUL/DIV instructions.
|
|
// ----------------------------------------------------------------------------
|
|
typedef InstructionSelectorTestWithParam<MachInst2>
|
|
InstructionSelectorMulDivTest;
|
|
|
|
TEST_P(InstructionSelectorMulDivTest, Parameter) {
|
|
const MachInst2 dpi = GetParam();
|
|
const MachineType type = dpi.machine_type;
|
|
StreamBuilder m(this, type, type, type);
|
|
m.Return((m.*dpi.constructor)(m.Parameter(0), m.Parameter(1)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(dpi.arch_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
|
|
INSTANTIATE_TEST_CASE_P(InstructionSelectorTest, InstructionSelectorMulDivTest,
|
|
::testing::ValuesIn(kMulDivInstructions));
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// MOD instructions.
|
|
// ----------------------------------------------------------------------------
|
|
typedef InstructionSelectorTestWithParam<MachInst2> InstructionSelectorModTest;
|
|
|
|
TEST_P(InstructionSelectorModTest, Parameter) {
|
|
const MachInst2 dpi = GetParam();
|
|
const MachineType type = dpi.machine_type;
|
|
StreamBuilder m(this, type, type, type);
|
|
m.Return((m.*dpi.constructor)(m.Parameter(0), m.Parameter(1)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(dpi.arch_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
|
|
INSTANTIATE_TEST_CASE_P(InstructionSelectorTest, InstructionSelectorModTest,
|
|
::testing::ValuesIn(kModInstructions));
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Floating point instructions.
|
|
// ----------------------------------------------------------------------------
|
|
typedef InstructionSelectorTestWithParam<MachInst2>
|
|
InstructionSelectorFPArithTest;
|
|
|
|
TEST_P(InstructionSelectorFPArithTest, Parameter) {
|
|
const MachInst2 fpa = GetParam();
|
|
StreamBuilder m(this, fpa.machine_type, fpa.machine_type, fpa.machine_type);
|
|
m.Return((m.*fpa.constructor)(m.Parameter(0), m.Parameter(1)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(fpa.arch_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
|
|
INSTANTIATE_TEST_CASE_P(InstructionSelectorTest, InstructionSelectorFPArithTest,
|
|
::testing::ValuesIn(kFPArithInstructions));
|
|
// ----------------------------------------------------------------------------
|
|
// Integer arithmetic
|
|
// ----------------------------------------------------------------------------
|
|
typedef InstructionSelectorTestWithParam<MachInst2>
|
|
InstructionSelectorIntArithTwoTest;
|
|
|
|
TEST_P(InstructionSelectorIntArithTwoTest, Parameter) {
|
|
const MachInst2 intpa = GetParam();
|
|
StreamBuilder m(this, intpa.machine_type, intpa.machine_type,
|
|
intpa.machine_type);
|
|
m.Return((m.*intpa.constructor)(m.Parameter(0), m.Parameter(1)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(intpa.arch_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
|
|
INSTANTIATE_TEST_CASE_P(InstructionSelectorTest,
|
|
InstructionSelectorIntArithTwoTest,
|
|
::testing::ValuesIn(kAddSubInstructions));
|
|
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// One node.
|
|
// ----------------------------------------------------------------------------
|
|
|
|
|
|
typedef InstructionSelectorTestWithParam<MachInst1>
|
|
InstructionSelectorIntArithOneTest;
|
|
|
|
TEST_P(InstructionSelectorIntArithOneTest, Parameter) {
|
|
const MachInst1 intpa = GetParam();
|
|
StreamBuilder m(this, intpa.machine_type, intpa.machine_type,
|
|
intpa.machine_type);
|
|
m.Return((m.*intpa.constructor)(m.Parameter(0)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(intpa.arch_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
|
|
INSTANTIATE_TEST_CASE_P(InstructionSelectorTest,
|
|
InstructionSelectorIntArithOneTest,
|
|
::testing::ValuesIn(kAddSubOneInstructions));
|
|
// ----------------------------------------------------------------------------
|
|
// Conversions.
|
|
// ----------------------------------------------------------------------------
|
|
typedef InstructionSelectorTestWithParam<Conversion>
|
|
InstructionSelectorConversionTest;
|
|
|
|
TEST_P(InstructionSelectorConversionTest, Parameter) {
|
|
const Conversion conv = GetParam();
|
|
StreamBuilder m(this, conv.mi.machine_type, conv.src_machine_type);
|
|
m.Return((m.*conv.mi.constructor)(m.Parameter(0)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(conv.mi.arch_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
|
|
INSTANTIATE_TEST_CASE_P(InstructionSelectorTest,
|
|
InstructionSelectorConversionTest,
|
|
::testing::ValuesIn(kConversionInstructions));
|
|
|
|
TEST_F(InstructionSelectorTest, ChangesFromToSmi) {
|
|
{
|
|
StreamBuilder m(this, kMachInt32, kMachInt32);
|
|
m.Return(m.TruncateInt64ToInt32(
|
|
m.Word64Sar(m.Parameter(0), m.Int32Constant(32))));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMips64Dsar, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_None, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
{
|
|
StreamBuilder m(this, kMachInt32, kMachInt32);
|
|
m.Return(
|
|
m.Word64Shl(m.ChangeInt32ToInt64(m.Parameter(0)), m.Int32Constant(32)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMips64Dshl, s[0]->arch_opcode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, CombineShiftsWithMul) {
|
|
{
|
|
StreamBuilder m(this, kMachInt32, kMachInt32);
|
|
m.Return(m.Int32Mul(m.Word64Sar(m.Parameter(0), m.Int32Constant(32)),
|
|
m.Word64Sar(m.Parameter(0), m.Int32Constant(32))));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMips64DMulHigh, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_None, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, CombineShiftsWithDivMod) {
|
|
{
|
|
StreamBuilder m(this, kMachInt32, kMachInt32);
|
|
m.Return(m.Int32Div(m.Word64Sar(m.Parameter(0), m.Int32Constant(32)),
|
|
m.Word64Sar(m.Parameter(0), m.Int32Constant(32))));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMips64Ddiv, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_None, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
{
|
|
StreamBuilder m(this, kMachInt32, kMachInt32);
|
|
m.Return(m.Int32Mod(m.Word64Sar(m.Parameter(0), m.Int32Constant(32)),
|
|
m.Word64Sar(m.Parameter(0), m.Int32Constant(32))));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMips64Dmod, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_None, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
}
|
|
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Loads and stores.
|
|
// ----------------------------------------------------------------------------
|
|
|
|
|
|
namespace {
|
|
|
|
struct MemoryAccess {
|
|
MachineType type;
|
|
ArchOpcode load_opcode;
|
|
ArchOpcode store_opcode;
|
|
};
|
|
|
|
static const MemoryAccess kMemoryAccesses[] = {
|
|
{kMachInt8, kMips64Lb, kMips64Sb},
|
|
{kMachUint8, kMips64Lbu, kMips64Sb},
|
|
{kMachInt16, kMips64Lh, kMips64Sh},
|
|
{kMachUint16, kMips64Lhu, kMips64Sh},
|
|
{kMachInt32, kMips64Lw, kMips64Sw},
|
|
{kMachFloat32, kMips64Lwc1, kMips64Swc1},
|
|
{kMachFloat64, kMips64Ldc1, kMips64Sdc1},
|
|
{kMachInt64, kMips64Ld, kMips64Sd}};
|
|
|
|
|
|
struct MemoryAccessImm {
|
|
MachineType type;
|
|
ArchOpcode load_opcode;
|
|
ArchOpcode store_opcode;
|
|
bool (InstructionSelectorTest::Stream::*val_predicate)(
|
|
const InstructionOperand*) const;
|
|
const int32_t immediates[40];
|
|
};
|
|
|
|
|
|
std::ostream& operator<<(std::ostream& os, const MemoryAccessImm& acc) {
|
|
return os << acc.type;
|
|
}
|
|
|
|
|
|
struct MemoryAccessImm1 {
|
|
MachineType type;
|
|
ArchOpcode load_opcode;
|
|
ArchOpcode store_opcode;
|
|
bool (InstructionSelectorTest::Stream::*val_predicate)(
|
|
const InstructionOperand*) const;
|
|
const int32_t immediates[5];
|
|
};
|
|
|
|
|
|
std::ostream& operator<<(std::ostream& os, const MemoryAccessImm1& acc) {
|
|
return os << acc.type;
|
|
}
|
|
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Loads and stores immediate values
|
|
// ----------------------------------------------------------------------------
|
|
|
|
|
|
const MemoryAccessImm kMemoryAccessesImm[] = {
|
|
{kMachInt8,
|
|
kMips64Lb,
|
|
kMips64Sb,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-4095, -3340, -3231, -3224, -3088, -1758, -1203, -123, -117, -91, -89,
|
|
-87, -86, -82, -44, -23, -3, 0, 7, 10, 39, 52, 69, 71, 91, 92, 107, 109,
|
|
115, 124, 286, 655, 1362, 1569, 2587, 3067, 3096, 3462, 3510, 4095}},
|
|
{kMachUint8,
|
|
kMips64Lbu,
|
|
kMips64Sb,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-4095, -3340, -3231, -3224, -3088, -1758, -1203, -123, -117, -91, -89,
|
|
-87, -86, -82, -44, -23, -3, 0, 7, 10, 39, 52, 69, 71, 91, 92, 107, 109,
|
|
115, 124, 286, 655, 1362, 1569, 2587, 3067, 3096, 3462, 3510, 4095}},
|
|
{kMachInt16,
|
|
kMips64Lh,
|
|
kMips64Sh,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-4095, -3340, -3231, -3224, -3088, -1758, -1203, -123, -117, -91, -89,
|
|
-87, -86, -82, -44, -23, -3, 0, 7, 10, 39, 52, 69, 71, 91, 92, 107, 109,
|
|
115, 124, 286, 655, 1362, 1569, 2587, 3067, 3096, 3462, 3510, 4095}},
|
|
{kMachUint16,
|
|
kMips64Lhu,
|
|
kMips64Sh,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-4095, -3340, -3231, -3224, -3088, -1758, -1203, -123, -117, -91, -89,
|
|
-87, -86, -82, -44, -23, -3, 0, 7, 10, 39, 52, 69, 71, 91, 92, 107, 109,
|
|
115, 124, 286, 655, 1362, 1569, 2587, 3067, 3096, 3462, 3510, 4095}},
|
|
{kMachInt32,
|
|
kMips64Lw,
|
|
kMips64Sw,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-4095, -3340, -3231, -3224, -3088, -1758, -1203, -123, -117, -91, -89,
|
|
-87, -86, -82, -44, -23, -3, 0, 7, 10, 39, 52, 69, 71, 91, 92, 107, 109,
|
|
115, 124, 286, 655, 1362, 1569, 2587, 3067, 3096, 3462, 3510, 4095}},
|
|
{kMachFloat32,
|
|
kMips64Lwc1,
|
|
kMips64Swc1,
|
|
&InstructionSelectorTest::Stream::IsDouble,
|
|
{-4095, -3340, -3231, -3224, -3088, -1758, -1203, -123, -117, -91, -89,
|
|
-87, -86, -82, -44, -23, -3, 0, 7, 10, 39, 52, 69, 71, 91, 92, 107, 109,
|
|
115, 124, 286, 655, 1362, 1569, 2587, 3067, 3096, 3462, 3510, 4095}},
|
|
{kMachFloat64,
|
|
kMips64Ldc1,
|
|
kMips64Sdc1,
|
|
&InstructionSelectorTest::Stream::IsDouble,
|
|
{-4095, -3340, -3231, -3224, -3088, -1758, -1203, -123, -117, -91, -89,
|
|
-87, -86, -82, -44, -23, -3, 0, 7, 10, 39, 52, 69, 71, 91, 92, 107, 109,
|
|
115, 124, 286, 655, 1362, 1569, 2587, 3067, 3096, 3462, 3510, 4095}},
|
|
{kMachInt64,
|
|
kMips64Ld,
|
|
kMips64Sd,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-4095, -3340, -3231, -3224, -3088, -1758, -1203, -123, -117, -91, -89,
|
|
-87, -86, -82, -44, -23, -3, 0, 7, 10, 39, 52, 69, 71, 91, 92, 107, 109,
|
|
115, 124, 286, 655, 1362, 1569, 2587, 3067, 3096, 3462, 3510, 4095}}};
|
|
|
|
|
|
const MemoryAccessImm1 kMemoryAccessImmMoreThan16bit[] = {
|
|
{kMachInt8,
|
|
kMips64Lb,
|
|
kMips64Sb,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-65000, -55000, 32777, 55000, 65000}},
|
|
{kMachInt8,
|
|
kMips64Lbu,
|
|
kMips64Sb,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-65000, -55000, 32777, 55000, 65000}},
|
|
{kMachInt16,
|
|
kMips64Lh,
|
|
kMips64Sh,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-65000, -55000, 32777, 55000, 65000}},
|
|
{kMachInt16,
|
|
kMips64Lhu,
|
|
kMips64Sh,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-65000, -55000, 32777, 55000, 65000}},
|
|
{kMachInt32,
|
|
kMips64Lw,
|
|
kMips64Sw,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-65000, -55000, 32777, 55000, 65000}},
|
|
{kMachFloat32,
|
|
kMips64Lwc1,
|
|
kMips64Swc1,
|
|
&InstructionSelectorTest::Stream::IsDouble,
|
|
{-65000, -55000, 32777, 55000, 65000}},
|
|
{kMachFloat64,
|
|
kMips64Ldc1,
|
|
kMips64Sdc1,
|
|
&InstructionSelectorTest::Stream::IsDouble,
|
|
{-65000, -55000, 32777, 55000, 65000}},
|
|
{kMachInt64,
|
|
kMips64Ld,
|
|
kMips64Sd,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-65000, -55000, 32777, 55000, 65000}}};
|
|
|
|
} // namespace
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typedef InstructionSelectorTestWithParam<MemoryAccess>
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InstructionSelectorMemoryAccessTest;
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TEST_P(InstructionSelectorMemoryAccessTest, LoadWithParameters) {
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const MemoryAccess memacc = GetParam();
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StreamBuilder m(this, memacc.type, kMachPtr, kMachInt32);
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m.Return(m.Load(memacc.type, m.Parameter(0)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(memacc.load_opcode, s[0]->arch_opcode());
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EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
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}
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TEST_P(InstructionSelectorMemoryAccessTest, StoreWithParameters) {
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const MemoryAccess memacc = GetParam();
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StreamBuilder m(this, kMachInt32, kMachPtr, kMachInt32, memacc.type);
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m.Store(memacc.type, m.Parameter(0), m.Parameter(1), kNoWriteBarrier);
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m.Return(m.Int32Constant(0));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode());
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EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
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}
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INSTANTIATE_TEST_CASE_P(InstructionSelectorTest,
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InstructionSelectorMemoryAccessTest,
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::testing::ValuesIn(kMemoryAccesses));
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// ----------------------------------------------------------------------------
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// Load immediate.
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// ----------------------------------------------------------------------------
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typedef InstructionSelectorTestWithParam<MemoryAccessImm>
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InstructionSelectorMemoryAccessImmTest;
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TEST_P(InstructionSelectorMemoryAccessImmTest, LoadWithImmediateIndex) {
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const MemoryAccessImm memacc = GetParam();
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TRACED_FOREACH(int32_t, index, memacc.immediates) {
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StreamBuilder m(this, memacc.type, kMachPtr);
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m.Return(m.Load(memacc.type, m.Parameter(0), m.Int32Constant(index)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(memacc.load_opcode, s[0]->arch_opcode());
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EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
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ASSERT_EQ(2U, s[0]->InputCount());
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ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind());
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EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1)));
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ASSERT_EQ(1U, s[0]->OutputCount());
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EXPECT_TRUE((s.*memacc.val_predicate)(s[0]->Output()));
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}
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}
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// ----------------------------------------------------------------------------
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// Store immediate.
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// ----------------------------------------------------------------------------
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TEST_P(InstructionSelectorMemoryAccessImmTest, StoreWithImmediateIndex) {
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const MemoryAccessImm memacc = GetParam();
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TRACED_FOREACH(int32_t, index, memacc.immediates) {
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StreamBuilder m(this, kMachInt32, kMachPtr, memacc.type);
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m.Store(memacc.type, m.Parameter(0), m.Int32Constant(index), m.Parameter(1),
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kNoWriteBarrier);
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m.Return(m.Int32Constant(0));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode());
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EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
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ASSERT_EQ(3U, s[0]->InputCount());
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ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind());
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EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1)));
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EXPECT_EQ(0U, s[0]->OutputCount());
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}
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}
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INSTANTIATE_TEST_CASE_P(InstructionSelectorTest,
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InstructionSelectorMemoryAccessImmTest,
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::testing::ValuesIn(kMemoryAccessesImm));
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// ----------------------------------------------------------------------------
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// Load/store offsets more than 16 bits.
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// ----------------------------------------------------------------------------
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typedef InstructionSelectorTestWithParam<MemoryAccessImm1>
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InstructionSelectorMemoryAccessImmMoreThan16bitTest;
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TEST_P(InstructionSelectorMemoryAccessImmMoreThan16bitTest,
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LoadWithImmediateIndex) {
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const MemoryAccessImm1 memacc = GetParam();
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TRACED_FOREACH(int32_t, index, memacc.immediates) {
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StreamBuilder m(this, memacc.type, kMachPtr);
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m.Return(m.Load(memacc.type, m.Parameter(0), m.Int32Constant(index)));
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Stream s = m.Build();
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ASSERT_EQ(2U, s.size());
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// kMips64Dadd is expected opcode
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// size more than 16 bits wide
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EXPECT_EQ(kMips64Dadd, s[0]->arch_opcode());
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EXPECT_EQ(kMode_None, s[0]->addressing_mode());
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EXPECT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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}
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TEST_P(InstructionSelectorMemoryAccessImmMoreThan16bitTest,
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StoreWithImmediateIndex) {
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const MemoryAccessImm1 memacc = GetParam();
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TRACED_FOREACH(int32_t, index, memacc.immediates) {
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StreamBuilder m(this, kMachInt32, kMachPtr, memacc.type);
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m.Store(memacc.type, m.Parameter(0), m.Int32Constant(index), m.Parameter(1),
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kNoWriteBarrier);
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m.Return(m.Int32Constant(0));
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Stream s = m.Build();
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ASSERT_EQ(2U, s.size());
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// kMips64Add is expected opcode
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// size more than 16 bits wide
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EXPECT_EQ(kMips64Dadd, s[0]->arch_opcode());
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EXPECT_EQ(kMode_None, s[0]->addressing_mode());
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EXPECT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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}
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INSTANTIATE_TEST_CASE_P(InstructionSelectorTest,
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InstructionSelectorMemoryAccessImmMoreThan16bitTest,
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::testing::ValuesIn(kMemoryAccessImmMoreThan16bit));
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// ----------------------------------------------------------------------------
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// kMips64Cmp with zero testing.
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// ----------------------------------------------------------------------------
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TEST_F(InstructionSelectorTest, Word32EqualWithZero) {
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{
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StreamBuilder m(this, kMachInt32, kMachInt32);
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m.Return(m.Word32Equal(m.Parameter(0), m.Int32Constant(0)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMips64Cmp, s[0]->arch_opcode());
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EXPECT_EQ(kMode_None, s[0]->addressing_mode());
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ASSERT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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EXPECT_EQ(kFlags_set, s[0]->flags_mode());
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EXPECT_EQ(kEqual, s[0]->flags_condition());
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}
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{
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StreamBuilder m(this, kMachInt32, kMachInt32);
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m.Return(m.Word32Equal(m.Int32Constant(0), m.Parameter(0)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMips64Cmp, s[0]->arch_opcode());
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EXPECT_EQ(kMode_None, s[0]->addressing_mode());
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ASSERT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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EXPECT_EQ(kFlags_set, s[0]->flags_mode());
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EXPECT_EQ(kEqual, s[0]->flags_condition());
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}
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}
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TEST_F(InstructionSelectorTest, Word64EqualWithZero) {
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{
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StreamBuilder m(this, kMachInt64, kMachInt64);
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m.Return(m.Word64Equal(m.Parameter(0), m.Int64Constant(0)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMips64Cmp, s[0]->arch_opcode());
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EXPECT_EQ(kMode_None, s[0]->addressing_mode());
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ASSERT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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EXPECT_EQ(kFlags_set, s[0]->flags_mode());
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EXPECT_EQ(kEqual, s[0]->flags_condition());
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}
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{
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StreamBuilder m(this, kMachInt64, kMachInt64);
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m.Return(m.Word64Equal(m.Int32Constant(0), m.Parameter(0)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMips64Cmp, s[0]->arch_opcode());
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EXPECT_EQ(kMode_None, s[0]->addressing_mode());
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ASSERT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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EXPECT_EQ(kFlags_set, s[0]->flags_mode());
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EXPECT_EQ(kEqual, s[0]->flags_condition());
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}
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}
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TEST_F(InstructionSelectorTest, Word32Clz) {
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StreamBuilder m(this, kMachUint32, kMachUint32);
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Node* const p0 = m.Parameter(0);
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Node* const n = m.Word32Clz(p0);
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m.Return(n);
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMips64Clz, s[0]->arch_opcode());
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ASSERT_EQ(1U, s[0]->InputCount());
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EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
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ASSERT_EQ(1U, s[0]->OutputCount());
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EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
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}
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TEST_F(InstructionSelectorTest, Word64Clz) {
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StreamBuilder m(this, kMachUint64, kMachUint64);
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Node* const p0 = m.Parameter(0);
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Node* const n = m.Word64Clz(p0);
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m.Return(n);
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMips64Dclz, s[0]->arch_opcode());
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ASSERT_EQ(1U, s[0]->InputCount());
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EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
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ASSERT_EQ(1U, s[0]->OutputCount());
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EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
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}
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TEST_F(InstructionSelectorTest, Float32Abs) {
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StreamBuilder m(this, kMachFloat32, kMachFloat32);
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Node* const p0 = m.Parameter(0);
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Node* const n = m.Float32Abs(p0);
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m.Return(n);
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMips64AbsS, s[0]->arch_opcode());
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ASSERT_EQ(1U, s[0]->InputCount());
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EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
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ASSERT_EQ(1U, s[0]->OutputCount());
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EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
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}
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TEST_F(InstructionSelectorTest, Float64Abs) {
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StreamBuilder m(this, kMachFloat64, kMachFloat64);
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Node* const p0 = m.Parameter(0);
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Node* const n = m.Float64Abs(p0);
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m.Return(n);
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMips64AbsD, s[0]->arch_opcode());
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ASSERT_EQ(1U, s[0]->InputCount());
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EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
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ASSERT_EQ(1U, s[0]->OutputCount());
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EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
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}
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TEST_F(InstructionSelectorTest, Float32Max) {
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StreamBuilder m(this, kMachFloat32, kMachFloat32, kMachFloat32);
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Node* const p0 = m.Parameter(0);
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Node* const p1 = m.Parameter(1);
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Node* const n = m.Float32Max(p0, p1);
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m.Return(n);
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Stream s = m.Build();
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// Float32Max is `(b < a) ? a : b`.
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMips64Float32Max, s[0]->arch_opcode());
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ASSERT_EQ(2U, s[0]->InputCount());
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ASSERT_EQ(1U, s[0]->OutputCount());
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EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
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}
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TEST_F(InstructionSelectorTest, Float32Min) {
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StreamBuilder m(this, kMachFloat32, kMachFloat32, kMachFloat32);
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Node* const p0 = m.Parameter(0);
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Node* const p1 = m.Parameter(1);
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Node* const n = m.Float32Min(p0, p1);
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m.Return(n);
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Stream s = m.Build();
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// Float32Min is `(a < b) ? a : b`.
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMips64Float32Min, s[0]->arch_opcode());
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ASSERT_EQ(2U, s[0]->InputCount());
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ASSERT_EQ(1U, s[0]->OutputCount());
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EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
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}
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TEST_F(InstructionSelectorTest, Float64Max) {
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StreamBuilder m(this, kMachFloat64, kMachFloat64, kMachFloat64);
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Node* const p0 = m.Parameter(0);
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Node* const p1 = m.Parameter(1);
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Node* const n = m.Float64Max(p0, p1);
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m.Return(n);
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Stream s = m.Build();
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// Float64Max is `(b < a) ? a : b`.
|
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMips64Float64Max, s[0]->arch_opcode());
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ASSERT_EQ(2U, s[0]->InputCount());
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ASSERT_EQ(1U, s[0]->OutputCount());
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EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
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}
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TEST_F(InstructionSelectorTest, Float64Min) {
|
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StreamBuilder m(this, kMachFloat64, kMachFloat64, kMachFloat64);
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Node* const p0 = m.Parameter(0);
|
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Node* const p1 = m.Parameter(1);
|
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Node* const n = m.Float64Min(p0, p1);
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m.Return(n);
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Stream s = m.Build();
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// Float64Min is `(a < b) ? a : b`.
|
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMips64Float64Min, s[0]->arch_opcode());
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ASSERT_EQ(2U, s[0]->InputCount());
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ASSERT_EQ(1U, s[0]->OutputCount());
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EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
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}
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} // namespace compiler
|
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} // namespace internal
|
|
} // namespace v8
|