7276f14ca7
Added a few samples and support for building them. The samples include a simple shell that can be used to benchmark and test V8.
Changed V8::GetVersion to return the version as a string.
Added source for lazily loaded scripts to snapshots and made serialization non-destructive.
Improved ARM support by fixing the write barrier code to use aligned loads and stores and by removing premature locals optimization that relied on broken support for callee-saved registers (removed).
Refactored the code for marking live objects during garbage collection and the code for allocating objects in paged spaces. Introduced an abstraction for the map word of a heap-allocated object and changed the memory allocator to allocate executable memory only for spaces that may contain code objects.
Moved StringBuilder to utils.h and ScopedLock to platform.h, where they can be used by debugging and logging modules. Added thread-safe message queues for dealing with debugger events.
Fixed the source code reported by toString for certain builtin empty functions and made sure that the prototype property of a function is enumerable.
Improved performance of converting values to condition flags in generated code.
Merged disassembler-{arch} files.
git-svn-id: http://v8.googlecode.com/svn/trunk@8 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
808 lines
24 KiB
C++
808 lines
24 KiB
C++
// Copyright (c) 1994-2006 Sun Microsystems Inc.
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// All Rights Reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// - Redistribution in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// - Neither the name of Sun Microsystems or the names of contributors may
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// be used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// The original source code covered by the above license above has been
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// modified significantly by Google Inc.
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// Copyright 2006-2008 Google Inc. All Rights Reserved.
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// A light-weight IA32 Assembler.
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#ifndef V8_ASSEMBLER_IA32_H_
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#define V8_ASSEMBLER_IA32_H_
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namespace v8 { namespace internal {
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// CPU Registers.
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//
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// 1) We would prefer to use an enum, but enum values are assignment-
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// compatible with int, which has caused code-generation bugs.
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//
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// 2) We would prefer to use a class instead of a struct but we don't like
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// the register initialization to depend on the particular initialization
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// order (which appears to be different on OS X, Linux, and Windows for the
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// installed versions of C++ we tried). Using a struct permits C-style
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// "initialization". Also, the Register objects cannot be const as this
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// forces initialization stubs in MSVC, making us dependent on initialization
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// order.
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//
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// 3) By not using an enum, we are possibly preventing the compiler from
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// doing certain constant folds, which may significantly reduce the
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// code generated for some assembly instructions (because they boil down
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// to a few constants). If this is a problem, we could change the code
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// such that we use an enum in optimized mode, and the struct in debug
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// mode. This way we get the compile-time error checking in debug mode
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// and best performance in optimized code.
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//
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struct Register {
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bool is_valid() const { return 0 <= code_ && code_ < 8; }
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bool is(Register reg) const { return code_ == reg.code_; }
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int code() const {
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ASSERT(is_valid());
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return code_;
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}
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int bit() const {
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ASSERT(is_valid());
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return 1 << code_;
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}
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// (unfortunately we can't make this private in a struct)
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int code_;
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};
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extern Register eax;
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extern Register ecx;
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extern Register edx;
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extern Register ebx;
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extern Register esp;
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extern Register ebp;
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extern Register esi;
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extern Register edi;
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extern Register no_reg;
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struct XMMRegister {
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bool is_valid() const { return 0 <= code_ && code_ < 2; } // currently
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int code() const {
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ASSERT(is_valid());
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return code_;
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}
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int code_;
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};
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extern XMMRegister xmm0;
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extern XMMRegister xmm1;
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extern XMMRegister xmm2;
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extern XMMRegister xmm3;
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extern XMMRegister xmm4;
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extern XMMRegister xmm5;
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extern XMMRegister xmm6;
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extern XMMRegister xmm7;
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enum Condition {
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// any value < 0 is considered no_condition
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no_condition = -1,
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overflow = 0,
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no_overflow = 1,
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below = 2,
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above_equal = 3,
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equal = 4,
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not_equal = 5,
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below_equal = 6,
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above = 7,
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sign = 8,
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not_sign = 9,
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parity_even = 10,
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parity_odd = 11,
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less = 12,
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greater_equal = 13,
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less_equal = 14,
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greater = 15,
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// aliases
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zero = equal,
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not_zero = not_equal,
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negative = sign,
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positive = not_sign
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};
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// Returns the equivalent of !cc.
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// Negation of the default no_condition (-1) results in a non-default
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// no_condition value (-2). As long as tests for no_condition check
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// for condition < 0, this will work as expected.
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inline Condition NegateCondition(Condition cc);
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// Corresponds to transposing the operands of a comparison.
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inline Condition ReverseCondition(Condition cc) {
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switch (cc) {
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case below:
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return above;
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case above:
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return below;
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case above_equal:
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return below_equal;
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case below_equal:
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return above_equal;
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case less:
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return greater;
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case greater:
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return less;
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case greater_equal:
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return less_equal;
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case less_equal:
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return greater_equal;
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default:
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return cc;
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};
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}
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enum Hint {
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no_hint = 0,
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not_taken = 0x2e,
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taken = 0x3e
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};
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// -----------------------------------------------------------------------------
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// Machine instruction Immediates
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class Immediate BASE_EMBEDDED {
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public:
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inline explicit Immediate(int x);
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inline explicit Immediate(const char* s);
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inline explicit Immediate(const ExternalReference& ext);
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inline explicit Immediate(Handle<Object> handle);
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inline explicit Immediate(Smi* value);
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bool is_zero() const { return x_ == 0 && rmode_ == no_reloc; }
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bool is_int8() const { return -128 <= x_ && x_ < 128 && rmode_ == no_reloc; }
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private:
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int x_;
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RelocMode rmode_;
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friend class Assembler;
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};
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// -----------------------------------------------------------------------------
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// Machine instruction Operands
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enum ScaleFactor {
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times_1 = 0,
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times_2 = 1,
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times_4 = 2,
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times_8 = 3
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};
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class Operand BASE_EMBEDDED {
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public:
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// reg
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INLINE(explicit Operand(Register reg));
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// [disp/r]
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INLINE(explicit Operand(int32_t disp, RelocMode rmode));
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// disp only must always be relocated
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// [base + disp/r]
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explicit Operand(Register base, int32_t disp, RelocMode rmode = no_reloc);
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// [base + index*scale + disp/r]
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explicit Operand(Register base,
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Register index,
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ScaleFactor scale,
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int32_t disp,
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RelocMode rmode = no_reloc);
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// [index*scale + disp/r]
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explicit Operand(Register index,
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ScaleFactor scale,
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int32_t disp,
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RelocMode rmode = no_reloc);
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static Operand StaticVariable(const ExternalReference& ext) {
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return Operand(reinterpret_cast<int32_t>(ext.address()),
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external_reference);
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}
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static Operand StaticArray(Register index,
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ScaleFactor scale,
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const ExternalReference& arr) {
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return Operand(index, scale, reinterpret_cast<int32_t>(arr.address()),
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external_reference);
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}
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// Returns true if this Operand is a wrapper for the specified register.
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bool is_reg(Register reg) const;
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private:
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// Mutable because reg in ModR/M byte is set by Assembler via set_reg().
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mutable byte buf_[6];
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// The number of bytes in buf_.
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unsigned int len_;
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// Only valid if len_ > 4.
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RelocMode rmode_;
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inline void set_modrm(int mod, // reg == 0
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Register rm);
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inline void set_sib(ScaleFactor scale, Register index, Register base);
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inline void set_disp8(int8_t disp);
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inline void set_dispr(int32_t disp, RelocMode rmode);
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inline void set_reg(Register reg) const;
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friend class Assembler;
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};
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// -----------------------------------------------------------------------------
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// A Displacement describes the 32bit immediate field of an instruction which
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// may be used together with a Label in order to refer to a yet unknown code
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// position. Displacements stored in the instruction stream are used to describe
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// the instruction and to chain a list of instructions using the same Label.
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// A Displacement contains 2 different fields:
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//
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// next field: position of next displacement in the chain (0 = end of list)
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// type field: instruction type
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//
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// A next value of null (0) indicates the end of a chain (note that there can
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// be no displacement at position zero, because there is always at least one
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// instruction byte before the displacement).
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//
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// Displacement _data field layout
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//
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// |31.....1|.......0|
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// [ next | type |
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class Displacement BASE_EMBEDDED {
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public:
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enum Type {
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UNCONDITIONAL_JUMP,
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OTHER
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};
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int data() const { return data_; }
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Type type() const { return TypeField::decode(data_); }
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void next(Label* L) const {
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int n = NextField::decode(data_);
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n > 0 ? L->link_to(n) : L->Unuse();
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}
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void link_to(Label* L) { init(L, type()); }
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explicit Displacement(int data) { data_ = data; }
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Displacement(Label* L, Type type) { init(L, type); }
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void print() {
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PrintF("%s (%x) ", (type() == UNCONDITIONAL_JUMP ? "jmp" : "[other]"),
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NextField::decode(data_));
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}
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private:
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int data_;
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class TypeField: public BitField<Type, 0, 1> {};
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class NextField: public BitField<int, 1, 32-1> {};
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void init(Label* L, Type type);
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};
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// CpuFeatures keeps track of which features are supported by the target CPU.
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// Supported features must be enabled by a Scope before use.
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// Example:
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// if (CpuFeatures::IsSupported(SSE2)) {
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// CpuFeatures::Scope fscope(SSE2);
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// // Generate SSE2 floating point code.
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// } else {
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// // Generate standard x87 floating point code.
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// }
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class CpuFeatures : public AllStatic {
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public:
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// Feature flags bit positions. They are mostly based on the CPUID spec.
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// (We assign CPUID itself to one of the currently reserved bits --
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// feel free to change this if needed.)
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enum Feature { SSE2 = 26, CMOV = 15, RDTSC = 4, CPUID = 10 };
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// Detect features of the target CPU. Set safe defaults if the serializer
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// is enabled (snapshots must be portable).
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static void Probe();
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// Check whether a feature is supported by the target CPU.
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static bool IsSupported(Feature f) { return supported_ & (1 << f); }
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// Check whether a feature is currently enabled.
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static bool IsEnabled(Feature f) { return enabled_ & (1 << f); }
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// Enable a specified feature within a scope.
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class Scope BASE_EMBEDDED {
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#ifdef DEBUG
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public:
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explicit Scope(Feature f) {
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ASSERT(CpuFeatures::IsSupported(f));
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old_enabled_ = CpuFeatures::enabled_;
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CpuFeatures::enabled_ |= (1 << f);
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}
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~Scope() { CpuFeatures::enabled_ = old_enabled_; }
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private:
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uint32_t old_enabled_;
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#else
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public:
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explicit Scope(Feature f) {}
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#endif
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};
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private:
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static uint32_t supported_;
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static uint32_t enabled_;
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};
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class Assembler : public Malloced {
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private:
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// The relocation writer's position is kGap bytes below the end of
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// the generated instructions. This leaves enough space for the
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// longest possible ia32 instruction (17 bytes as of 9/26/06) and
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// allows for a single, fast space check per instruction.
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static const int kGap = 32;
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public:
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// Create an assembler. Instructions and relocation information are emitted
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// into a buffer, with the instructions starting from the beginning and the
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// relocation information starting from the end of the buffer. See CodeDesc
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// for a detailed comment on the layout (globals.h).
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//
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// If the provided buffer is NULL, the assembler allocates and grows its own
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// buffer, and buffer_size determines the initial buffer size. The buffer is
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// owned by the assembler and deallocated upon destruction of the assembler.
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//
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// If the provided buffer is not NULL, the assembler uses the provided buffer
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// for code generation and assumes its size to be buffer_size. If the buffer
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// is too small, a fatal error occurs. No deallocation of the buffer is done
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// upon destruction of the assembler.
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Assembler(void* buffer, int buffer_size);
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~Assembler();
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// GetCode emits any pending (non-emitted) code and fills the descriptor
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// desc. GetCode() is idempotent; it returns the same result if no other
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// Assembler functions are invoked inbetween GetCode() calls.
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void GetCode(CodeDesc* desc);
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// Read/Modify the code target in the branch/call instruction at pc.
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inline static Address target_address_at(Address pc);
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inline static void set_target_address_at(Address pc, Address target);
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// Distance between the address of the code target in the call instruction
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// and the return address
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static const int kTargetAddrToReturnAddrDist = kPointerSize;
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// ---------------------------------------------------------------------------
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// Code generation
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//
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// - function names correspond one-to-one to ia32 instruction mnemonics
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// - unless specified otherwise, instructions operate on 32bit operands
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// - instructions on 8bit (byte) operands/registers have a trailing '_b'
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// - instructions on 16bit (word) operands/registers have a trailing '_w'
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// - naming conflicts with C++ keywords are resolved via a trailing '_'
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// NOTE ON INTERFACE: Currently, the interface is not very consistent
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// in the sense that some operations (e.g. mov()) can be called in more
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// the one way to generate the same instruction: The Register argument
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// can in some cases be replaced with an Operand(Register) argument.
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// This should be cleaned up and made more othogonal. The questions
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// is: should we always use Operands instead of Registers where an
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// Operand is possible, or should we have a Register (overloaded) form
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// instead? We must be carefull to make sure that the selected instruction
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// is obvious from the parameters to avoid hard-to-find code generation
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// bugs.
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// Insert the smallest number of nop instructions
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// possible to align the pc offset to a multiple
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// of m. m must be a power of 2.
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void Align(int m);
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// Stack
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void pushad();
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void popad();
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void pushfd();
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void popfd();
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void push(const Immediate& x);
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void push(Register src);
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void push(const Operand& src);
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void pop(Register dst);
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void pop(const Operand& dst);
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// Moves
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void mov_b(Register dst, const Operand& src);
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void mov_b(const Operand& dst, int8_t imm8);
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void mov_b(const Operand& dst, Register src);
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void mov_w(Register dst, const Operand& src);
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void mov_w(const Operand& dst, Register src);
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void mov(Register dst, int32_t imm32);
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void mov(Register dst, Handle<Object> handle);
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void mov(Register dst, const Operand& src);
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void mov(const Operand& dst, const Immediate& x);
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void mov(const Operand& dst, Handle<Object> handle);
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void mov(const Operand& dst, Register src);
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void movsx_b(Register dst, const Operand& src);
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void movsx_w(Register dst, const Operand& src);
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void movzx_b(Register dst, const Operand& src);
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void movzx_w(Register dst, const Operand& src);
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// Conditional moves
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void cmov(Condition cc, Register dst, int32_t imm32);
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void cmov(Condition cc, Register dst, Handle<Object> handle);
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void cmov(Condition cc, Register dst, const Operand& src);
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// Arithmetics
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void adc(Register dst, int32_t imm32);
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void adc(Register dst, const Operand& src);
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void add(Register dst, const Operand& src);
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void add(const Operand& dst, const Immediate& x);
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void and_(Register dst, int32_t imm32);
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void and_(Register dst, const Operand& src);
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void and_(const Operand& src, Register dst);
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void and_(const Operand& dst, const Immediate& x);
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void cmp(Register reg, int32_t imm32);
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void cmp(Register reg, Handle<Object> handle);
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void cmp(Register reg, const Operand& op);
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void cmp(const Operand& op, const Immediate& imm);
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void dec_b(Register dst);
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void dec(Register dst);
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void dec(const Operand& dst);
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void cdq();
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void idiv(Register src);
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void imul(Register dst, const Operand& src);
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void imul(Register dst, Register src, int32_t imm32);
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void inc(Register dst);
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void inc(const Operand& dst);
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void lea(Register dst, const Operand& src);
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void mul(Register src);
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void neg(Register dst);
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void not_(Register dst);
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void or_(Register dst, int32_t imm32);
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void or_(Register dst, const Operand& src);
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void or_(const Operand& dst, Register src);
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void or_(const Operand& dst, const Immediate& x);
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|
void rcl(Register dst, uint8_t imm8);
|
|
|
|
void sar(Register dst, uint8_t imm8);
|
|
void sar(Register dst);
|
|
|
|
void sbb(Register dst, const Operand& src);
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|
|
|
void shld(Register dst, const Operand& src);
|
|
|
|
void shl(Register dst, uint8_t imm8);
|
|
void shl(Register dst);
|
|
|
|
void shrd(Register dst, const Operand& src);
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|
|
|
void shr(Register dst, uint8_t imm8);
|
|
void shr(Register dst);
|
|
|
|
void sub(const Operand& dst, const Immediate& x);
|
|
void sub(Register dst, const Operand& src);
|
|
void sub(const Operand& dst, Register src);
|
|
|
|
void test(Register reg, const Immediate& imm);
|
|
void test(Register reg, const Operand& op);
|
|
void test(const Operand& op, const Immediate& imm);
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|
|
|
void xor_(Register dst, int32_t imm32);
|
|
void xor_(Register dst, const Operand& src);
|
|
void xor_(const Operand& src, Register dst);
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|
void xor_(const Operand& dst, const Immediate& x);
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|
|
|
// Bit operations.
|
|
void bts(const Operand& dst, Register src);
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|
|
|
// Miscellaneous
|
|
void hlt();
|
|
void int3();
|
|
void nop();
|
|
void rdtsc();
|
|
void ret(int imm16);
|
|
void leave();
|
|
|
|
// Label operations & relative jumps (PPUM Appendix D)
|
|
//
|
|
// Takes a branch opcode (cc) and a label (L) and generates
|
|
// either a backward branch or a forward branch and links it
|
|
// to the label fixup chain. Usage:
|
|
//
|
|
// Label L; // unbound label
|
|
// j(cc, &L); // forward branch to unbound label
|
|
// bind(&L); // bind label to the current pc
|
|
// j(cc, &L); // backward branch to bound label
|
|
// bind(&L); // illegal: a label may be bound only once
|
|
//
|
|
// Note: The same Label can be used for forward and backward branches
|
|
// but it may be bound only once.
|
|
|
|
void bind(Label* L); // binds an unbound label L to the current code position
|
|
|
|
// Calls
|
|
void call(Label* L);
|
|
void call(byte* entry, RelocMode rmode);
|
|
void call(const Operand& adr);
|
|
void call(Handle<Code> code, RelocMode rmode);
|
|
|
|
// Jumps
|
|
void jmp(Label* L); // unconditional jump to L
|
|
void jmp(byte* entry, RelocMode rmode);
|
|
void jmp(const Operand& adr);
|
|
void jmp(Handle<Code> code, RelocMode rmode);
|
|
|
|
// Conditional jumps
|
|
void j(Condition cc, Label* L, Hint hint = no_hint);
|
|
void j(Condition cc, byte* entry, RelocMode rmode, Hint hint = no_hint);
|
|
void j(Condition cc, Handle<Code> code, Hint hint = no_hint);
|
|
|
|
// Floating-point operations
|
|
void fld(int i);
|
|
|
|
void fld1();
|
|
void fldz();
|
|
|
|
void fld_s(const Operand& adr);
|
|
void fld_d(const Operand& adr);
|
|
|
|
void fstp_s(const Operand& adr);
|
|
void fstp_d(const Operand& adr);
|
|
|
|
void fild_s(const Operand& adr);
|
|
void fild_d(const Operand& adr);
|
|
|
|
void fist_s(const Operand& adr);
|
|
|
|
void fistp_s(const Operand& adr);
|
|
void fistp_d(const Operand& adr);
|
|
|
|
void fabs();
|
|
void fchs();
|
|
|
|
void fadd(int i);
|
|
void fsub(int i);
|
|
void fmul(int i);
|
|
void fdiv(int i);
|
|
|
|
void fisub_s(const Operand& adr);
|
|
|
|
void faddp(int i = 1);
|
|
void fsubp(int i = 1);
|
|
void fsubrp(int i = 1);
|
|
void fmulp(int i = 1);
|
|
void fdivp(int i = 1);
|
|
void fprem();
|
|
void fprem1();
|
|
|
|
void fxch(int i = 1);
|
|
void fincstp();
|
|
void ffree(int i = 0);
|
|
|
|
void ftst();
|
|
void fucomp(int i);
|
|
void fucompp();
|
|
void fcompp();
|
|
void fnstsw_ax();
|
|
void fwait();
|
|
|
|
void frndint();
|
|
|
|
void sahf();
|
|
|
|
void cpuid();
|
|
|
|
// SSE2 instructions
|
|
void cvttss2si(Register dst, const Operand& src);
|
|
void cvttsd2si(Register dst, const Operand& src);
|
|
|
|
void cvtsi2sd(XMMRegister dst, const Operand& src);
|
|
|
|
void addsd(XMMRegister dst, XMMRegister src);
|
|
void subsd(XMMRegister dst, XMMRegister src);
|
|
void mulsd(XMMRegister dst, XMMRegister src);
|
|
void divsd(XMMRegister dst, XMMRegister src);
|
|
|
|
// Use either movsd or movlpd.
|
|
void movdbl(XMMRegister dst, const Operand& src);
|
|
void movdbl(const Operand& dst, XMMRegister src);
|
|
|
|
// Debugging
|
|
void Print();
|
|
|
|
// Check the code size generated from label to here.
|
|
int SizeOfCodeGeneratedSince(Label* l) { return pc_offset() - l->pos(); }
|
|
|
|
// Mark address of the ExitJSFrame code.
|
|
void RecordJSReturn();
|
|
|
|
// Record a comment relocation entry that can be used by a disassembler.
|
|
// Use --debug_code to enable.
|
|
void RecordComment(const char* msg);
|
|
|
|
void RecordPosition(int pos);
|
|
void RecordStatementPosition(int pos);
|
|
|
|
int pc_offset() const { return pc_ - buffer_; }
|
|
int last_position() const { return last_position_; }
|
|
bool last_position_is_statement() const {
|
|
return last_position_is_statement_;
|
|
}
|
|
|
|
// Check if there is less than kGap bytes available in the buffer.
|
|
// If this is the case, we need to grow the buffer before emitting
|
|
// an instruction or relocation information.
|
|
inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; }
|
|
|
|
// Get the number of bytes available in the buffer.
|
|
inline int available_space() const { return reloc_info_writer.pos() - pc_; }
|
|
|
|
// Avoid overflows for displacements etc.
|
|
static const int kMaximalBufferSize = 512*MB;
|
|
static const int kMinimalBufferSize = 4*KB;
|
|
|
|
protected:
|
|
void movsd(XMMRegister dst, const Operand& src);
|
|
void movsd(const Operand& dst, XMMRegister src);
|
|
|
|
void emit_sse_operand(XMMRegister reg, const Operand& adr);
|
|
void emit_sse_operand(XMMRegister dst, XMMRegister src);
|
|
|
|
|
|
private:
|
|
// Code buffer:
|
|
// The buffer into which code and relocation info are generated.
|
|
byte* buffer_;
|
|
int buffer_size_;
|
|
// True if the assembler owns the buffer, false if buffer is external.
|
|
bool own_buffer_;
|
|
|
|
// code generation
|
|
byte* pc_; // the program counter; moves forward
|
|
RelocInfoWriter reloc_info_writer;
|
|
|
|
// push-pop elimination
|
|
byte* last_pc_;
|
|
|
|
// Jump-to-jump elimination:
|
|
// The last label to be bound to _binding_pos, if unbound.
|
|
Label unbound_label_;
|
|
// The position to which _unbound_label has to be bound, if present.
|
|
int binding_pos_;
|
|
// The position before which jumps cannot be eliminated.
|
|
int last_bound_pos_;
|
|
|
|
// source position information
|
|
int last_position_;
|
|
bool last_position_is_statement_;
|
|
|
|
byte* addr_at(int pos) { return buffer_ + pos; }
|
|
byte byte_at(int pos) { return buffer_[pos]; }
|
|
uint32_t long_at(int pos) {
|
|
return *reinterpret_cast<uint32_t*>(addr_at(pos));
|
|
}
|
|
void long_at_put(int pos, uint32_t x) {
|
|
*reinterpret_cast<uint32_t*>(addr_at(pos)) = x;
|
|
}
|
|
|
|
// code emission
|
|
void GrowBuffer();
|
|
inline void emit(uint32_t x);
|
|
inline void emit(Handle<Object> handle);
|
|
inline void emit(uint32_t x, RelocMode rmode);
|
|
inline void emit(const Immediate& x);
|
|
|
|
// instruction generation
|
|
void emit_arith_b(int op1, int op2, Register dst, int imm8);
|
|
|
|
// Emit a basic arithmetic instruction (i.e. first byte of the family is 0x81)
|
|
// with a given destination expression and an immediate operand. It attempts
|
|
// to use the shortest encoding possible.
|
|
// sel specifies the /n in the modrm byte (see the Intel PRM).
|
|
void emit_arith(int sel, Operand dst, const Immediate& x);
|
|
|
|
void emit_operand(Register reg, const Operand& adr);
|
|
void emit_operand(const Operand& adr, Register reg);
|
|
|
|
void emit_farith(int b1, int b2, int i);
|
|
|
|
// labels
|
|
void print(Label* L);
|
|
void bind_to(Label* L, int pos);
|
|
void link_to(Label* L, Label* appendix);
|
|
|
|
// displacements
|
|
inline Displacement disp_at(Label* L);
|
|
inline void disp_at_put(Label* L, Displacement disp);
|
|
inline void emit_disp(Label* L, Displacement::Type type);
|
|
|
|
// record reloc info for current pc_
|
|
void RecordRelocInfo(RelocMode rmode, intptr_t data = 0);
|
|
|
|
friend class CodePatcher;
|
|
friend class EnsureSpace;
|
|
};
|
|
|
|
|
|
// Helper class that ensures that there is enough space for generating
|
|
// instructions and relocation information. The constructor makes
|
|
// sure that there is enough space and (in debug mode) the destructor
|
|
// checks that we did not generate too much.
|
|
class EnsureSpace BASE_EMBEDDED {
|
|
public:
|
|
explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) {
|
|
if (assembler_->overflow()) assembler_->GrowBuffer();
|
|
#ifdef DEBUG
|
|
space_before_ = assembler_->available_space();
|
|
#endif
|
|
}
|
|
|
|
#ifdef DEBUG
|
|
~EnsureSpace() {
|
|
int bytes_generated = space_before_ - assembler_->available_space();
|
|
ASSERT(bytes_generated < assembler_->kGap);
|
|
}
|
|
#endif
|
|
|
|
private:
|
|
Assembler* assembler_;
|
|
#ifdef DEBUG
|
|
int space_before_;
|
|
#endif
|
|
};
|
|
|
|
} } // namespace v8::internal
|
|
|
|
#endif // V8_ASSEMBLER_IA32_H_
|