b4a219774a
Review URL: http://codereview.chromium.org/112066 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2076 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
276 lines
8.3 KiB
C++
276 lines
8.3 KiB
C++
// Copyright 2009 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#ifndef V8_X64_ASSEMBLER_X64_INL_H_
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#define V8_X64_ASSEMBLER_X64_INL_H_
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#include "cpu.h"
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namespace v8 {
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namespace internal {
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Condition NegateCondition(Condition cc) {
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return static_cast<Condition>(cc ^ 1);
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}
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// -----------------------------------------------------------------------------
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// Implementation of Assembler
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void Assembler::emitl(uint32_t x) {
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Memory::uint32_at(pc_) = x;
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pc_ += sizeof(uint32_t);
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}
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void Assembler::emitq(uint64_t x, RelocInfo::Mode rmode) {
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Memory::uint64_at(pc_) = x;
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RecordRelocInfo(rmode, x);
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}
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// High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
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// REX.W is set. REX.X is cleared.
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void Assembler::emit_rex_64(Register reg, Register rm_reg) {
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emit(0x48 | (reg.code() & 0x8) >> 1 | rm_reg.code() >> 3);
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}
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// The high bit of reg is used for REX.R, the high bit of op's base
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// register is used for REX.B, and the high bit of op's index register
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// is used for REX.X. REX.W is set.
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void Assembler::emit_rex_64(Register reg, const Operand& op) {
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emit(0x48 | (reg.code() & 0x8) >> 1 | op.rex_);
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}
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// High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
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// REX.W is set. REX.X is cleared.
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void Assembler::emit_rex_32(Register reg, Register rm_reg) {
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emit(0x40 | (reg.code() & 0x8) >> 1 | rm_reg.code() >> 3);
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}
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// The high bit of reg is used for REX.R, the high bit of op's base
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// register is used for REX.B, and the high bit of op's index register
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// is used for REX.X. REX.W is cleared.
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void Assembler::emit_rex_32(Register reg, const Operand& op) {
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emit(0x40 | (reg.code() & 0x8) >> 1 | op.rex_);
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}
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// High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
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// REX.W and REX.X are cleared. If no REX bits are set, no byte is emitted.
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void Assembler::emit_optional_rex_32(Register reg, Register rm_reg) {
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byte rex_bits = (reg.code() & 0x8) >> 1 | rm_reg.code() >> 3;
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if (rex_bits) emit(0x40 | rex_bits);
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}
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// The high bit of reg is used for REX.R, the high bit of op's base
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// register is used for REX.B, and the high bit of op's index register
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// is used for REX.X. REX.W is cleared. If no REX bits are set, nothing
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// is emitted.
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void Assembler::emit_optional_rex_32(Register reg, const Operand& op) {
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byte rex_bits = (reg.code() & 0x8) >> 1 | op.rex_;
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if (rex_bits) emit(0x40 | rex_bits);
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}
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void Assembler::set_target_address_at(byte* location, byte* value) {
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UNIMPLEMENTED();
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}
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byte* Assembler::target_address_at(byte* location) {
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UNIMPLEMENTED();
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return NULL;
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}
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// -----------------------------------------------------------------------------
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// Implementation of RelocInfo
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// The modes possibly affected by apply must be in kApplyMask.
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void RelocInfo::apply(int delta) {
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if (rmode_ == RUNTIME_ENTRY || IsCodeTarget(rmode_)) {
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intptr_t* p = reinterpret_cast<intptr_t*>(pc_);
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*p -= delta; // relocate entry
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} else if (rmode_ == JS_RETURN && IsCallInstruction()) {
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// Special handling of js_return when a break point is set (call
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// instruction has been inserted).
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intptr_t* p = reinterpret_cast<intptr_t*>(pc_ + 1);
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*p -= delta; // relocate entry
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} else if (IsInternalReference(rmode_)) {
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// absolute code pointer inside code object moves with the code object.
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intptr_t* p = reinterpret_cast<intptr_t*>(pc_);
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*p += delta; // relocate entry
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}
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}
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Address RelocInfo::target_address() {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == RUNTIME_ENTRY);
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return Assembler::target_address_at(pc_);
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}
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Address RelocInfo::target_address_address() {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == RUNTIME_ENTRY);
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return reinterpret_cast<Address>(pc_);
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}
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void RelocInfo::set_target_address(Address target) {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == RUNTIME_ENTRY);
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Assembler::set_target_address_at(pc_, target);
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}
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Object* RelocInfo::target_object() {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
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return *reinterpret_cast<Object**>(pc_);
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}
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Object** RelocInfo::target_object_address() {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
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return reinterpret_cast<Object**>(pc_);
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}
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Address* RelocInfo::target_reference_address() {
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ASSERT(rmode_ == RelocInfo::EXTERNAL_REFERENCE);
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return reinterpret_cast<Address*>(pc_);
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}
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void RelocInfo::set_target_object(Object* target) {
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ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
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*reinterpret_cast<Object**>(pc_) = target;
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}
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bool RelocInfo::IsCallInstruction() {
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UNIMPLEMENTED(); // IA32 code below.
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return *pc_ == 0xE8;
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}
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Address RelocInfo::call_address() {
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UNIMPLEMENTED(); // IA32 code below.
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ASSERT(IsCallInstruction());
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return Assembler::target_address_at(pc_ + 1);
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}
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void RelocInfo::set_call_address(Address target) {
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UNIMPLEMENTED(); // IA32 code below.
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ASSERT(IsCallInstruction());
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Assembler::set_target_address_at(pc_ + 1, target);
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}
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Object* RelocInfo::call_object() {
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UNIMPLEMENTED(); // IA32 code below.
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ASSERT(IsCallInstruction());
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return *call_object_address();
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}
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void RelocInfo::set_call_object(Object* target) {
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UNIMPLEMENTED(); // IA32 code below.
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ASSERT(IsCallInstruction());
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*call_object_address() = target;
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}
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Object** RelocInfo::call_object_address() {
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UNIMPLEMENTED(); // IA32 code below.
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ASSERT(IsCallInstruction());
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return reinterpret_cast<Object**>(pc_ + 1);
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}
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// -----------------------------------------------------------------------------
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// Implementation of Operand
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Operand::Operand(Register base, int32_t disp) {
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len_ = 1;
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if (base.is(rsp) || base.is(r12)) {
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// SIB byte is needed to encode (rsp + offset) or (r12 + offset).
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set_sib(times_1, rsp, base);
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}
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if (disp == 0 && !base.is(rbp) && !base.is(r13)) {
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set_modrm(0, rsp);
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} else if (is_int8(disp)) {
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set_modrm(1, base);
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set_disp8(disp);
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} else {
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set_modrm(2, base);
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set_disp32(disp);
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}
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}
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void Operand::set_modrm(int mod, Register rm) {
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ASSERT((mod & -4) == 0);
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buf_[0] = mod << 6 | (rm.code() & 0x7);
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// Set REX.B to the high bit of rm.code().
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rex_ |= (rm.code() >> 3);
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}
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void Operand::set_sib(ScaleFactor scale, Register index, Register base) {
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ASSERT(len_ == 1);
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ASSERT((scale & -4) == 0);
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// Use SIB with no index register only for base rsp or r12.
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ASSERT(!index.is(rsp) || base.is(rsp) || base.is(r12));
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buf_[1] = scale << 6 | (index.code() & 0x7) << 3 | (base.code() & 0x7);
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rex_ |= (index.code() >> 3) << 1 | base.code() >> 3;
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len_ = 2;
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}
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void Operand::set_disp8(int disp) {
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ASSERT(is_int8(disp));
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ASSERT(len_ == 1 || len_ == 2);
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int8_t* p = reinterpret_cast<int8_t*>(&buf_[len_]);
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*p = disp;
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len_ += sizeof(int8_t);
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}
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void Operand::set_disp32(int disp) {
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ASSERT(len_ == 1 || len_ == 2);
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int32_t* p = reinterpret_cast<int32_t*>(&buf_[len_]);
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*p = disp;
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len_ += sizeof(int32_t);
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}
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} } // namespace v8::internal
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#endif // V8_X64_ASSEMBLER_X64_INL_H_
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