a335f2aeed
This replaces all typedefs that define types and not functions by the equivalent "using" declaration. This was done mostly automatically using this command: ag -l '\btypedef\b' src test | xargs -L1 \ perl -i -p0e 's/typedef ([^*;{}]+) (\w+);/using \2 = \1;/sg' Patchset 2 then adds some manual changes for typedefs for pointer types, where the regular expression did not match. R=mstarzinger@chromium.org TBR=yangguo@chromium.org, jarin@chromium.org Bug: v8:9183 Change-Id: I6f6ee28d1793b7ac34a58f980b94babc21874b78 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1631409 Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#61849}
1427 lines
53 KiB
C++
1427 lines
53 KiB
C++
// Copyright 2014 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file
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#include "test/unittests/compiler/backend/instruction-selector-unittest.h"
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#include "src/objects/objects-inl.h"
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namespace v8 {
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namespace internal {
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namespace compiler {
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namespace {
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template <typename T>
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struct MachInst {
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T constructor;
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const char* constructor_name;
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ArchOpcode arch_opcode;
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MachineType machine_type;
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};
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template <typename T>
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std::ostream& operator<<(std::ostream& os, const MachInst<T>& mi) {
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return os << mi.constructor_name;
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}
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using MachInst1 = MachInst<Node* (RawMachineAssembler::*)(Node*)>;
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using MachInst2 = MachInst<Node* (RawMachineAssembler::*)(Node*, Node*)>;
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// To avoid duplicated code IntCmp helper structure
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// is created. It contains MachInst2 with two nodes and expected_size
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// because different cmp instructions have different size.
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struct IntCmp {
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MachInst2 mi;
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uint32_t expected_size;
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};
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struct FPCmp {
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MachInst2 mi;
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FlagsCondition cond;
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};
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const FPCmp kFPCmpInstructions[] = {
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{{&RawMachineAssembler::Float64Equal, "Float64Equal", kMipsCmpD,
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MachineType::Float64()},
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kEqual},
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{{&RawMachineAssembler::Float64LessThan, "Float64LessThan", kMipsCmpD,
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MachineType::Float64()},
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kUnsignedLessThan},
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{{&RawMachineAssembler::Float64LessThanOrEqual, "Float64LessThanOrEqual",
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kMipsCmpD, MachineType::Float64()},
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kUnsignedLessThanOrEqual},
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{{&RawMachineAssembler::Float64GreaterThan, "Float64GreaterThan", kMipsCmpD,
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MachineType::Float64()},
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kUnsignedLessThan},
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{{&RawMachineAssembler::Float64GreaterThanOrEqual,
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"Float64GreaterThanOrEqual", kMipsCmpD, MachineType::Float64()},
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kUnsignedLessThanOrEqual}};
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struct Conversion {
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// The machine_type field in MachInst1 represents the destination type.
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MachInst1 mi;
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MachineType src_machine_type;
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};
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// ----------------------------------------------------------------------------
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// Logical instructions.
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// ----------------------------------------------------------------------------
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const MachInst2 kLogicalInstructions[] = {
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{&RawMachineAssembler::WordAnd, "WordAnd", kMipsAnd, MachineType::Int16()},
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{&RawMachineAssembler::WordOr, "WordOr", kMipsOr, MachineType::Int16()},
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{&RawMachineAssembler::WordXor, "WordXor", kMipsXor, MachineType::Int16()},
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{&RawMachineAssembler::Word32And, "Word32And", kMipsAnd,
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MachineType::Int32()},
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{&RawMachineAssembler::Word32Or, "Word32Or", kMipsOr, MachineType::Int32()},
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{&RawMachineAssembler::Word32Xor, "Word32Xor", kMipsXor,
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MachineType::Int32()}};
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// ----------------------------------------------------------------------------
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// Shift instructions.
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// ----------------------------------------------------------------------------
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const MachInst2 kShiftInstructions[] = {
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{&RawMachineAssembler::WordShl, "WordShl", kMipsShl, MachineType::Int16()},
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{&RawMachineAssembler::WordShr, "WordShr", kMipsShr, MachineType::Int16()},
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{&RawMachineAssembler::WordSar, "WordSar", kMipsSar, MachineType::Int16()},
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{&RawMachineAssembler::WordRor, "WordRor", kMipsRor, MachineType::Int16()},
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{&RawMachineAssembler::Word32Shl, "Word32Shl", kMipsShl,
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MachineType::Int32()},
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{&RawMachineAssembler::Word32Shr, "Word32Shr", kMipsShr,
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MachineType::Int32()},
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{&RawMachineAssembler::Word32Sar, "Word32Sar", kMipsSar,
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MachineType::Int32()},
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{&RawMachineAssembler::Word32Ror, "Word32Ror", kMipsRor,
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MachineType::Int32()}};
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// ----------------------------------------------------------------------------
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// MUL/DIV instructions.
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// ----------------------------------------------------------------------------
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const MachInst2 kMulDivInstructions[] = {
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{&RawMachineAssembler::Int32Mul, "Int32Mul", kMipsMul,
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MachineType::Int32()},
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{&RawMachineAssembler::Int32Div, "Int32Div", kMipsDiv,
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MachineType::Int32()},
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{&RawMachineAssembler::Uint32Div, "Uint32Div", kMipsDivU,
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MachineType::Uint32()},
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{&RawMachineAssembler::Float64Mul, "Float64Mul", kMipsMulD,
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MachineType::Float64()},
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{&RawMachineAssembler::Float64Div, "Float64Div", kMipsDivD,
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MachineType::Float64()}};
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// ----------------------------------------------------------------------------
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// MOD instructions.
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// ----------------------------------------------------------------------------
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const MachInst2 kModInstructions[] = {
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{&RawMachineAssembler::Int32Mod, "Int32Mod", kMipsMod,
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MachineType::Int32()},
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{&RawMachineAssembler::Uint32Mod, "Int32UMod", kMipsModU,
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MachineType::Int32()},
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{&RawMachineAssembler::Float64Mod, "Float64Mod", kMipsModD,
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MachineType::Float64()}};
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// ----------------------------------------------------------------------------
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// Arithmetic FPU instructions.
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// ----------------------------------------------------------------------------
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const MachInst2 kFPArithInstructions[] = {
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{&RawMachineAssembler::Float64Add, "Float64Add", kMipsAddD,
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MachineType::Float64()},
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{&RawMachineAssembler::Float64Sub, "Float64Sub", kMipsSubD,
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MachineType::Float64()}};
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// ----------------------------------------------------------------------------
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// IntArithTest instructions, two nodes.
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// ----------------------------------------------------------------------------
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const MachInst2 kAddSubInstructions[] = {
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{&RawMachineAssembler::Int32Add, "Int32Add", kMipsAdd,
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MachineType::Int32()},
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{&RawMachineAssembler::Int32Sub, "Int32Sub", kMipsSub,
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MachineType::Int32()},
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{&RawMachineAssembler::Int32AddWithOverflow, "Int32AddWithOverflow",
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kMipsAddOvf, MachineType::Int32()},
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{&RawMachineAssembler::Int32SubWithOverflow, "Int32SubWithOverflow",
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kMipsSubOvf, MachineType::Int32()}};
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// ----------------------------------------------------------------------------
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// IntArithTest instructions, one node.
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// ----------------------------------------------------------------------------
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const MachInst1 kAddSubOneInstructions[] = {
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{&RawMachineAssembler::Int32Neg, "Int32Neg", kMipsSub,
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MachineType::Int32()},
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// TODO(dusmil): check this ...
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// {&RawMachineAssembler::WordEqual , "WordEqual" , kMipsTst,
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// MachineType::Int32()}
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};
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// ----------------------------------------------------------------------------
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// Arithmetic compare instructions.
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// ----------------------------------------------------------------------------
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const IntCmp kCmpInstructions[] = {
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{{&RawMachineAssembler::WordEqual, "WordEqual", kMipsCmp,
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MachineType::Int16()},
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1U},
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{{&RawMachineAssembler::WordNotEqual, "WordNotEqual", kMipsCmp,
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MachineType::Int16()},
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1U},
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{{&RawMachineAssembler::Word32Equal, "Word32Equal", kMipsCmp,
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MachineType::Int32()},
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1U},
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{{&RawMachineAssembler::Word32NotEqual, "Word32NotEqual", kMipsCmp,
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MachineType::Int32()},
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1U},
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{{&RawMachineAssembler::Int32LessThan, "Int32LessThan", kMipsCmp,
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MachineType::Int32()},
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1U},
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{{&RawMachineAssembler::Int32LessThanOrEqual, "Int32LessThanOrEqual",
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kMipsCmp, MachineType::Int32()},
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1U},
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{{&RawMachineAssembler::Int32GreaterThan, "Int32GreaterThan", kMipsCmp,
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MachineType::Int32()},
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1U},
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{{&RawMachineAssembler::Int32GreaterThanOrEqual, "Int32GreaterThanOrEqual",
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kMipsCmp, MachineType::Int32()},
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1U},
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{{&RawMachineAssembler::Uint32LessThan, "Uint32LessThan", kMipsCmp,
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MachineType::Uint32()},
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1U},
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{{&RawMachineAssembler::Uint32LessThanOrEqual, "Uint32LessThanOrEqual",
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kMipsCmp, MachineType::Uint32()},
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1U}};
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// ----------------------------------------------------------------------------
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// Conversion instructions.
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// ----------------------------------------------------------------------------
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const Conversion kConversionInstructions[] = {
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// Conversion instructions are related to machine_operator.h:
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// FPU conversions:
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// Convert representation of integers between float64 and int32/uint32.
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// The precise rounding mode and handling of out of range inputs are *not*
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// defined for these operators, since they are intended only for use with
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// integers.
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// mips instruction: cvt_d_w
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{{&RawMachineAssembler::ChangeInt32ToFloat64, "ChangeInt32ToFloat64",
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kMipsCvtDW, MachineType::Float64()},
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MachineType::Int32()},
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// mips instruction: cvt_d_uw
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{{&RawMachineAssembler::ChangeUint32ToFloat64, "ChangeUint32ToFloat64",
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kMipsCvtDUw, MachineType::Float64()},
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MachineType::Int32()},
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// mips instruction: trunc_w_d
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{{&RawMachineAssembler::ChangeFloat64ToInt32, "ChangeFloat64ToInt32",
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kMipsTruncWD, MachineType::Float64()},
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MachineType::Int32()},
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// mips instruction: trunc_uw_d
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{{&RawMachineAssembler::ChangeFloat64ToUint32, "ChangeFloat64ToUint32",
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kMipsTruncUwD, MachineType::Float64()},
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MachineType::Int32()}};
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const Conversion kFloat64RoundInstructions[] = {
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{{&RawMachineAssembler::Float64RoundUp, "Float64RoundUp", kMipsCeilWD,
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MachineType::Int32()},
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MachineType::Float64()},
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{{&RawMachineAssembler::Float64RoundDown, "Float64RoundDown", kMipsFloorWD,
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MachineType::Int32()},
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MachineType::Float64()},
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{{&RawMachineAssembler::Float64RoundTiesEven, "Float64RoundTiesEven",
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kMipsRoundWD, MachineType::Int32()},
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MachineType::Float64()},
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{{&RawMachineAssembler::Float64RoundTruncate, "Float64RoundTruncate",
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kMipsTruncWD, MachineType::Int32()},
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MachineType::Float64()}};
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const Conversion kFloat32RoundInstructions[] = {
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{{&RawMachineAssembler::Float32RoundUp, "Float32RoundUp", kMipsCeilWS,
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MachineType::Int32()},
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MachineType::Float32()},
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{{&RawMachineAssembler::Float32RoundDown, "Float32RoundDown", kMipsFloorWS,
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MachineType::Int32()},
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MachineType::Float32()},
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{{&RawMachineAssembler::Float32RoundTiesEven, "Float32RoundTiesEven",
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kMipsRoundWS, MachineType::Int32()},
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MachineType::Float32()},
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{{&RawMachineAssembler::Float32RoundTruncate, "Float32RoundTruncate",
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kMipsTruncWS, MachineType::Int32()},
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MachineType::Float32()}};
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} // namespace
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using InstructionSelectorFPCmpTest = InstructionSelectorTestWithParam<FPCmp>;
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TEST_P(InstructionSelectorFPCmpTest, Parameter) {
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const FPCmp cmp = GetParam();
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StreamBuilder m(this, MachineType::Int32(), cmp.mi.machine_type,
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cmp.mi.machine_type);
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m.Return((m.*cmp.mi.constructor)(m.Parameter(0), m.Parameter(1)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(cmp.mi.arch_opcode, s[0]->arch_opcode());
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EXPECT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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EXPECT_EQ(kFlags_set, s[0]->flags_mode());
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EXPECT_EQ(cmp.cond, s[0]->flags_condition());
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}
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INSTANTIATE_TEST_SUITE_P(InstructionSelectorTest, InstructionSelectorFPCmpTest,
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::testing::ValuesIn(kFPCmpInstructions));
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// ----------------------------------------------------------------------------
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// Arithmetic compare instructions integers.
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// ----------------------------------------------------------------------------
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using InstructionSelectorCmpTest = InstructionSelectorTestWithParam<IntCmp>;
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TEST_P(InstructionSelectorCmpTest, Parameter) {
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const IntCmp cmp = GetParam();
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const MachineType type = cmp.mi.machine_type;
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StreamBuilder m(this, type, type, type);
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m.Return((m.*cmp.mi.constructor)(m.Parameter(0), m.Parameter(1)));
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Stream s = m.Build();
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ASSERT_EQ(cmp.expected_size, s.size());
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EXPECT_EQ(cmp.mi.arch_opcode, s[0]->arch_opcode());
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EXPECT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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INSTANTIATE_TEST_SUITE_P(InstructionSelectorTest, InstructionSelectorCmpTest,
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::testing::ValuesIn(kCmpInstructions));
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// ----------------------------------------------------------------------------
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// Shift instructions.
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// ----------------------------------------------------------------------------
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using InstructionSelectorShiftTest =
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InstructionSelectorTestWithParam<MachInst2>;
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TEST_P(InstructionSelectorShiftTest, Immediate) {
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const MachInst2 dpi = GetParam();
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const MachineType type = dpi.machine_type;
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TRACED_FORRANGE(int32_t, imm, 0,
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((1 << ElementSizeLog2Of(type.representation())) * 8) - 1) {
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StreamBuilder m(this, type, type);
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m.Return((m.*dpi.constructor)(m.Parameter(0), m.Int32Constant(imm)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(dpi.arch_opcode, s[0]->arch_opcode());
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EXPECT_EQ(2U, s[0]->InputCount());
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EXPECT_TRUE(s[0]->InputAt(1)->IsImmediate());
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EXPECT_EQ(imm, s.ToInt32(s[0]->InputAt(1)));
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EXPECT_EQ(1U, s[0]->OutputCount());
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}
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}
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INSTANTIATE_TEST_SUITE_P(InstructionSelectorTest, InstructionSelectorShiftTest,
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::testing::ValuesIn(kShiftInstructions));
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TEST_F(InstructionSelectorTest, Word32ShrWithWord32AndWithImmediate) {
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// The available shift operand range is `0 <= imm < 32`, but we also test
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// that immediates outside this range are handled properly (modulo-32).
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TRACED_FORRANGE(int32_t, shift, -32, 63) {
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int32_t lsb = shift & 0x1F;
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TRACED_FORRANGE(int32_t, width, 1, 32 - lsb) {
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uint32_t jnk = rng()->NextInt();
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jnk = (lsb > 0) ? (jnk >> (32 - lsb)) : 0;
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uint32_t msk = ((0xFFFFFFFFu >> (32 - width)) << lsb) | jnk;
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StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
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m.Return(m.Word32Shr(m.Word32And(m.Parameter(0), m.Int32Constant(msk)),
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m.Int32Constant(shift)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMipsExt, s[0]->arch_opcode());
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ASSERT_EQ(3U, s[0]->InputCount());
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EXPECT_EQ(lsb, s.ToInt32(s[0]->InputAt(1)));
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EXPECT_EQ(width, s.ToInt32(s[0]->InputAt(2)));
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}
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}
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TRACED_FORRANGE(int32_t, shift, -32, 63) {
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int32_t lsb = shift & 0x1F;
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TRACED_FORRANGE(int32_t, width, 1, 32 - lsb) {
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uint32_t jnk = rng()->NextInt();
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jnk = (lsb > 0) ? (jnk >> (32 - lsb)) : 0;
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uint32_t msk = ((0xFFFFFFFFu >> (32 - width)) << lsb) | jnk;
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StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
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m.Return(m.Word32Shr(m.Word32And(m.Int32Constant(msk), m.Parameter(0)),
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m.Int32Constant(shift)));
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMipsExt, s[0]->arch_opcode());
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ASSERT_EQ(3U, s[0]->InputCount());
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EXPECT_EQ(lsb, s.ToInt32(s[0]->InputAt(1)));
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EXPECT_EQ(width, s.ToInt32(s[0]->InputAt(2)));
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}
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}
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}
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TEST_F(InstructionSelectorTest, Word32ShlWithWord32And) {
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TRACED_FORRANGE(int32_t, shift, 0, 30) {
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StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
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Node* const p0 = m.Parameter(0);
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Node* const r =
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m.Word32Shl(m.Word32And(p0, m.Int32Constant((1 << (31 - shift)) - 1)),
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m.Int32Constant(shift + 1));
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m.Return(r);
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMipsShl, s[0]->arch_opcode());
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ASSERT_EQ(2U, s[0]->InputCount());
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EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
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ASSERT_EQ(1U, s[0]->OutputCount());
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EXPECT_EQ(s.ToVreg(r), s.ToVreg(s[0]->Output()));
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}
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}
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TEST_F(InstructionSelectorTest, Word32SarWithWord32Shl) {
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if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
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{
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StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
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Node* const p0 = m.Parameter(0);
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Node* const r = m.Word32Sar(m.Word32Shl(p0, m.Int32Constant(24)),
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m.Int32Constant(24));
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m.Return(r);
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMipsSeb, s[0]->arch_opcode());
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ASSERT_EQ(1U, s[0]->InputCount());
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EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
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ASSERT_EQ(1U, s[0]->OutputCount());
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EXPECT_EQ(s.ToVreg(r), s.ToVreg(s[0]->Output()));
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}
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{
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StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
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Node* const p0 = m.Parameter(0);
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Node* const r = m.Word32Sar(m.Word32Shl(p0, m.Int32Constant(16)),
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m.Int32Constant(16));
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m.Return(r);
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Stream s = m.Build();
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ASSERT_EQ(1U, s.size());
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EXPECT_EQ(kMipsSeh, s[0]->arch_opcode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(s.ToVreg(r), s.ToVreg(s[0]->Output()));
|
|
}
|
|
}
|
|
}
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Logical instructions.
|
|
// ----------------------------------------------------------------------------
|
|
|
|
using InstructionSelectorLogicalTest =
|
|
InstructionSelectorTestWithParam<MachInst2>;
|
|
|
|
TEST_P(InstructionSelectorLogicalTest, Parameter) {
|
|
const MachInst2 dpi = GetParam();
|
|
const MachineType type = dpi.machine_type;
|
|
StreamBuilder m(this, type, type, type);
|
|
m.Return((m.*dpi.constructor)(m.Parameter(0), m.Parameter(1)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(dpi.arch_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
|
|
INSTANTIATE_TEST_SUITE_P(InstructionSelectorTest,
|
|
InstructionSelectorLogicalTest,
|
|
::testing::ValuesIn(kLogicalInstructions));
|
|
|
|
TEST_F(InstructionSelectorTest, Word32XorMinusOneWithParameter) {
|
|
{
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
m.Return(m.Word32Xor(m.Parameter(0), m.Int32Constant(-1)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsNor, s[0]->arch_opcode());
|
|
EXPECT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
{
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
m.Return(m.Word32Xor(m.Int32Constant(-1), m.Parameter(0)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsNor, s[0]->arch_opcode());
|
|
EXPECT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Word32XorMinusOneWithWord32Or) {
|
|
{
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
m.Return(m.Word32Xor(m.Word32Or(m.Parameter(0), m.Parameter(0)),
|
|
m.Int32Constant(-1)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsNor, s[0]->arch_opcode());
|
|
EXPECT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
{
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
m.Return(m.Word32Xor(m.Int32Constant(-1),
|
|
m.Word32Or(m.Parameter(0), m.Parameter(0))));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsNor, s[0]->arch_opcode());
|
|
EXPECT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Word32AndWithImmediateWithWord32Shr) {
|
|
// The available shift operand range is `0 <= imm < 32`, but we also test
|
|
// that immediates outside this range are handled properly (modulo-32).
|
|
TRACED_FORRANGE(int32_t, shift, -32, 63) {
|
|
int32_t lsb = shift & 0x1F;
|
|
TRACED_FORRANGE(int32_t, width, 1, 31) {
|
|
uint32_t msk = (1 << width) - 1;
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
m.Return(m.Word32And(m.Word32Shr(m.Parameter(0), m.Int32Constant(shift)),
|
|
m.Int32Constant(msk)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsExt, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(lsb, s.ToInt32(s[0]->InputAt(1)));
|
|
int32_t actual_width = (lsb + width > 32) ? (32 - lsb) : width;
|
|
EXPECT_EQ(actual_width, s.ToInt32(s[0]->InputAt(2)));
|
|
}
|
|
}
|
|
TRACED_FORRANGE(int32_t, shift, -32, 63) {
|
|
int32_t lsb = shift & 0x1F;
|
|
TRACED_FORRANGE(int32_t, width, 1, 31) {
|
|
uint32_t msk = (1 << width) - 1;
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
m.Return(
|
|
m.Word32And(m.Int32Constant(msk),
|
|
m.Word32Shr(m.Parameter(0), m.Int32Constant(shift))));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsExt, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(lsb, s.ToInt32(s[0]->InputAt(1)));
|
|
int32_t actual_width = (lsb + width > 32) ? (32 - lsb) : width;
|
|
EXPECT_EQ(actual_width, s.ToInt32(s[0]->InputAt(2)));
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Word32AndToClearBits) {
|
|
TRACED_FORRANGE(int32_t, shift, 1, 31) {
|
|
int32_t mask = ~((1 << shift) - 1);
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
m.Return(m.Word32And(m.Parameter(0), m.Int32Constant(mask)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsIns, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(0, s.ToInt32(s[0]->InputAt(1)));
|
|
EXPECT_EQ(shift, s.ToInt32(s[0]->InputAt(2)));
|
|
}
|
|
TRACED_FORRANGE(int32_t, shift, 1, 31) {
|
|
int32_t mask = ~((1 << shift) - 1);
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
m.Return(m.Word32And(m.Int32Constant(mask), m.Parameter(0)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsIns, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(0, s.ToInt32(s[0]->InputAt(1)));
|
|
EXPECT_EQ(shift, s.ToInt32(s[0]->InputAt(2)));
|
|
}
|
|
}
|
|
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// MUL/DIV instructions.
|
|
// ----------------------------------------------------------------------------
|
|
|
|
using InstructionSelectorMulDivTest =
|
|
InstructionSelectorTestWithParam<MachInst2>;
|
|
|
|
TEST_P(InstructionSelectorMulDivTest, Parameter) {
|
|
const MachInst2 dpi = GetParam();
|
|
const MachineType type = dpi.machine_type;
|
|
StreamBuilder m(this, type, type, type);
|
|
m.Return((m.*dpi.constructor)(m.Parameter(0), m.Parameter(1)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(dpi.arch_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
|
|
INSTANTIATE_TEST_SUITE_P(InstructionSelectorTest, InstructionSelectorMulDivTest,
|
|
::testing::ValuesIn(kMulDivInstructions));
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// MOD instructions.
|
|
// ----------------------------------------------------------------------------
|
|
|
|
using InstructionSelectorModTest = InstructionSelectorTestWithParam<MachInst2>;
|
|
|
|
TEST_P(InstructionSelectorModTest, Parameter) {
|
|
const MachInst2 dpi = GetParam();
|
|
const MachineType type = dpi.machine_type;
|
|
StreamBuilder m(this, type, type, type);
|
|
m.Return((m.*dpi.constructor)(m.Parameter(0), m.Parameter(1)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(dpi.arch_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
|
|
INSTANTIATE_TEST_SUITE_P(InstructionSelectorTest, InstructionSelectorModTest,
|
|
::testing::ValuesIn(kModInstructions));
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Floating point instructions.
|
|
// ----------------------------------------------------------------------------
|
|
|
|
using InstructionSelectorFPArithTest =
|
|
InstructionSelectorTestWithParam<MachInst2>;
|
|
|
|
TEST_P(InstructionSelectorFPArithTest, Parameter) {
|
|
const MachInst2 fpa = GetParam();
|
|
StreamBuilder m(this, fpa.machine_type, fpa.machine_type, fpa.machine_type);
|
|
m.Return((m.*fpa.constructor)(m.Parameter(0), m.Parameter(1)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(fpa.arch_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
|
|
INSTANTIATE_TEST_SUITE_P(InstructionSelectorTest,
|
|
InstructionSelectorFPArithTest,
|
|
::testing::ValuesIn(kFPArithInstructions));
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Integer arithmetic.
|
|
// ----------------------------------------------------------------------------
|
|
|
|
using InstructionSelectorIntArithTwoTest =
|
|
InstructionSelectorTestWithParam<MachInst2>;
|
|
|
|
TEST_P(InstructionSelectorIntArithTwoTest, Parameter) {
|
|
const MachInst2 intpa = GetParam();
|
|
StreamBuilder m(this, intpa.machine_type, intpa.machine_type,
|
|
intpa.machine_type);
|
|
m.Return((m.*intpa.constructor)(m.Parameter(0), m.Parameter(1)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(intpa.arch_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
|
|
INSTANTIATE_TEST_SUITE_P(InstructionSelectorTest,
|
|
InstructionSelectorIntArithTwoTest,
|
|
::testing::ValuesIn(kAddSubInstructions));
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// One node.
|
|
// ----------------------------------------------------------------------------
|
|
|
|
using InstructionSelectorIntArithOneTest =
|
|
InstructionSelectorTestWithParam<MachInst1>;
|
|
|
|
TEST_P(InstructionSelectorIntArithOneTest, Parameter) {
|
|
const MachInst1 intpa = GetParam();
|
|
StreamBuilder m(this, intpa.machine_type, intpa.machine_type,
|
|
intpa.machine_type);
|
|
m.Return((m.*intpa.constructor)(m.Parameter(0)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(intpa.arch_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
|
|
INSTANTIATE_TEST_SUITE_P(InstructionSelectorTest,
|
|
InstructionSelectorIntArithOneTest,
|
|
::testing::ValuesIn(kAddSubOneInstructions));
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Conversions.
|
|
// ----------------------------------------------------------------------------
|
|
|
|
using InstructionSelectorConversionTest =
|
|
InstructionSelectorTestWithParam<Conversion>;
|
|
|
|
TEST_P(InstructionSelectorConversionTest, Parameter) {
|
|
const Conversion conv = GetParam();
|
|
StreamBuilder m(this, conv.mi.machine_type, conv.src_machine_type);
|
|
m.Return((m.*conv.mi.constructor)(m.Parameter(0)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(conv.mi.arch_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
|
|
INSTANTIATE_TEST_SUITE_P(InstructionSelectorTest,
|
|
InstructionSelectorConversionTest,
|
|
::testing::ValuesIn(kConversionInstructions));
|
|
|
|
using CombineChangeFloat64ToInt32WithRoundFloat64 =
|
|
InstructionSelectorTestWithParam<Conversion>;
|
|
|
|
TEST_P(CombineChangeFloat64ToInt32WithRoundFloat64, Parameter) {
|
|
{
|
|
const Conversion conv = GetParam();
|
|
StreamBuilder m(this, conv.mi.machine_type, conv.src_machine_type);
|
|
m.Return(m.ChangeFloat64ToInt32((m.*conv.mi.constructor)(m.Parameter(0))));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(conv.mi.arch_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_None, s[0]->addressing_mode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
}
|
|
|
|
INSTANTIATE_TEST_SUITE_P(InstructionSelectorTest,
|
|
CombineChangeFloat64ToInt32WithRoundFloat64,
|
|
::testing::ValuesIn(kFloat64RoundInstructions));
|
|
|
|
using CombineChangeFloat32ToInt32WithRoundFloat32 =
|
|
InstructionSelectorTestWithParam<Conversion>;
|
|
|
|
TEST_P(CombineChangeFloat32ToInt32WithRoundFloat32, Parameter) {
|
|
{
|
|
const Conversion conv = GetParam();
|
|
StreamBuilder m(this, conv.mi.machine_type, conv.src_machine_type);
|
|
m.Return(m.ChangeFloat64ToInt32(
|
|
m.ChangeFloat32ToFloat64((m.*conv.mi.constructor)(m.Parameter(0)))));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(conv.mi.arch_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_None, s[0]->addressing_mode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
}
|
|
|
|
INSTANTIATE_TEST_SUITE_P(InstructionSelectorTest,
|
|
CombineChangeFloat32ToInt32WithRoundFloat32,
|
|
::testing::ValuesIn(kFloat32RoundInstructions));
|
|
|
|
TEST_F(InstructionSelectorTest, ChangeFloat64ToInt32OfChangeFloat32ToFloat64) {
|
|
{
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Float32());
|
|
m.Return(m.ChangeFloat64ToInt32(m.ChangeFloat32ToFloat64(m.Parameter(0))));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsTruncWS, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_None, s[0]->addressing_mode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest,
|
|
TruncateFloat64ToFloat32OfChangeInt32ToFloat64) {
|
|
{
|
|
StreamBuilder m(this, MachineType::Float32(), MachineType::Int32());
|
|
m.Return(
|
|
m.TruncateFloat64ToFloat32(m.ChangeInt32ToFloat64(m.Parameter(0))));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsCvtSW, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_None, s[0]->addressing_mode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
}
|
|
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Loads and stores.
|
|
// ----------------------------------------------------------------------------
|
|
|
|
namespace {
|
|
|
|
struct MemoryAccess {
|
|
MachineType type;
|
|
ArchOpcode load_opcode;
|
|
ArchOpcode store_opcode;
|
|
};
|
|
|
|
|
|
static const MemoryAccess kMemoryAccesses[] = {
|
|
{MachineType::Int8(), kMipsLb, kMipsSb},
|
|
{MachineType::Uint8(), kMipsLbu, kMipsSb},
|
|
{MachineType::Int16(), kMipsLh, kMipsSh},
|
|
{MachineType::Uint16(), kMipsLhu, kMipsSh},
|
|
{MachineType::Int32(), kMipsLw, kMipsSw},
|
|
{MachineType::Float32(), kMipsLwc1, kMipsSwc1},
|
|
{MachineType::Float64(), kMipsLdc1, kMipsSdc1}};
|
|
|
|
|
|
struct MemoryAccessImm {
|
|
MachineType type;
|
|
ArchOpcode load_opcode;
|
|
ArchOpcode store_opcode;
|
|
bool (InstructionSelectorTest::Stream::*val_predicate)(
|
|
const InstructionOperand*) const;
|
|
const int32_t immediates[40];
|
|
};
|
|
|
|
|
|
std::ostream& operator<<(std::ostream& os, const MemoryAccessImm& acc) {
|
|
return os << acc.type;
|
|
}
|
|
|
|
|
|
struct MemoryAccessImm1 {
|
|
MachineType type;
|
|
ArchOpcode load_opcode;
|
|
ArchOpcode store_opcode;
|
|
bool (InstructionSelectorTest::Stream::*val_predicate)(
|
|
const InstructionOperand*) const;
|
|
const int32_t immediates[5];
|
|
};
|
|
|
|
|
|
std::ostream& operator<<(std::ostream& os, const MemoryAccessImm1& acc) {
|
|
return os << acc.type;
|
|
}
|
|
|
|
struct MemoryAccessImm2 {
|
|
MachineType type;
|
|
ArchOpcode store_opcode;
|
|
ArchOpcode store_opcode_unaligned;
|
|
bool (InstructionSelectorTest::Stream::*val_predicate)(
|
|
const InstructionOperand*) const;
|
|
const int32_t immediates[40];
|
|
};
|
|
|
|
std::ostream& operator<<(std::ostream& os, const MemoryAccessImm2& acc) {
|
|
return os << acc.type;
|
|
}
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Loads and stores immediate values.
|
|
// ----------------------------------------------------------------------------
|
|
|
|
|
|
const MemoryAccessImm kMemoryAccessesImm[] = {
|
|
{MachineType::Int8(),
|
|
kMipsLb,
|
|
kMipsSb,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-4095, -3340, -3231, -3224, -3088, -1758, -1203, -123, -117, -91, -89,
|
|
-87, -86, -82, -44, -23, -3, 0, 7, 10, 39, 52, 69, 71, 91, 92, 107, 109,
|
|
115, 124, 286, 655, 1362, 1569, 2587, 3067, 3096, 3462, 3510, 4095}},
|
|
{MachineType::Uint8(),
|
|
kMipsLbu,
|
|
kMipsSb,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-4095, -3340, -3231, -3224, -3088, -1758, -1203, -123, -117, -91, -89,
|
|
-87, -86, -82, -44, -23, -3, 0, 7, 10, 39, 52, 69, 71, 91, 92, 107, 109,
|
|
115, 124, 286, 655, 1362, 1569, 2587, 3067, 3096, 3462, 3510, 4095}},
|
|
{MachineType::Int16(),
|
|
kMipsLh,
|
|
kMipsSh,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-4095, -3340, -3231, -3224, -3088, -1758, -1203, -123, -117, -91, -89,
|
|
-87, -86, -82, -44, -23, -3, 0, 7, 10, 39, 52, 69, 71, 91, 92, 107, 109,
|
|
115, 124, 286, 655, 1362, 1569, 2587, 3067, 3096, 3462, 3510, 4095}},
|
|
{MachineType::Uint16(),
|
|
kMipsLhu,
|
|
kMipsSh,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-4095, -3340, -3231, -3224, -3088, -1758, -1203, -123, -117, -91, -89,
|
|
-87, -86, -82, -44, -23, -3, 0, 7, 10, 39, 52, 69, 71, 91, 92, 107, 109,
|
|
115, 124, 286, 655, 1362, 1569, 2587, 3067, 3096, 3462, 3510, 4095}},
|
|
{MachineType::Int32(),
|
|
kMipsLw,
|
|
kMipsSw,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-4095, -3340, -3231, -3224, -3088, -1758, -1203, -123, -117, -91, -89,
|
|
-87, -86, -82, -44, -23, -3, 0, 7, 10, 39, 52, 69, 71, 91, 92, 107, 109,
|
|
115, 124, 286, 655, 1362, 1569, 2587, 3067, 3096, 3462, 3510, 4095}},
|
|
{MachineType::Float32(),
|
|
kMipsLwc1,
|
|
kMipsSwc1,
|
|
&InstructionSelectorTest::Stream::IsDouble,
|
|
{-4095, -3340, -3231, -3224, -3088, -1758, -1203, -123, -117, -91, -89,
|
|
-87, -86, -82, -44, -23, -3, 0, 7, 10, 39, 52, 69, 71, 91, 92, 107, 109,
|
|
115, 124, 286, 655, 1362, 1569, 2587, 3067, 3096, 3462, 3510, 4095}},
|
|
{MachineType::Float64(),
|
|
kMipsLdc1,
|
|
kMipsSdc1,
|
|
&InstructionSelectorTest::Stream::IsDouble,
|
|
{-4095, -3340, -3231, -3224, -3088, -1758, -1203, -123, -117, -91, -89,
|
|
-87, -86, -82, -44, -23, -3, 0, 7, 10, 39, 52, 69, 71, 91, 92, 107, 109,
|
|
115, 124, 286, 655, 1362, 1569, 2587, 3067, 3096, 3462, 3510, 4095}}};
|
|
|
|
const MemoryAccessImm1 kMemoryAccessImmMoreThan16bit[] = {
|
|
{MachineType::Int8(),
|
|
kMipsLb,
|
|
kMipsSb,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-65000, -55000, 32777, 55000, 65000}},
|
|
{MachineType::Uint8(),
|
|
kMipsLbu,
|
|
kMipsSb,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-65000, -55000, 32777, 55000, 65000}},
|
|
{MachineType::Int16(),
|
|
kMipsLh,
|
|
kMipsSh,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-65000, -55000, 32777, 55000, 65000}},
|
|
{MachineType::Uint16(),
|
|
kMipsLhu,
|
|
kMipsSh,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-65000, -55000, 32777, 55000, 65000}},
|
|
{MachineType::Int32(),
|
|
kMipsLw,
|
|
kMipsSw,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-65000, -55000, 32777, 55000, 65000}},
|
|
{MachineType::Float32(),
|
|
kMipsLwc1,
|
|
kMipsSwc1,
|
|
&InstructionSelectorTest::Stream::IsDouble,
|
|
{-65000, -55000, 32777, 55000, 65000}},
|
|
{MachineType::Float64(),
|
|
kMipsLdc1,
|
|
kMipsSdc1,
|
|
&InstructionSelectorTest::Stream::IsDouble,
|
|
{-65000, -55000, 32777, 55000, 65000}}};
|
|
|
|
const MemoryAccessImm2 kMemoryAccessesImmUnaligned[] = {
|
|
{MachineType::Int16(),
|
|
kMipsUsh,
|
|
kMipsSh,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-4095, -3340, -3231, -3224, -3088, -1758, -1203, -123, -117, -91,
|
|
-89, -87, -86, -82, -44, -23, -3, 0, 7, 10,
|
|
39, 52, 69, 71, 91, 92, 107, 109, 115, 124,
|
|
286, 655, 1362, 1569, 2587, 3067, 3096, 3462, 3510, 4095}},
|
|
{MachineType::Int32(),
|
|
kMipsUsw,
|
|
kMipsSw,
|
|
&InstructionSelectorTest::Stream::IsInteger,
|
|
{-4095, -3340, -3231, -3224, -3088, -1758, -1203, -123, -117, -91,
|
|
-89, -87, -86, -82, -44, -23, -3, 0, 7, 10,
|
|
39, 52, 69, 71, 91, 92, 107, 109, 115, 124,
|
|
286, 655, 1362, 1569, 2587, 3067, 3096, 3462, 3510, 4095}},
|
|
{MachineType::Float32(),
|
|
kMipsUswc1,
|
|
kMipsSwc1,
|
|
&InstructionSelectorTest::Stream::IsDouble,
|
|
{-4095, -3340, -3231, -3224, -3088, -1758, -1203, -123, -117, -91,
|
|
-89, -87, -86, -82, -44, -23, -3, 0, 7, 10,
|
|
39, 52, 69, 71, 91, 92, 107, 109, 115, 124,
|
|
286, 655, 1362, 1569, 2587, 3067, 3096, 3462, 3510, 4095}},
|
|
{MachineType::Float64(),
|
|
kMipsUsdc1,
|
|
kMipsSdc1,
|
|
&InstructionSelectorTest::Stream::IsDouble,
|
|
{-4095, -3340, -3231, -3224, -3088, -1758, -1203, -123, -117, -91,
|
|
-89, -87, -86, -82, -44, -23, -3, 0, 7, 10,
|
|
39, 52, 69, 71, 91, 92, 107, 109, 115, 124,
|
|
286, 655, 1362, 1569, 2587, 3067, 3096, 3462, 3510, 4095}}};
|
|
|
|
} // namespace
|
|
|
|
using InstructionSelectorMemoryAccessTest =
|
|
InstructionSelectorTestWithParam<MemoryAccess>;
|
|
|
|
TEST_P(InstructionSelectorMemoryAccessTest, LoadWithParameters) {
|
|
const MemoryAccess memacc = GetParam();
|
|
StreamBuilder m(this, memacc.type, MachineType::Pointer(),
|
|
MachineType::Int32());
|
|
m.Return(m.Load(memacc.type, m.Parameter(0)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(memacc.load_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
|
|
}
|
|
|
|
|
|
TEST_P(InstructionSelectorMemoryAccessTest, StoreWithParameters) {
|
|
const MemoryAccess memacc = GetParam();
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Pointer(),
|
|
MachineType::Int32(), memacc.type);
|
|
m.Store(memacc.type.representation(), m.Parameter(0), m.Parameter(1),
|
|
kNoWriteBarrier);
|
|
m.Return(m.Int32Constant(0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
|
|
}
|
|
|
|
INSTANTIATE_TEST_SUITE_P(InstructionSelectorTest,
|
|
InstructionSelectorMemoryAccessTest,
|
|
::testing::ValuesIn(kMemoryAccesses));
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Load immediate.
|
|
// ----------------------------------------------------------------------------
|
|
|
|
using InstructionSelectorMemoryAccessImmTest =
|
|
InstructionSelectorTestWithParam<MemoryAccessImm>;
|
|
|
|
TEST_P(InstructionSelectorMemoryAccessImmTest, LoadWithImmediateIndex) {
|
|
const MemoryAccessImm memacc = GetParam();
|
|
TRACED_FOREACH(int32_t, index, memacc.immediates) {
|
|
StreamBuilder m(this, memacc.type, MachineType::Pointer());
|
|
m.Return(m.Load(memacc.type, m.Parameter(0), m.Int32Constant(index)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(memacc.load_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind());
|
|
EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_TRUE((s.*memacc.val_predicate)(s[0]->Output()));
|
|
}
|
|
}
|
|
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Store immediate.
|
|
// ----------------------------------------------------------------------------
|
|
|
|
|
|
TEST_P(InstructionSelectorMemoryAccessImmTest, StoreWithImmediateIndex) {
|
|
const MemoryAccessImm memacc = GetParam();
|
|
TRACED_FOREACH(int32_t, index, memacc.immediates) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Pointer(),
|
|
memacc.type);
|
|
m.Store(memacc.type.representation(), m.Parameter(0),
|
|
m.Int32Constant(index), m.Parameter(1), kNoWriteBarrier);
|
|
m.Return(m.Int32Constant(0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind());
|
|
EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1)));
|
|
EXPECT_EQ(0U, s[0]->OutputCount());
|
|
}
|
|
}
|
|
|
|
TEST_P(InstructionSelectorMemoryAccessImmTest, StoreZero) {
|
|
const MemoryAccessImm memacc = GetParam();
|
|
TRACED_FOREACH(int32_t, index, memacc.immediates) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Pointer());
|
|
m.Store(memacc.type.representation(), m.Parameter(0),
|
|
m.Int32Constant(index), m.Int32Constant(0), kNoWriteBarrier);
|
|
m.Return(m.Int32Constant(0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind());
|
|
EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1)));
|
|
ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(2)->kind());
|
|
EXPECT_EQ(0, s.ToInt64(s[0]->InputAt(2)));
|
|
EXPECT_EQ(0U, s[0]->OutputCount());
|
|
}
|
|
}
|
|
|
|
INSTANTIATE_TEST_SUITE_P(InstructionSelectorTest,
|
|
InstructionSelectorMemoryAccessImmTest,
|
|
::testing::ValuesIn(kMemoryAccessesImm));
|
|
|
|
using InstructionSelectorMemoryAccessUnalignedImmTest =
|
|
InstructionSelectorTestWithParam<MemoryAccessImm2>;
|
|
|
|
TEST_P(InstructionSelectorMemoryAccessUnalignedImmTest, StoreZero) {
|
|
const MemoryAccessImm2 memacc = GetParam();
|
|
TRACED_FOREACH(int32_t, index, memacc.immediates) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Pointer());
|
|
bool unaligned_store_supported =
|
|
m.machine()->UnalignedStoreSupported(memacc.type.representation());
|
|
m.UnalignedStore(memacc.type.representation(), m.Parameter(0),
|
|
m.Int32Constant(index), m.Int32Constant(0));
|
|
m.Return(m.Int32Constant(0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(unaligned_store_supported ? memacc.store_opcode_unaligned
|
|
: memacc.store_opcode,
|
|
s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind());
|
|
EXPECT_EQ(index, s.ToInt32(s[0]->InputAt(1)));
|
|
ASSERT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(2)->kind());
|
|
EXPECT_EQ(0, s.ToInt64(s[0]->InputAt(2)));
|
|
EXPECT_EQ(0U, s[0]->OutputCount());
|
|
}
|
|
}
|
|
|
|
INSTANTIATE_TEST_SUITE_P(InstructionSelectorTest,
|
|
InstructionSelectorMemoryAccessUnalignedImmTest,
|
|
::testing::ValuesIn(kMemoryAccessesImmUnaligned));
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Load/store offsets more than 16 bits.
|
|
// ----------------------------------------------------------------------------
|
|
|
|
using InstructionSelectorMemoryAccessImmMoreThan16bitTest =
|
|
InstructionSelectorTestWithParam<MemoryAccessImm1>;
|
|
|
|
TEST_P(InstructionSelectorMemoryAccessImmMoreThan16bitTest,
|
|
LoadWithImmediateIndex) {
|
|
const MemoryAccessImm1 memacc = GetParam();
|
|
TRACED_FOREACH(int32_t, index, memacc.immediates) {
|
|
StreamBuilder m(this, memacc.type, MachineType::Pointer());
|
|
m.Return(m.Load(memacc.type, m.Parameter(0), m.Int32Constant(index)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(memacc.load_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
|
|
EXPECT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
}
|
|
|
|
|
|
TEST_P(InstructionSelectorMemoryAccessImmMoreThan16bitTest,
|
|
StoreWithImmediateIndex) {
|
|
const MemoryAccessImm1 memacc = GetParam();
|
|
TRACED_FOREACH(int32_t, index, memacc.immediates) {
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Pointer(),
|
|
memacc.type);
|
|
m.Store(memacc.type.representation(), m.Parameter(0),
|
|
m.Int32Constant(index), m.Parameter(1), kNoWriteBarrier);
|
|
m.Return(m.Int32Constant(0));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
|
|
EXPECT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(0U, s[0]->OutputCount());
|
|
}
|
|
}
|
|
|
|
INSTANTIATE_TEST_SUITE_P(InstructionSelectorTest,
|
|
InstructionSelectorMemoryAccessImmMoreThan16bitTest,
|
|
::testing::ValuesIn(kMemoryAccessImmMoreThan16bit));
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// kMipsTst testing.
|
|
// ----------------------------------------------------------------------------
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Word32EqualWithZero) {
|
|
{
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
m.Return(m.Word32Equal(m.Parameter(0), m.Int32Constant(0)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsCmp, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_None, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(kFlags_set, s[0]->flags_mode());
|
|
EXPECT_EQ(kEqual, s[0]->flags_condition());
|
|
}
|
|
{
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
m.Return(m.Word32Equal(m.Int32Constant(0), m.Parameter(0)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsCmp, s[0]->arch_opcode());
|
|
EXPECT_EQ(kMode_None, s[0]->addressing_mode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(kFlags_set, s[0]->flags_mode());
|
|
EXPECT_EQ(kEqual, s[0]->flags_condition());
|
|
}
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Word32Clz) {
|
|
StreamBuilder m(this, MachineType::Uint32(), MachineType::Uint32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const n = m.Word32Clz(p0);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsClz, s[0]->arch_opcode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Float32Abs) {
|
|
StreamBuilder m(this, MachineType::Float32(), MachineType::Float32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const n = m.Float32Abs(p0);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsAbsS, s[0]->arch_opcode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Float64Abs) {
|
|
StreamBuilder m(this, MachineType::Float64(), MachineType::Float64());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const n = m.Float64Abs(p0);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsAbsD, s[0]->arch_opcode());
|
|
ASSERT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, Float32AddWithFloat32Mul) {
|
|
if (!IsMipsArchVariant(kMips32r2)) {
|
|
return;
|
|
}
|
|
{
|
|
StreamBuilder m(this, MachineType::Float32(), MachineType::Float32(),
|
|
MachineType::Float32(), MachineType::Float32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const p2 = m.Parameter(2);
|
|
Node* const n = m.Float32Add(m.Float32Mul(p0, p1), p2);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsMaddS, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(2)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_FALSE(
|
|
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
|
}
|
|
{
|
|
StreamBuilder m(this, MachineType::Float32(), MachineType::Float32(),
|
|
MachineType::Float32(), MachineType::Float32());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const p2 = m.Parameter(2);
|
|
Node* const n = m.Float32Add(p0, m.Float32Mul(p1, p2));
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsMaddS, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(2)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_FALSE(
|
|
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
|
}
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, Float64AddWithFloat64Mul) {
|
|
if (!IsMipsArchVariant(kMips32r2)) {
|
|
return;
|
|
}
|
|
{
|
|
StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(),
|
|
MachineType::Float64(), MachineType::Float64());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const p2 = m.Parameter(2);
|
|
Node* const n = m.Float64Add(m.Float64Mul(p0, p1), p2);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsMaddD, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(2)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_FALSE(
|
|
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
|
}
|
|
{
|
|
StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(),
|
|
MachineType::Float64(), MachineType::Float64());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const p2 = m.Parameter(2);
|
|
Node* const n = m.Float64Add(p0, m.Float64Mul(p1, p2));
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsMaddD, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(2)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_FALSE(
|
|
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
|
}
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, Float32SubWithFloat32Mul) {
|
|
StreamBuilder m(this, MachineType::Float32(), MachineType::Float32(),
|
|
MachineType::Float32(), MachineType::Float32());
|
|
if (!IsMipsArchVariant(kMips32r2)) {
|
|
return;
|
|
}
|
|
{
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const p2 = m.Parameter(2);
|
|
Node* n = nullptr;
|
|
|
|
n = m.Float32Sub(m.Float32Mul(p1, p2), p0);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsMsubS, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(2)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_FALSE(
|
|
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
|
}
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, Float64SubWithFloat64Mul) {
|
|
StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(),
|
|
MachineType::Float64(), MachineType::Float64());
|
|
if (!IsMipsArchVariant(kMips32r2)) {
|
|
return;
|
|
}
|
|
{
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const p2 = m.Parameter(2);
|
|
Node* n = nullptr;
|
|
|
|
n = m.Float64Sub(m.Float64Mul(p1, p2), p0);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsMsubD, s[0]->arch_opcode());
|
|
ASSERT_EQ(3U, s[0]->InputCount());
|
|
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
|
|
EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
|
|
EXPECT_EQ(s.ToVreg(p2), s.ToVreg(s[0]->InputAt(2)));
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_FALSE(
|
|
UnallocatedOperand::cast(s[0]->Output())->HasSameAsInputPolicy());
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
EXPECT_EQ(kFlags_none, s[0]->flags_mode());
|
|
}
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, Float64Max) {
|
|
StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(),
|
|
MachineType::Float64());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const n = m.Float64Max(p0, p1);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsFloat64Max, s[0]->arch_opcode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
}
|
|
|
|
|
|
TEST_F(InstructionSelectorTest, Float64Min) {
|
|
StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(),
|
|
MachineType::Float64());
|
|
Node* const p0 = m.Parameter(0);
|
|
Node* const p1 = m.Parameter(1);
|
|
Node* const n = m.Float64Min(p0, p1);
|
|
m.Return(n);
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsFloat64Min, s[0]->arch_opcode());
|
|
ASSERT_EQ(2U, s[0]->InputCount());
|
|
ASSERT_EQ(1U, s[0]->OutputCount());
|
|
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
|
|
}
|
|
|
|
TEST_F(InstructionSelectorTest, Word32ReverseBytes) {
|
|
{
|
|
StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
|
|
m.Return(m.Word32ReverseBytes(m.Parameter(0)));
|
|
Stream s = m.Build();
|
|
ASSERT_EQ(1U, s.size());
|
|
EXPECT_EQ(kMipsByteSwap32, s[0]->arch_opcode());
|
|
EXPECT_EQ(1U, s[0]->InputCount());
|
|
EXPECT_EQ(1U, s[0]->OutputCount());
|
|
}
|
|
}
|
|
|
|
} // namespace compiler
|
|
} // namespace internal
|
|
} // namespace v8
|