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1bc0e6f59a
Add a new legalization pass to dedupe invocation interlock instructions DXC will be adding support for HLSL's rasterizer ordered views by using the SPV_EXT_fragment_shader_interlock_extension. That extension stipulates that if an entry point has an interlock ordering execution mode, it must dynamically execute OpBeginInvocationInterlockEXT and OpEndInvocationInterlockEXT, in that order, exactly once. This would be difficult to determine in DXC's SPIR-V backend, so instead we will emit these instructions potentially multiple times, and use this legalization pass to ensure that the final SPIR-V follows the specification. This PR uses data-flow analysis to determine where to place begin and end instructions; in essence, determining whether a block contains or is preceded by a begin instruction is similar to a specialized case of a reaching definitions analysis, where we have only a single definition, such as `bool has_begun = false`. For this simpler case, we can compute the set of blocks using BFS to determine the reachability of the begin instruction. We need to do this for both begin and end instructions, so I have generalized portions of the code to run both forward and backward over the CFG for each respective case. |
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| .. | ||
| instrument.hpp | ||
| libspirv.h | ||
| libspirv.hpp | ||
| linker.hpp | ||
| linter.hpp | ||
| optimizer.hpp | ||