AuroraMiddleware/glibc
1
0
Fork 0
mirror of https://sourceware.org/git/glibc.git synced 2024-12-27 21:20:18 +00:00
Code Issues Packages Projects Releases Wiki Activity
37,405 Commits 334 Branches 1,646 Tags 289 MiB
5295172e20
Commit Graph

37405 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Xeonacid
5295172e20 fix typo 
"accomodate" should be "accommodate"
Reviewed-by: Paul Zimmermann <Paul.Zimmermann@inria.fr>
 2021-06-02 12:16:49 +02:00
Florian Weimer
a23c28ec0d dlfcn: Move dlerror into libc 
The symbol was moved using scripts/move-symbol-to-libc.py.

There is a minor functionality enhancement: dlerror now sets
errno if it was set as part of the exception.  (This is the result
of using %m in asprintf, to avoid the strerror PLT call.) The
previous errno value upon function return was unpredictable.
Documenting this as a feature is premature; we need to make sure
that the error codes are meaningful when they are set by the dynamic
loader.

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
 2021-06-02 09:06:10 +02:00
Florian Weimer
c44838ebf8 Add libc ABI extension kludge for baseline-violating libdl symbols 
Some targets have a GLIBC_2.0 baseline for libdl, while using
GLIBC_2.2 for libc.  This means that the generated libc.map file
does not have any version nodes for GLIBC_2.0 or GLIBC_2.1.  However,
moving symbols from libdl into libc needs such version nodes.
(Future symbol moves from librt will need this as well.)

This kludge is only necessary for symbols predating GLIBC_2.2 because
the affected targets use GLIBC_2.2 as the baseline for libc.  Given
the small number and fixed set of affected architectures, no generic
mechanism is implemented, and instead the map file fragment is
hard-coded in scripts/versions.mk.

The compat_symbol macro already emits the appropriate version strings,
so no adjustments are needed there.

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
 2021-06-02 07:34:24 +02:00
Florian Weimer
d32ee64df7 scripts/versions.awk: Add local: * to all version nodes 
This requires that all exported symbol versions are listed in
Versions files.  It results in more consistent behavior across
architectures because previously, symbols could be exported
via explicit versioned_symbol and compat_symbol macros if the
version node existed in some Versions file (without listing the
symbol), and it was not the base version for the library (which
already had the local: * directive).

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
 2021-06-02 07:32:44 +02:00
Florian Weimer
186cd80b1e Add missing symbols to Version files 
Some symbols have explicit versioned_symbol or compat_symbol markers
in the sources, but no corresponding entry in the Versions files.
This presently works because the local: * directive is only applied
to the base version.

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
 2021-06-02 07:32:19 +02:00
Florian Weimer
217b6dc298 Fix use of __pthread_attr_copy in mq_notify (bug 27896) 
__pthread_attr_copy can fail and does not initialize the attribute
structure in that case.

If __pthread_attr_copy is never called and there is no allocated
attribute, pthread_attr_destroy should not be called, otherwise
there is a null pointer dereference in rt/tst-mqueue6.

Fixes commit 42d3593505
("Use __pthread_attr_copy in mq_notify (bug 27896)").

Reviewed-by: Siddhesh Poyarekar <siddhesh@sourceware.org>
 2021-06-02 07:12:18 +02:00
Andreas Schwab
42d3593505 Use __pthread_attr_copy in mq_notify (bug 27896) 
Make a deep copy of the pthread attribute object to remove a potential
use-after-free issue.
 2021-06-01 17:12:33 +02:00
Joseph Myers
858045ad1c Update floating-point feature test macro handling for C2X 
ISO C2X has made some changes to the handling of feature test macros
related to features from the floating-point TSes, and to exactly what
such features are present in what headers, that require corresponding
changes in glibc.

* For the few features that were controlled by
  __STDC_WANT_IEC_60559_BFP_EXT__ (and the corresponding DFP macro) in
  C2X, there is now instead a new feature test macro
  __STDC_WANT_IEC_60559_EXT__ covering both binary and decimal FP.
  This controls CR_DECIMAL_DIG in <float.h> (provided by GCC; I
  implemented support for the new feature test macro for GCC 11) and
  the totalorder and payload functions in <math.h>.  C2X no longer
  says anything about __STDC_WANT_IEC_60559_BFP_EXT__ (so it's
  appropriate for that macro to continue to enable exactly the
  features from TS 18661-1).

* The SNAN macros for each floating-point type have moved to <float.h>
  (and been renamed in the process).  Thus, the copies in <math.h>
  should only be defined for __STDC_WANT_IEC_60559_BFP_EXT__, not for
  C2X.

* The fmaxmag and fminmag functions have been removed (replaced by new
  functions for the new min/max operations in IEEE 754-2019).  Thus
  those should also only be declared for
  __STDC_WANT_IEC_60559_BFP_EXT__.

* The _FloatN / _FloatNx handling for the last two points in glibc is
  trickier, since __STDC_WANT_IEC_60559_TYPES_EXT__ is still in C2X
  (the integration of TS 18661-3 as an Annex, that is, which hasn't
  yet been merged into the C standard git repository but has been
  accepted by WG14), so C2X with that macro should not declare some
  things that are declared for older standards with that macro.  The
  approach taken here is to provide the declarations (when
  __STDC_WANT_IEC_60559_TYPES_EXT__ is enabled) only when (defined
  __USE_GNU || !__GLIBC_USE (ISOC2X)), so if C2X features are enabled
  then those declarations (that are only in TS 18661-3 and not in C2X)
  will only be provided if _GNU_SOURCE is defined as well.  Thus
  _GNU_SOURCE remains a superset of the TS features as well as of C2X.

Some other somewhat related changes in C2X are not addressed here.
There's an open proposal not to include the fmin and fmax functions
for the _FloatN / _FloatNx types, given the new min/max operations,
which could be handled like the previous point if adopted.  And the
fromfp functions have been changed to return a result in floating type
rather than intmax_t / uintmax_t; my inclination there is to treat
that like that change of totalorder type (new symbol versions etc. for
the ABI change; old versions become compat symbols and are no longer
supported as an API).

Tested for x86_64 and x86.
 2021-06-01 14:22:06 +00:00
Florian Weimer
c8a11c5867 stdio-common: Remove _IO_vfwscanf 
The symbol has never been exported, so no compatibility symbol is
needed.  Removing this file prevents ld from creation an exported
symbol in case GLIBC_2_0 expands to a symbol version which
does not have a local: *; directive in the symbol version map file.

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
 2021-06-01 16:00:52 +02:00
Szabolcs Nagy
3842ba4949 aarch64: align stack in clone [BZ #27939] 
The AArch64 PCS requires 16 byte aligned stack.  Previously if the
caller passed an unaligned stack to clone then the child crashed.

Fixes bug 27939.
 2021-06-01 09:47:48 +01:00
Lucas A. M. Magalhaes
a55e2da270 powerpc: Optimized memcmp for power10 
This patch was based on the __memcmp_power8 and the recent
__strlen_power10.

Improvements from __memcmp_power8:

1. Don't need alignment code.

   On POWER10 lxvp and lxvl do not generate alignment interrupts, so
they are safe for use on caching-inhibited memory.  Notice that the
comparison on the main loop will wait for both VSR to be ready.
Therefore aligning one of the input address does not improve
performance.  In order to align both registers a vperm is necessary
which add too much overhead.

2. Uses new POWER10 instructions

   This code uses lxvp to decrease contention on load by loading 32 bytes
per instruction.
   The vextractbm is used to have a smaller tail code for calculating the
return value.

3. Performance improvement

   This version has around 35% better performance on average. I saw no
performance regressions for any length or alignment.

Thanks Matheus for helping me out with some details.

Co-authored-by: Matheus Castanho <msc@linux.ibm.com>
Reviewed-by: Raphael M Zinsly <rzinsly@linux.ibm.com>
 2021-05-31 18:00:20 -03:00
H.J. Lu
92a7d13439 x86-64: Align child stack to 16 bytes [BZ #27902] 
In the x86-64 clone wrapper, align child stack to 16 bytes per the
x86-64 psABI.

Reviewed-by: Carlos O'Donell <carlos@redhat.com>
 2021-05-31 12:03:36 -07:00
Adhemerval Zanella
271ec55d0a support: Do not build xpthread_attr_setaffinity_np for hurd 
It does not provide pthread_attr_setaffinity_np extension.
 2021-05-28 16:00:19 -03:00
Adhemerval Zanella
2c44452b61 nptl: Add pthread_attr_setaffinity_np failure test 
It checks whether an invalid affinity mask does return an error,
similar to what sysdeps/pthread/tst-bad-schedattr.c does for
pthread_attr_setschedparam.

Checked on x86_64-linux-gnu.
 2021-05-27 13:12:16 -03:00
Adhemerval Zanella
d85ad0e58a support: Add xpthread_attr_setaffinity_np wrapper 2021-05-27 13:12:07 -03:00
Adhemerval Zanella
42813c675d nptl: Move createthread to pthread_create 
The 'create_thread' function is moved to pthread_create.c.  It removes
the START_THREAD_DEFN and START_THREAD_SELF macros and make the
lock usage more clear (no need to cross-reference multiple files).

No functional change.
 2021-05-27 13:11:41 -03:00
Adhemerval Zanella
65ba6fa431 nptl: Move Linux createthread to nptl 
git mv -f sysdeps/unix/sysv/linux/createthread.c nptl/createthread.c

No functional change.
 2021-05-27 13:11:35 -03:00
Florian Weimer
76b0c59e33 nptl: Install SIGSETXID handler with SA_ONSTACK [BZ #27914] 
The signal is sent to all threads, some of which may have switched
to very small stacks.  If they have also installed an alternate
signal stack, SA_ONSTACK makes this work.  The Go runtime needs this:

  runtime: C.setuid/C.setgid smashes Go stack
  <https://github.com/golang/go/issues/9400>

Doing this for SIGCANCEL is less obviously beneficial and needs further
testing.

Reviewed-by: Carlos O'Donell <carlos@redhat.com>
 2021-05-27 15:37:35 +02:00
Naohiro Tamura
4f26956d5b aarch64: Added optimized memset for A64FX 
This patch optimizes the performance of memset for A64FX [1] which
implements ARMv8-A SVE and has L1 64KB cache per core and L2 8MB cache
per NUMA node.

The performance optimization makes use of Scalable Vector Register
with several techniques such as loop unrolling, memory access
alignment, cache zero fill and prefetch.

SVE assembler code for memset is implemented as Vector Length Agnostic
code so theoretically it can be run on any SOC which supports ARMv8-A
SVE standard.

We confirmed that all testcases have been passed by running 'make
check' and 'make xcheck' not only on A64FX but also on ThunderX2.

And also we confirmed that the SVE 512 bit vector register performance
is roughly 4 times better than Advanced SIMD 128 bit register and 8
times better than scalar 64 bit register by running 'make bench'.

[1] https://github.com/fujitsu/A64FX

Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
Reviewed-by: Szabolcs Nagy <Szabolcs.Nagy@arm.com>
 2021-05-27 09:47:53 +01:00
Naohiro Tamura
fa527f345c aarch64: Added optimized memcpy and memmove for A64FX 
This patch optimizes the performance of memcpy/memmove for A64FX [1]
which implements ARMv8-A SVE and has L1 64KB cache per core and L2 8MB
cache per NUMA node.

The performance optimization makes use of Scalable Vector Register
with several techniques such as loop unrolling, memory access
alignment, cache zero fill, and software pipelining.

SVE assembler code for memcpy/memmove is implemented as Vector Length
Agnostic code so theoretically it can be run on any SOC which supports
ARMv8-A SVE standard.

We confirmed that all testcases have been passed by running 'make
check' and 'make xcheck' not only on A64FX but also on ThunderX2.

And also we confirmed that the SVE 512 bit vector register performance
is roughly 4 times better than Advanced SIMD 128 bit register and 8
times better than scalar 64 bit register by running 'make bench'.

[1] https://github.com/fujitsu/A64FX

Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
Reviewed-by: Szabolcs Nagy <Szabolcs.Nagy@arm.com>
 2021-05-27 09:47:53 +01:00
Naohiro Tamura
f12ec02f53 benchtests: Fixed bench-memcpy-random: buf1: mprotect failed 
This patch fixed mprotect system call failure on AArch64.
This failure happened on not only A64FX but also ThunderX2.

Also this patch updated a JSON key from "max-size" to "length" so that
'plot_strings.py' can process 'bench-memcpy-random.out'
 2021-05-26 12:01:06 +01:00
Naohiro Tamura
3856056358 aarch64: Added Vector Length Set test helper script 
This patch is a test helper script to change Vector Length for child
process. This script can be used as test-wrapper for 'make check'.

Usage examples:

~/build$ make check subdirs=string \
test-wrapper='~/glibc/sysdeps/unix/sysv/linux/aarch64/vltest.py 16'

~/build$ ~/glibc/sysdeps/unix/sysv/linux/aarch64/vltest.py 16 \
make test t=string/test-memcpy

~/build$ ~/glibc/sysdeps/unix/sysv/linux/aarch64/vltest.py 32 \
./debugglibc.sh string/test-memmove

~/build$ ~/glibc/sysdeps/unix/sysv/linux/aarch64/vltest.py 64 \
./testrun.sh string/test-memset
 2021-05-26 12:01:06 +01:00
Naohiro Tamura
bd4317fbd6 aarch64: define BTI_C and BTI_J macros as NOP unless HAVE_AARCH64_BTI 
This patch defines BTI_C and BTI_J macros conditionally for
performance.
If HAVE_AARCH64_BTI is true, BTI_C and BTI_J are defined as HINT
instruction for ARMv8.5 BTI (Branch Target Identification).
If HAVE_AARCH64_BTI is false, both BTI_C and BTI_J are defined as
NOP.
 2021-05-26 12:01:06 +01:00
Naohiro Tamura
77d175e14e config: Added HAVE_AARCH64_SVE_ASM for aarch64 
This patch checks if assembler supports '-march=armv8.2-a+sve' to
generate SVE code or not, and then define HAVE_AARCH64_SVE_ASM macro.
 2021-05-26 12:01:06 +01:00
Yang Xu
bfbdfe4eab tst-mallinfo2.c: Use correct multiple for total variable 
Since test uses 160 multiple for malloc size, we should also use 160 multiple
for total variable instead of 16, then comparison is meaningful. So fix it.

Also change the ">" to ">=" so that the test is technically valid.

Reviewed-by: DJ Delorie <dj@redhat.com>
 2021-05-25 16:47:01 -04:00
Florian Weimer
ac0353af81 Linux: Remove remaining references to $(shared-thread-library) 
Since the variable expands to nothing under Linux, it is no longer
necessary to clutter the makefiles with it.

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
 2021-05-25 11:30:23 +02:00
Florian Weimer
3b638095a5 nptl: Do not install libpthread.so and do not link tests with it 
Keep installing libpthread.a, so that -lpthread works.

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
 2021-05-25 11:30:23 +02:00
Lucas A. M. Magalhaes
709e3709a0 testrun.sh: Improve --help message 
The testrun.sh --help message was missing the "container" option.
Besides just adding the missing option I decide to rewrite it in the
same layout as other tools.

Reviewed-by: Carlos O'Donell <carlos@redhat.com>
 2021-05-25 10:14:19 +05:30
Nicholas Piggin
7de36744ee powerpc: Fix handling of scv return error codes [BZ #27892] 
When using scv for templated ASM syscalls, current code interprets any
negative return value as error, but the only valid error codes are in
the range -4095..-1 according to the ABI.

This commit also fixes 'signal.gen.test' strace test, where the issue
was first identified.

Reviewed-by: Matheus Castanho <msc@linux.ibm.com>
 2021-05-24 17:01:40 -03:00
H.J. Lu
79aec84102 Properly check stack alignment [BZ #27901] 
1. Replace

if ((((uintptr_t) &_d) & (__alignof (double) - 1)) != 0)

which may be optimized out by compiler, with

int
__attribute__ ((weak, noclone, noinline))
is_aligned (void *p, int align)
{
  return (((uintptr_t) p) & (align - 1)) != 0;
}

2. Add TEST_STACK_ALIGN_INIT to TEST_STACK_ALIGN.
3. Add a common TEST_STACK_ALIGN_INIT to check 16-byte stack alignment
for both i386 and x86-64.
4. Update powerpc to use TEST_STACK_ALIGN_INIT.

Reviewed-by: Carlos O'Donell <carlos@redhat.com>
 2021-05-24 07:42:12 -07:00
Noah Goldstein
1b992204f6 x86: Improve memmove-vec-unaligned-erms.S 
This patch changes the condition for copy 4x VEC so that if length is
exactly equal to 4 * VEC_SIZE it will use the 4x VEC case instead of
8x VEC case.

Results For Skylake memcpy-avx2-erms
size, al1 , al2 , Cur T   , New T   , Win , New / Cur
128 , 0   , 0   , 9.137   , 6.873   , New , 75.22
128 , 7   , 0   , 12.933  , 7.732   , New , 59.79
128 , 0   , 7   , 11.852  , 6.76    , New , 57.04
128 , 7   , 7   , 12.587  , 6.808   , New , 54.09

Results For Icelake memcpy-evex-erms
size, al1 , al2 , Cur T   , New T   , Win , New / Cur
128 , 0   , 0   , 9.963   , 5.416   , New , 54.36
128 , 7   , 0   , 16.467  , 8.061   , New , 48.95
128 , 0   , 7   , 14.388  , 7.644   , New , 53.13
128 , 7   , 7   , 14.546  , 7.642   , New , 52.54

Results For Tigerlake memcpy-evex-erms
size, al1 , al2 , Cur T   , New T   , Win , New / Cur
128 , 0   , 0   , 8.979   , 4.95    , New , 55.13
128 , 7   , 0   , 14.245  , 7.122   , New , 50.0
128 , 0   , 7   , 12.668  , 6.675   , New , 52.69
128 , 7   , 7   , 13.042  , 6.802   , New , 52.15

Results For Skylake memmove-avx2-erms
size, al1 , al2 , Cur T   , New T   , Win , New / Cur
128 , 0   , 32  , 6.181   , 5.691   , New , 92.07
128 , 32  , 0   , 6.165   , 5.752   , New , 93.3
128 , 0   , 7   , 13.923  , 9.37    , New , 67.3
128 , 7   , 0   , 12.049  , 10.182  , New , 84.5

Results For Icelake memmove-evex-erms
size, al1 , al2 , Cur T   , New T   , Win , New / Cur
128 , 0   , 32  , 5.479   , 4.889   , New , 89.23
128 , 32  , 0   , 5.127   , 4.911   , New , 95.79
128 , 0   , 7   , 18.885  , 13.547  , New , 71.73
128 , 7   , 0   , 15.565  , 14.436  , New , 92.75

Results For Tigerlake memmove-evex-erms
size, al1 , al2 , Cur T   , New T   , Win , New / Cur
128 , 0   , 32  , 5.275   , 4.815   , New , 91.28
128 , 32  , 0   , 5.376   , 4.565   , New , 84.91
128 , 0   , 7   , 19.426  , 14.273  , New , 73.47
128 , 7   , 0   , 15.924  , 14.951  , New , 93.89

Signed-off-by: Noah Goldstein <goldstein.w.n@gmail.com>
 2021-05-23 22:50:49 -04:00
Noah Goldstein
fc335a0ded Bench: Add support for choose direction of memcpy in benchtests 
This patch adds support for testing memcpy with both dst > src and dst
< src. Since memcpy is implemented as memmove which has seperate
control flows for certain sizes depending on dst > src it seems like
1) information that should be provided in the benchtest output and a
variable that can be controlled for the benchmarks.

Signed-off-by: Noah Goldstein <goldstein.w.n@gmail.com>
 2021-05-23 19:36:36 -04:00
H.J. Lu
94bc766ec6 Add cast_to_pointer to cast an integer to void * pointer 2021-05-22 05:09:15 -07:00
Florian Weimer
49e182c737 nptl: Remove remaining code from libpthread 
Only the placeholder compatibility symbols are left now.

The __errno_location symbol was removed (moved) using
scripts/move-symbol-to-libc.py.

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
 2021-05-21 22:35:01 +02:00
Florian Weimer
f47f1d91af nptl: Move pthread_create, thrd_create into libc 
The symbols were moved using scripts/move-symbol-to-libc.py.

The libpthread placeholder symbols need some changes because some
symbol versions have gone away completely.  But
__errno_location@@GLIBC_2.0 still exists, so the GLIBC_2.0 version
is still there.

The internal __pthread_create symbol now points to the correct
function, so the sysdeps/nptl/thrd_create.c override is no longer
necessary.

There was an issue how the hidden alias of pthread_getattr_default_np
was defined, so this commit cleans up that aspects and removes the
GLIBC_PRIVATE export altogether.

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
 2021-05-21 22:35:00 +02:00
Florian Weimer
7862ff8e69 elf: Use custom NODELETE DSO for tst-dlopenfail, tst-dlopenfail-2 
Once libpthread is empty and no longer marked NODELETE, it no longer
can be used for testing.

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
 2021-05-21 22:35:00 +02:00
Florian Weimer
b8cdc3bba7 nptl: Move semi-public __pthread_get_minstack symbol into libc 
No abilist updates here because it is a GLIBC_PRIVATE symbol.

It's also necessary to move nptl_version into pthread_create, so
that it still ends up in static binaries.

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
 2021-05-21 22:35:00 +02:00
Florian Weimer
d03511f48f nptl: Eliminate the __static_tls_size, __static_tls_align_m1 variables 
Use the  __nptl_tls_static_size_for_stack inline function instead,
and the GLRO (dl_tls_static_align) value directly.

The computation of GLRO (dl_tls_static_align)  in
_dl_determine_tlsoffset ensures that the alignment is at least
TLS_TCB_ALIGN, which at least STACK_ALIGN (see allocate_stack).
Therefore, the additional rounding-up step is removed.

ALso move the initialization of the default stack size from
__pthread_initialize_minimal_internal to __pthread_early_init.
This introduces an extra system call during single-threaded startup,
but this simplifies the initialization sequence.  No locking is
needed around the writes to __default_pthread_attr because the
process is single-threaded at this point.

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
 2021-05-21 22:35:00 +02:00
Florian Weimer
2f69522d46 nptl: Perform signal initialization upon pthread_create 
Install signal handlers and unblock signals before pthread_create
creates the first thread.

create_thread in sysdeps/unix/sysv/linux/createthread.c can send
SIGCANCEL to the current thread, so the SIGCANCEL handler is currently
needed even if pthread_cancel is never called.  (The way timer_create
uses SIGCANCEL does not need a signal handler; both SIG_DFL and SIG_IGN
dispositions should work.)

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
 2021-05-21 22:35:00 +02:00
Florian Weimer
06a36b70f9 nptl: Remove unused __libc_pthread_init function 
Fixes commit 732139dabe
("Linux: Move __reclaim_stacks into the fork implementation in
libc").
 2021-05-21 12:09:07 +02:00
Noah Goldstein
6abf27980a x86: Improve memset-vec-unaligned-erms.S 
No bug. This commit makes a few small improvements to
memset-vec-unaligned-erms.S. The changes are 1) only aligning to 64
instead of 128. Either alignment will perform equally well in a loop
and 128 just increases the odds of having to do an extra iteration
which can be significant overhead for small values. 2) Align some
targets and the loop. 3) Remove an ALU from the alignment process. 4)
Reorder the last 4x VEC so that they are stored after the loop. 5)
Move the condition for leq 8x VEC to before the alignment
process. test-memset and test-wmemset are both passing.

Signed-off-by: Noah Goldstein <goldstein.w.n@gmail.com>
Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
 2021-05-20 17:28:33 -04:00
Florian Weimer
f5e196b5a0 Hurd: Define ARCH_MIN_GUARD_SIZE in internal <pthread.h> 
This macro is always defined on Linux.

Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
 2021-05-20 18:56:57 +02:00
Florian Weimer
9ec7fff6cd elf: Initialize GLRO (dl_minsigstacksize) after static dlopen 
This is another field of _rtld_global_ro that benefits from
initialization in __rtld_static_init.

Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
 2021-05-20 18:56:42 +02:00
Florian Weimer
eb0e4756cf nptl: Add missing __pthread_cond_wait alias in static builds 
Fixes commit cf3fff1c19 ("nptl: Move
cnd_wait into libc").

Reviewed-by: Jonathan Nieder <jrnieder@gmail.com>
 2021-05-19 22:16:28 +02:00
Adhemerval Zanella
f294306ba1 Remove --enable-stackguard-randomization (BZ #27872) 
Last ENABLE_STACKGUARD_RANDOMIZE usage was removed by 4a103975c4.
 2021-05-19 10:22:19 -03:00
Florian Weimer
1805bf753f s390x: Check HWCAP bits against compiler flags 
When compiled with GCC 11.1 and -march=z14 -O3 build flags, running
ld.so (or any dynamically linked program) prints:

Fatal glibc error: CPU lacks VXE support (z14 or later required)

Co-Authored-By: Stefan Liebler <stli@linux.ibm.com>
Reviewed-by: Stefan Liebler <stli@linux.ibm.com>
 2021-05-19 11:09:57 +02:00
Florian Weimer
d337345ce1 powerpc64le: Check HWCAP bits against compiler build flags 
When built with GCC 11.1 and -mcpu=power9, ld.so prints this error
message when running on POWER8:

Fatal glibc error: CPU lacks ISA 3.00 support (POWER9 or later required)
 2021-05-19 11:09:57 +02:00
Florian Weimer
eb24865637 elf: Add hook for checking HWCAP bits after auxiliary vector parsing 
Reviewed-by: Stefan Liebler <stli@linux.ibm.com>
 2021-05-19 11:09:57 +02:00
Noah Goldstein
4ad473e97a x86: Optimize memcmp-evex-movbe.S 
No bug. This commit optimizes memcmp-evex.S. The optimizations include
adding a new vec compare path for small sizes, reorganizing the entry
control flow, removing some unnecissary ALU instructions from the main
loop, and most importantly replacing the heavy use of vpcmp + kand
logic with vpxor + vptern. test-memcmp and test-wmemcmp are both
passing.

Signed-off-by: Noah Goldstein <goldstein.w.n@gmail.com>
Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
 2021-05-18 22:57:51 -04:00
Noah Goldstein
16d12015c5 x86: Optimize memcmp-avx2-movbe.S 
No bug. This commit optimizes memcmp-avx2.S. The optimizations include
adding a new vec compare path for small sizes, reorganizing the entry
control flow, and removing some unnecissary ALU instructions from the
main loop. test-memcmp and test-wmemcmp are both passing.

Signed-off-by: Noah Goldstein <goldstein.w.n@gmail.com>
Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
 2021-05-18 22:57:44 -04:00