AuroraMiddleware/qt5base-lts
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
e0eb2818fa
qt5base-lts/config.tests/arch/arch.cpp

295 lines
7.5 KiB
C++
Raw Normal View History

Use SPDX license identifiers Replace the current license disclaimer in files by a SPDX-License-Identifier. Files that have to be modified by hand are modified. License files are organized under LICENSES directory. Task-number: QTBUG-67283 Change-Id: Id880c92784c40f3bbde861c0d93f58151c18b9f1 Reviewed-by: Qt CI Bot <qt_ci_bot@qt-project.org> Reviewed-by: Lars Knoll <lars.knoll@qt.io> Reviewed-by: Jörg Bornemann <joerg.bornemann@qt.io>
2022-05-10 10:06:48 +00:00
// Copyright (C) 2016 The Qt Company Ltd.
// Copyright (C) 2016 Intel Corporation.
// SPDX-License-Identifier: LicenseRef-Qt-Commercial OR LGPL-3.0-only OR GPL-2.0-only OR GPL-3.0-only
Remove -arch argument and #define QT_ARCH from configures Do not try to detect the host or target architectures using uname or similar, and do not override with the -arch or -host-arch configure arguments. The configures will still accept the -arch and -host-arch arguments, but it ignores them and instead outputs a warning stating that these arguments are obsolete and should not be used. Set QT_ARCH and QT_HOST_ARCH qconfig.pri variables based on the compiler target. This is done by running qmake (twice when cross-compiling) on config.tests/arch/arch.pro, which preprocesses a file that contains all knowns processors. On Windows, configure.exe has never run any config.tests before, and does not currently have a function to run a program and capture its output. Use _popen() to accomplish this (as qmake does for its system() function). This needs to be done after qmake is built, as does the mkspecs/qconfig.pri generation. As a side effect, the configure steps have been slightly re-ordered, but the overall result is the same. The displayConfig() call is moved to just before generating Makefiles, so that it can show the detected architecture(s). Change-Id: I77666c77a93b48848f87648d08e79a42f721683f Reviewed-by: Morten Johan Sørvig <morten.sorvig@nokia.com> Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2012-02-14 09:01:17 +00:00
Ensure that qXXXdetection.h can be included directly Those files might have dependency on one another, on qconfig.h and on early qglobal.h definitions, so ensure that the only correct include order is that of qglobal.h. Change-Id: I89098bacaf16353ee8b51604ee885508dc8e201a Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
2012-03-28 19:28:46 +00:00
#define QGLOBAL_H
Add QSysInfo::cpuArchitecture() and fullCpuArchitecture() This uses the same logic as the config.test, so we will return the same string as the $$QT_ARCH variable in qmake for cpuArchitecture(). fullCpuArchitecture() is meant to be used in upgrade mechanisms, when combined with the OS type. Change-Id: If0dfee9eff75a07fa4c0778d204e0e768bf43074 Reviewed-by: Kai Koehne <kai.koehne@digia.com> Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@digia.com>
2014-03-06 20:58:21 +00:00
#include "../../src/corelib/global/archdetect.cpp"
Improve the architecture-detection mechanism For the Unix part, this now obeys the -v option, printing the full command-line it used to compile, allowing testers to identify why something went wrong. Unfortunately, it requires a full compilation cycle, instead of just preprocessing. Just one more among the many on Unix, but maybe a noticeable slow-down on Windows. Change-Id: I654b70d99887e04c96731a5b91be9ad555e4d8fe Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com> Reviewed-by: Girish Ramakrishnan <girish.1.ramakrishnan@nokia.com>
2012-03-27 17:43:45 +00:00
#include <stdio.h>
extern const char msg[];
Add QSysInfo::cpuArchitecture() and fullCpuArchitecture() This uses the same logic as the config.test, so we will return the same string as the $$QT_ARCH variable in qmake for cpuArchitecture(). fullCpuArchitecture() is meant to be used in upgrade mechanisms, when combined with the OS type. Change-Id: If0dfee9eff75a07fa4c0778d204e0e768bf43074 Reviewed-by: Kai Koehne <kai.koehne@digia.com> Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@digia.com>
2014-03-06 20:58:21 +00:00
const char msg[] = "==Qt=magic=Qt== Architecture:" ARCH_PROCESSOR;
Improve the architecture-detection mechanism For the Unix part, this now obeys the -v option, printing the full command-line it used to compile, allowing testers to identify why something went wrong. Unfortunately, it requires a full compilation cycle, instead of just preprocessing. Just one more among the many on Unix, but maybe a noticeable slow-down on Windows. Change-Id: I654b70d99887e04c96731a5b91be9ad555e4d8fe Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com> Reviewed-by: Girish Ramakrishnan <girish.1.ramakrishnan@nokia.com>
2012-03-27 17:43:45 +00:00
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
extern const char msg2[];
const char msg2[] = "==Qt=magic=Qt== Sub-architecture:"
// This is the list of features found in GCC or MSVC
// We don't use all of them, but this is ready for future expansion
// -- x86 --
#ifdef __3dNOW__
// 3dNow!, introduced with the AMD K6-2, discontinued after 2010
" 3dnow"
#endif
#ifdef __3dNOW_A__
// Athlon
" 3dnow-a"
#endif
#ifdef __ABM__
// Advanced Bit Manipulation, AMD Barcelona (family 10h)
" abm"
#endif
Update the list of x86 instruction set extensions enabled by GCC From GCC 6's gcc/config/i386.c and i386-c.c Change-Id: Ib306f8f647014b399b87ffff13f1d8a8cfbfa591 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@theqtcompany.com> Reviewed-by: Olivier Goffart (Woboq GmbH) <ogoffart@woboq.com>
2015-07-17 21:19:35 +00:00
#ifdef __ADX__
// Multi-Precision Add-Carry Instruction Extensions, Intel Core 5th generation ("Broadwell")
" adx"
#endif
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
#ifdef __AES__
// AES New Instructions, Intel Core-i7 second generation ("Sandy Bridge")
" aes"
#endif
#ifdef __AVX__
// Advanced Vector Extensions, Intel Core-i7 second generation ("Sandy Bridge")
" avx"
#endif
#ifdef __AVX2__
Replace the Intel Haswell and Ivy Bridge codenames with actual names Change-Id: I2a31e96d324dd704e6f96b35ec68c79fd64a090e Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@digia.com> Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
2013-08-06 23:04:50 +00:00
// AVX 2, Intel Core 4th Generation ("Haswell")
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
" avx2"
#endif
Add x86 arch detection support for AVX512 and SHA instructions The flags come from GCC commit 201219: http://gcc.gnu.org/viewcvs/gcc/branches/avx512/gcc/config/i386/i386-c.c?limit_changes=0&r1=201219&r2=201218&pathrev=201219 Clang and ICC don't seem to have support for this yet. Change-Id: Ic941654a5c56ed110d0e754e436a92dc5deaeb17 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@digia.com>
2013-08-06 23:24:57 +00:00
#ifdef __AVX512F__
SIMD: Remove unused (and unlikely to be ever used) AVX-512 profiles "AVX512MIC" (Many Integrated Cores) is the set of AVX-512 features found on the Intel Xeon Phi coprocessors (codename "Knights Landing"), which is an unlikely architecture for Qt to run on. The two profiles with VL came from study of early GCC code and are no longer applicable. GCC source code now shows both VBMI and IFMA as part of the -march=cannonlake feature set. Change-Id: Iff4151c519c144d580c4fffd153a0f268919fe2c Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2018-06-21 03:28:01 +00:00
// AVX512 Foundation, Intel Xeon Scalable ("Skylake" server), some Intel Core 7th generation ("Skylake")
Add x86 arch detection support for AVX512 and SHA instructions The flags come from GCC commit 201219: http://gcc.gnu.org/viewcvs/gcc/branches/avx512/gcc/config/i386/i386-c.c?limit_changes=0&r1=201219&r2=201218&pathrev=201219 Clang and ICC don't seem to have support for this yet. Change-Id: Ic941654a5c56ed110d0e754e436a92dc5deaeb17 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@digia.com>
2013-08-06 23:24:57 +00:00
" avx512f"
#endif
#ifdef __AVX512CD__
SIMD: Remove unused (and unlikely to be ever used) AVX-512 profiles "AVX512MIC" (Many Integrated Cores) is the set of AVX-512 features found on the Intel Xeon Phi coprocessors (codename "Knights Landing"), which is an unlikely architecture for Qt to run on. The two profiles with VL came from study of early GCC code and are no longer applicable. GCC source code now shows both VBMI and IFMA as part of the -march=cannonlake feature set. Change-Id: Iff4151c519c144d580c4fffd153a0f268919fe2c Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2018-06-21 03:28:01 +00:00
// AVX512 Conflict Detection, Intel Xeon Scalable ("Skylake" server), some Intel Core 7th generation ("Skylake")
Add x86 arch detection support for AVX512 and SHA instructions The flags come from GCC commit 201219: http://gcc.gnu.org/viewcvs/gcc/branches/avx512/gcc/config/i386/i386-c.c?limit_changes=0&r1=201219&r2=201218&pathrev=201219 Clang and ICC don't seem to have support for this yet. Change-Id: Ic941654a5c56ed110d0e754e436a92dc5deaeb17 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@digia.com>
2013-08-06 23:24:57 +00:00
" avx512cd"
#endif
Add the detection of the compiler macros for more AVX512 features Change-Id: I1d1f2c3857824b17185bc47398299ea7f92c5568 Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
2014-07-30 16:53:01 +00:00
#ifdef __AVX512DQ__
SIMD: Remove unused (and unlikely to be ever used) AVX-512 profiles "AVX512MIC" (Many Integrated Cores) is the set of AVX-512 features found on the Intel Xeon Phi coprocessors (codename "Knights Landing"), which is an unlikely architecture for Qt to run on. The two profiles with VL came from study of early GCC code and are no longer applicable. GCC source code now shows both VBMI and IFMA as part of the -march=cannonlake feature set. Change-Id: Iff4151c519c144d580c4fffd153a0f268919fe2c Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2018-06-21 03:28:01 +00:00
// AVX512 Double & Quadword, Intel Xeon Scalable ("Skylake" server), some Intel Core 7th generation ("Skylake")
Add the detection of the compiler macros for more AVX512 features Change-Id: I1d1f2c3857824b17185bc47398299ea7f92c5568 Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
2014-07-30 16:53:01 +00:00
" avx512dq"
#endif
#ifdef __AVX512BW__
SIMD: Remove unused (and unlikely to be ever used) AVX-512 profiles "AVX512MIC" (Many Integrated Cores) is the set of AVX-512 features found on the Intel Xeon Phi coprocessors (codename "Knights Landing"), which is an unlikely architecture for Qt to run on. The two profiles with VL came from study of early GCC code and are no longer applicable. GCC source code now shows both VBMI and IFMA as part of the -march=cannonlake feature set. Change-Id: Iff4151c519c144d580c4fffd153a0f268919fe2c Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2018-06-21 03:28:01 +00:00
// AVX512 Byte & Word, Intel Xeon Scalable ("Skylake" server), some Intel Core 7th generation ("Skylake")
Add the detection of the compiler macros for more AVX512 features Change-Id: I1d1f2c3857824b17185bc47398299ea7f92c5568 Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
2014-07-30 16:53:01 +00:00
" avx512bw"
#endif
Add x86 arch detection support for AVX512 and SHA instructions The flags come from GCC commit 201219: http://gcc.gnu.org/viewcvs/gcc/branches/avx512/gcc/config/i386/i386-c.c?limit_changes=0&r1=201219&r2=201218&pathrev=201219 Clang and ICC don't seem to have support for this yet. Change-Id: Ic941654a5c56ed110d0e754e436a92dc5deaeb17 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@digia.com>
2013-08-06 23:24:57 +00:00
#ifdef __AVX512ER__
// AVX512 Exponentiation & Reciprocal, Intel Xeon Phi codename "Knights Landing"
" avx512ef"
#endif
#ifdef __AVX512PF__
// AVX512 Prefetch, Intel Xeon Phi codename "Knights Landing"
" avx512pf"
#endif
Add the detection of the compiler macros for more AVX512 features Change-Id: I1d1f2c3857824b17185bc47398299ea7f92c5568 Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
2014-07-30 16:53:01 +00:00
#ifdef __AVX512VL__
SIMD: Remove unused (and unlikely to be ever used) AVX-512 profiles "AVX512MIC" (Many Integrated Cores) is the set of AVX-512 features found on the Intel Xeon Phi coprocessors (codename "Knights Landing"), which is an unlikely architecture for Qt to run on. The two profiles with VL came from study of early GCC code and are no longer applicable. GCC source code now shows both VBMI and IFMA as part of the -march=cannonlake feature set. Change-Id: Iff4151c519c144d580c4fffd153a0f268919fe2c Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2018-06-21 03:28:01 +00:00
// AVX512 Vector Length, Intel Xeon Scalable ("Skylake" server), some Intel Core 7th generation ("Skylake")
Add the detection of the compiler macros for more AVX512 features Change-Id: I1d1f2c3857824b17185bc47398299ea7f92c5568 Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
2014-07-30 16:53:01 +00:00
" avx512vl"
#endif
Update the list of x86 instruction set extensions enabled by GCC From GCC 6's gcc/config/i386.c and i386-c.c Change-Id: Ib306f8f647014b399b87ffff13f1d8a8cfbfa591 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@theqtcompany.com> Reviewed-by: Olivier Goffart (Woboq GmbH) <ogoffart@woboq.com>
2015-07-17 21:19:35 +00:00
#ifdef __AVX512IFMA__
// AVX512 Integer Fused Multiply-Add, Intel processor codename "Cannonlake"
" avx512ifma"
#endif
#ifdef __AVX512VBMI__
// AVX512 Vector Byte Manipulation Instructions, Intel processor codename "Cannonlake"
" avx512vbmi"
#endif
qsimd: add support for new x86 CPU features This adds detection for: VAES, GFNI, AVX512VBMI2, AVX512VNNI, AVX512BITALG, AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS. These features were found in the "Intel® Architecture Instruction Set Extensions and Future Features" manual, revision 30. This commit also adds support for RDPID (already in the main manual) and the Control-flow Enforcement Technology, which appears in a separate Intel paper. This new support was done by adding a new generator script so we don't have to maintain two tables in sync, one in qsimd.cpp with the feature names, and the other in qsimd_p.h. Since we now need a lot more bits, it's no longer worth keeping the two halves of the qt_cpu_features variable mostly similar to the main two CPUID results. This commit goes back to keeping things in order, like we used to prior to commit 6a8251a89b6a61258498f4af1ba7b3d5b7f7096c (Qt 5.6) At the time of this commit, GCC 8 has macros for AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS, AVX512VBMI2 and GFNI. Change-Id: I938b024e38bf4aac9154fffd14f7afae50faaa96 Reviewed-by: Edward Welbourne <edward.welbourne@qt.io> Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2017-09-17 19:39:35 +00:00
#ifdef __AVX512VBMI2__
// AVX512 Vector Byte Manipulation Instructions #2, Intel processor codename "Ice Lake"
" avx512vbmi2"
#endif
#ifdef __AVX512VPOPCNTDQ__
// AVX512 Vector Population Count Double & Quad, Future Intel Xeon Phi processor codename "Knights Mill", Intel processor codename "Ice Lake"
" avx512vpopcntdq"
#endif
#ifdef __AVX5124FMAPS__
// AVX512 4-iteration Fused Multiply Accumulation Packed Single, Future Intel Xeon Phi processor codename "Knights Mill"
" avx5124fmaps"
#endif
#ifdef __AVX5124VNNIW__
// AVX512 4-iteration Vector Neural Network Instructions Word, Future Intel Xeon Phi processor codename "Knights Mill"
" avx5124vnniw"
#endif
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
#ifdef __BMI__
Replace the Intel Haswell and Ivy Bridge codenames with actual names Change-Id: I2a31e96d324dd704e6f96b35ec68c79fd64a090e Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@digia.com> Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
2013-08-06 23:04:50 +00:00
// Bit Manipulation Instructions 1, Intel Core 4th Generation ("Haswell"), AMD "Bulldozer 2"
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
" bmi"
#endif
#ifdef __BMI2__
Replace the Intel Haswell and Ivy Bridge codenames with actual names Change-Id: I2a31e96d324dd704e6f96b35ec68c79fd64a090e Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@digia.com> Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
2013-08-06 23:04:50 +00:00
// Bit Manipulation Instructions 2, Intel Core 4th Generation ("Haswell")
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
" bmi2"
#endif
#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
// cmpxchg16b instruction, Intel Pentium 4 64-bit ("Nocona"), AMD Barcelona (family 10h)
// Notably, this instruction is missing on earlier AMD Athlon 64
" cx16"
#endif
#ifdef __F16C__
Replace the Intel Haswell and Ivy Bridge codenames with actual names Change-Id: I2a31e96d324dd704e6f96b35ec68c79fd64a090e Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@digia.com> Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
2013-08-06 23:04:50 +00:00
// 16-bit floating point conversion, Intel Core 3rd Generation ("Ivy Bridge")
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
" f16c"
#endif
#ifdef __FMA__
Replace the Intel Haswell and Ivy Bridge codenames with actual names Change-Id: I2a31e96d324dd704e6f96b35ec68c79fd64a090e Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@digia.com> Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
2013-08-06 23:04:50 +00:00
// Fused Multiply-Add with 3 arguments, Intel Core 4th Generation ("Haswell"), AMD "Bulldozer 2"
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
// a.k.a. "FMA3"
" fma"
#endif
#ifdef __FMA4__
// Fused Multiply-Add with 4 arguments, AMD "Bulldozer"
" fma4"
#endif
#ifdef __FSGSBASE__
Replace the Intel Haswell and Ivy Bridge codenames with actual names Change-Id: I2a31e96d324dd704e6f96b35ec68c79fd64a090e Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@digia.com> Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
2013-08-06 23:04:50 +00:00
// rdfsgsbase, wrfsgsbase, Intel Core 3rd Generation ("Ivy Bridge")
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
" fsgsbase"
#endif
qsimd: add support for new x86 CPU features This adds detection for: VAES, GFNI, AVX512VBMI2, AVX512VNNI, AVX512BITALG, AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS. These features were found in the "Intel® Architecture Instruction Set Extensions and Future Features" manual, revision 30. This commit also adds support for RDPID (already in the main manual) and the Control-flow Enforcement Technology, which appears in a separate Intel paper. This new support was done by adding a new generator script so we don't have to maintain two tables in sync, one in qsimd.cpp with the feature names, and the other in qsimd_p.h. Since we now need a lot more bits, it's no longer worth keeping the two halves of the qt_cpu_features variable mostly similar to the main two CPUID results. This commit goes back to keeping things in order, like we used to prior to commit 6a8251a89b6a61258498f4af1ba7b3d5b7f7096c (Qt 5.6) At the time of this commit, GCC 8 has macros for AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS, AVX512VBMI2 and GFNI. Change-Id: I938b024e38bf4aac9154fffd14f7afae50faaa96 Reviewed-by: Edward Welbourne <edward.welbourne@qt.io> Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2017-09-17 19:39:35 +00:00
#ifdef __GFNI__
// Galois Field new instructions, Intel processor codename "Ice Lake"
" gfni"
#endif
#ifdef __IBT__
// Indirect Branch Tracking, Intel processor TBA
" ibt"
#endif
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
#ifdef __LWP__
// LWP instructions, AMD "Bulldozer"
" lwp"
#endif
#ifdef __LZCNT__
Replace the Intel Haswell and Ivy Bridge codenames with actual names Change-Id: I2a31e96d324dd704e6f96b35ec68c79fd64a090e Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@digia.com> Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
2013-08-06 23:04:50 +00:00
// Leading-Zero bit count, Intel Core 4th Generation ("Haswell")
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
" lzcnt"
#endif
Remove the mandatory x86-64 features from its feature list The x86-64 architecture mandates support for MMX and SSE2, so we don't need to tell that the compiler generates them. They're implied. This could serve to determine that the user specified no -march= or -m flags that affect the architecture on the CMAKE_CXX_FLAGS, but fails if the compiler does that on its own for this particular target. For example, both for Android and macOS, the minimum feature set is SSSE3 for 32-bit and SSE4.1 for 64-bit. Change-Id: I76216ced393445a4ae2dfffd172a94b17e8a9a37 Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io>
2022-11-24 17:12:28 +00:00
#if defined(__MMX__) && defined(__i386__)
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
// Multimedia Extensions, Pentium MMX, AMD K6-2
" mmx"
#endif
#ifdef __MOVBE__
// Move Big Endian, Intel Atom & "Haswell"
" movbe"
#endif
Update the list of x86 instruction set extensions enabled by GCC From GCC 6's gcc/config/i386.c and i386-c.c Change-Id: Ib306f8f647014b399b87ffff13f1d8a8cfbfa591 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@theqtcompany.com> Reviewed-by: Olivier Goffart (Woboq GmbH) <ogoffart@woboq.com>
2015-07-17 21:19:35 +00:00
#ifdef __MPX__
// Memory Protection Extensions, Intel Core processor codename "Skylake"
" mpx"
#endif
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
#ifdef __NO_SAHF__
// missing SAHF instruction in 64-bit, up to Intel Pentium 4 64-bit ("Nocona"), AMD Athlon FX
// Note: the macro is not defined, so this will never show up
" no-sahf"
#endif
#ifdef __PCLMUL__
// (Packed) Carry-less multiplication, Intel Core-i7 second generation ("Sandy Bridge")
" pclmul"
#endif
#ifdef __POPCNT__
// Population Count (count of set bits), Intel Core-i7 second generation ("Sandy Bridge")
" popcnt"
#endif
Update the list of x86 instruction set extensions enabled by GCC From GCC 6's gcc/config/i386.c and i386-c.c Change-Id: Ib306f8f647014b399b87ffff13f1d8a8cfbfa591 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@theqtcompany.com> Reviewed-by: Olivier Goffart (Woboq GmbH) <ogoffart@woboq.com>
2015-07-17 21:19:35 +00:00
#ifdef __PREFETCHWT1__
// Prefetch data for writing with T1 hint, Intel processor TBA
" prefetchwt1"
#endif
#ifdef __PRFCHW__
// Prefetch data for writing, Intel Core 5th Generation ("Broadwell")
" prfchw"
#endif
qsimd: add support for new x86 CPU features This adds detection for: VAES, GFNI, AVX512VBMI2, AVX512VNNI, AVX512BITALG, AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS. These features were found in the "Intel® Architecture Instruction Set Extensions and Future Features" manual, revision 30. This commit also adds support for RDPID (already in the main manual) and the Control-flow Enforcement Technology, which appears in a separate Intel paper. This new support was done by adding a new generator script so we don't have to maintain two tables in sync, one in qsimd.cpp with the feature names, and the other in qsimd_p.h. Since we now need a lot more bits, it's no longer worth keeping the two halves of the qt_cpu_features variable mostly similar to the main two CPUID results. This commit goes back to keeping things in order, like we used to prior to commit 6a8251a89b6a61258498f4af1ba7b3d5b7f7096c (Qt 5.6) At the time of this commit, GCC 8 has macros for AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS, AVX512VBMI2 and GFNI. Change-Id: I938b024e38bf4aac9154fffd14f7afae50faaa96 Reviewed-by: Edward Welbourne <edward.welbourne@qt.io> Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2017-09-17 19:39:35 +00:00
#ifdef __RDPID__
// Read Processor ID, Intel processors codename "Ice Lake" and "Goldmont Plus"
" rdpid"
#endif
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
#ifdef __RDRND__
Replace the Intel Haswell and Ivy Bridge codenames with actual names Change-Id: I2a31e96d324dd704e6f96b35ec68c79fd64a090e Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@digia.com> Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
2013-08-06 23:04:50 +00:00
// Random number generator, Intel Core 3rd Generation ("Ivy Bridge")
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
" rdrnd"
#endif
Update the list of x86 instruction set extensions enabled by GCC From GCC 6's gcc/config/i386.c and i386-c.c Change-Id: Ib306f8f647014b399b87ffff13f1d8a8cfbfa591 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@theqtcompany.com> Reviewed-by: Olivier Goffart (Woboq GmbH) <ogoffart@woboq.com>
2015-07-17 21:19:35 +00:00
#ifdef __RDSEED__
// Random number generator, Intel Core 5th Generation ("Broadwell")
" rdseed"
#endif
#ifdef __RTM__
// Restricted Transactional Memory, Intel Core 4th Generation ("Haswell")
" rtm"
#endif
Add x86 arch detection support for AVX512 and SHA instructions The flags come from GCC commit 201219: http://gcc.gnu.org/viewcvs/gcc/branches/avx512/gcc/config/i386/i386-c.c?limit_changes=0&r1=201219&r2=201218&pathrev=201219 Clang and ICC don't seem to have support for this yet. Change-Id: Ic941654a5c56ed110d0e754e436a92dc5deaeb17 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@digia.com>
2013-08-06 23:24:57 +00:00
#ifdef __SHA__
qsimd: add support for new x86 CPU features This adds detection for: VAES, GFNI, AVX512VBMI2, AVX512VNNI, AVX512BITALG, AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS. These features were found in the "Intel® Architecture Instruction Set Extensions and Future Features" manual, revision 30. This commit also adds support for RDPID (already in the main manual) and the Control-flow Enforcement Technology, which appears in a separate Intel paper. This new support was done by adding a new generator script so we don't have to maintain two tables in sync, one in qsimd.cpp with the feature names, and the other in qsimd_p.h. Since we now need a lot more bits, it's no longer worth keeping the two halves of the qt_cpu_features variable mostly similar to the main two CPUID results. This commit goes back to keeping things in order, like we used to prior to commit 6a8251a89b6a61258498f4af1ba7b3d5b7f7096c (Qt 5.6) At the time of this commit, GCC 8 has macros for AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS, AVX512VBMI2 and GFNI. Change-Id: I938b024e38bf4aac9154fffd14f7afae50faaa96 Reviewed-by: Edward Welbourne <edward.welbourne@qt.io> Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2017-09-17 19:39:35 +00:00
// SHA-1 and SHA-256 instructions, Intel processors codename "Cannon Lake" and "Goldmont"
Add x86 arch detection support for AVX512 and SHA instructions The flags come from GCC commit 201219: http://gcc.gnu.org/viewcvs/gcc/branches/avx512/gcc/config/i386/i386-c.c?limit_changes=0&r1=201219&r2=201218&pathrev=201219 Clang and ICC don't seem to have support for this yet. Change-Id: Ic941654a5c56ed110d0e754e436a92dc5deaeb17 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@digia.com>
2013-08-06 23:24:57 +00:00
" sha"
#endif
qsimd: add support for new x86 CPU features This adds detection for: VAES, GFNI, AVX512VBMI2, AVX512VNNI, AVX512BITALG, AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS. These features were found in the "Intel® Architecture Instruction Set Extensions and Future Features" manual, revision 30. This commit also adds support for RDPID (already in the main manual) and the Control-flow Enforcement Technology, which appears in a separate Intel paper. This new support was done by adding a new generator script so we don't have to maintain two tables in sync, one in qsimd.cpp with the feature names, and the other in qsimd_p.h. Since we now need a lot more bits, it's no longer worth keeping the two halves of the qt_cpu_features variable mostly similar to the main two CPUID results. This commit goes back to keeping things in order, like we used to prior to commit 6a8251a89b6a61258498f4af1ba7b3d5b7f7096c (Qt 5.6) At the time of this commit, GCC 8 has macros for AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS, AVX512VBMI2 and GFNI. Change-Id: I938b024e38bf4aac9154fffd14f7afae50faaa96 Reviewed-by: Edward Welbourne <edward.welbourne@qt.io> Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2017-09-17 19:39:35 +00:00
#ifdef __SHSTK__
// Shadow stack, Intel processor TBA
" shstk"
#endif
Remove the mandatory x86-64 features from its feature list The x86-64 architecture mandates support for MMX and SSE2, so we don't need to tell that the compiler generates them. They're implied. This could serve to determine that the user specified no -march= or -m flags that affect the architecture on the CMAKE_CXX_FLAGS, but fails if the compiler does that on its own for this particular target. For example, both for Android and macOS, the minimum feature set is SSSE3 for 32-bit and SSE4.1 for 64-bit. Change-Id: I76216ced393445a4ae2dfffd172a94b17e8a9a37 Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io>
2022-11-24 17:12:28 +00:00
#if (defined(__SSE__) && defined(__i386__)) || (defined(_M_IX86_FP) && _M_IX86_FP >= 1 && defined(_M_IX86))
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
// Streaming SIMD Extensions, Intel Pentium III, AMD Athlon
" sse"
#endif
Remove the mandatory x86-64 features from its feature list The x86-64 architecture mandates support for MMX and SSE2, so we don't need to tell that the compiler generates them. They're implied. This could serve to determine that the user specified no -march= or -m flags that affect the architecture on the CMAKE_CXX_FLAGS, but fails if the compiler does that on its own for this particular target. For example, both for Android and macOS, the minimum feature set is SSSE3 for 32-bit and SSE4.1 for 64-bit. Change-Id: I76216ced393445a4ae2dfffd172a94b17e8a9a37 Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io>
2022-11-24 17:12:28 +00:00
#if (defined(__SSE2__) && defined(__i386__)) || (defined(_M_IX86_FP) && _M_IX86_FP >= 2 && defined(_M_IX86))
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
// SSE2, Intel Pentium-M, Intel Pentium 4, AMD Opteron and Athlon 64
" sse2"
#endif
#ifdef __SSE3__
// SSE3, Intel Pentium 4 "Prescott", AMD Athlon 64 rev E
" sse3"
#endif
#ifdef __SSSE3__
Update listing of when SSSE3 and SSE4.1 first became available SSSE3 was first available on the original Intel Core 2 processors, so add the "Merom" codename. SSE4.1 was available on the 45 nm shrink of those processors, codename "Penryn", not on the next architecture. Change-Id: I5fd92db62aa409b7f4e46f9b24d960519177f811 Reviewed-by: Giuseppe D'Angelo <giuseppe.dangelo@kdab.com>
2012-06-12 12:44:24 +00:00
// Supplemental SSE3, Intel Core 2 ("Merom"), AMD "Bulldozer"
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
" ssse3"
#endif
#ifdef __SSE4A__
// SSE4a, AMD Barcelona
" sse4a"
#endif
#ifdef __SSE4_1__
Update listing of when SSSE3 and SSE4.1 first became available SSSE3 was first available on the original Intel Core 2 processors, so add the "Merom" codename. SSE4.1 was available on the 45 nm shrink of those processors, codename "Penryn", not on the next architecture. Change-Id: I5fd92db62aa409b7f4e46f9b24d960519177f811 Reviewed-by: Giuseppe D'Angelo <giuseppe.dangelo@kdab.com>
2012-06-12 12:44:24 +00:00
// SSE 4.1, Intel Core2 45nm shrink ("Penryn"), AMD "Bulldozer"
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
" sse4.1"
#endif
#ifdef __SSE4_2__
// SSE 4.2, Intel Core-i7 ("Nehalem"), AMD "Bulldozer"
" sse4.2"
// Since no processor supports SSE4.2 without 4.1 and since no Intel processor
// supports SSE4a, define "sse4" to indicate SSE4"
" sse4"
#endif
#ifdef __TBM__
// TBM, AMD "Bulldozer"
" tbm"
#endif
#ifdef __XOP__
// XOP, AMD "Bulldozer"
" xop"
#endif
// -- ARM --
Detect NEON on AArch64 The __ARM_NEON is the standard define for NEON instructions support __ARM_NEON__ is only legacy, and specifically not defined in AArch64 builds, which causes us not to detect NEON support there. The NEON assembler files doesn't build with AArch64, so the NEON drawhelper methods must be excluded for now. Change-Id: Ie32f855bde94ee7efd8a8ddb7766c931778e729b Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
2015-11-12 14:50:00 +00:00
#if defined(__ARM_NEON) || defined(__ARM_NEON__)
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
" neon"
#endif
#ifdef __IWMMXT__
" iwmmxt"
#endif
ARMv8: add crc32 feature detection. Change-Id: I3cfac90dfa137d0bf3d124d87262eb2dbb56459c Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
2015-12-11 12:04:46 +00:00
#ifdef __ARM_FEATURE_CRC32
" crc32"
#endif
Add runtime ARM64 AES check Adds runtime CPU detection for Windows and macOS, and switches feature detection of AES to runtime like for x86, So far only on ARM64, since gcc doesn't do function versioning on ARM32, but clang can, so it could be added later. Change-Id: Ibe5d60f48cdae3e366a8ecd6263534ba2b09b131 Reviewed-by: Tor Arne Vestbø <tor.arne.vestbo@qt.io> Reviewed-by: Alexandru Croitor <alexandru.croitor@qt.io>
2021-04-21 09:33:44 +00:00
#ifdef __ARM_FEATURE_CRYPTO
" crypto"
#endif
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
// -- SPARC --
#ifdef __VIS__
" vis"
# if __VIS__ >= 0x200
" vis2"
# endif
# if __VIS__ >= 0x300
" vis3"
# endif
#endif
// -- MIPS --
mips: Autodetect MIPS DSP rev1 and rev2 instructionset Not every MIPS SoC has the DSP extensions, auto-detect them by using builtin GCC functions. Check for the DSP macros and add the result for rev1 and rev2 to the cpufeatures. Change-Id: I3d6c950f170f102514c43b349f9a23ee796d801a Reviewed-by: Girish Ramakrishnan <girish.1.ramakrishnan@nokia.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
2012-07-20 13:03:56 +00:00
# if __mips_dsp
" dsp"
# endif
# if __mips_dspr2
" dspr2"
# endif
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
// -- POWER, PowerPC --
#ifdef __ALTIVEC__
" altivec"
PowerPC: Add detection of SPE (found on e500) and VSX Poky (Yocto's reference distro) has a special build for the e500v2, so I'm guessing this ABI is somewhat important. Change-Id: I14839ba5678944c2864bffff14176c4d61b8799f Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@theqtcompany.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
2015-11-17 07:21:24 +00:00
#endif
#ifdef __SPE__
" spe"
#endif
#ifdef __VSX__
" vsx"
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
#endif
"";
Make build ABI available as qmake variable This is needed to encode the correct ABI into the generated qml caches. It is identical with the return value of QSysInfo::buildAbi(). Change-Id: I2d581b22326da4220f412ab4f517156f4ba31897 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@qt.io> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com> Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2017-03-27 08:54:59 +00:00
extern const char msg3[];
const char msg3[] = "==Qt=magic=Qt== Build-ABI:" ARCH_FULL;
Improve the architecture-detection mechanism For the Unix part, this now obeys the -v option, printing the full command-line it used to compile, allowing testers to identify why something went wrong. Unfortunately, it requires a full compilation cycle, instead of just preprocessing. Just one more among the many on Unix, but maybe a noticeable slow-down on Windows. Change-Id: I654b70d99887e04c96731a5b91be9ad555e4d8fe Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com> Reviewed-by: Girish Ramakrishnan <girish.1.ramakrishnan@nokia.com>
2012-03-27 17:43:45 +00:00
int main()
{
puts(msg);
Record the sub-architecture (CPU features enabled in the compiler) If the system's compiler has extra features on top of the base settings enabled or if the mkspec or $CXXFLAGS variable included some, record them. This will allow us to choose whether or not to use our own special compilers, based on whether the system default compiler contains it or not. Change-Id: I87cada9fab4cfa58846a831d0a7c7b50d8fa87fd Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com>
2011-12-31 22:40:49 +00:00
puts(msg2);
Make build ABI available as qmake variable This is needed to encode the correct ABI into the generated qml caches. It is identical with the return value of QSysInfo::buildAbi(). Change-Id: I2d581b22326da4220f412ab4f517156f4ba31897 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@qt.io> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com> Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2017-03-27 08:54:59 +00:00
puts(msg3);
Improve the architecture-detection mechanism For the Unix part, this now obeys the -v option, printing the full command-line it used to compile, allowing testers to identify why something went wrong. Unfortunately, it requires a full compilation cycle, instead of just preprocessing. Just one more among the many on Unix, but maybe a noticeable slow-down on Windows. Change-Id: I654b70d99887e04c96731a5b91be9ad555e4d8fe Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@nokia.com> Reviewed-by: Girish Ramakrishnan <girish.1.ramakrishnan@nokia.com>
2012-03-27 17:43:45 +00:00
}
Reference in New Issue Copy Permalink