AuroraMiddleware/v8
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity
43f2a3d654
v8/test/cctest/test-disasm-x64.cc

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

985 lines
33 KiB
C++
Raw Normal View History

Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
// Copyright 2011 the V8 project authors. All rights reserved.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
// * Neither the name of Google Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#include <stdlib.h>
Use full include paths everywhere - this avoids using relative include paths which are forbidden by the style guide - makes the code more readable since it's clear which header is meant - allows for starting to use checkdeps BUG=none R=jkummerow@chromium.org, danno@chromium.org LOG=n Review URL: https://codereview.chromium.org/304153016 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21625 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-06-03 08:12:43 +00:00
#include "src/v8.h"
Simplify IC interfaces BUG= Review URL: https://codereview.chromium.org/1865873002 Cr-Commit-Position: refs/heads/master@{#35301}
2016-04-06 13:36:49 +00:00
#include "src/code-factory.h"
Debugger: move implementation to a separate folder. R=cbruni@chromium.org Review URL: https://codereview.chromium.org/1265923002 Cr-Commit-Position: refs/heads/master@{#29951}
2015-07-31 11:07:50 +00:00
#include "src/debug/debug.h"
Use full include paths everywhere - this avoids using relative include paths which are forbidden by the style guide - makes the code more readable since it's clear which header is meant - allows for starting to use checkdeps BUG=none R=jkummerow@chromium.org, danno@chromium.org LOG=n Review URL: https://codereview.chromium.org/304153016 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21625 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-06-03 08:12:43 +00:00
#include "src/disasm.h"
#include "src/disassembler.h"
[iwyu] Do not include frames.h in macro assemblers. Since frames.h no longer defines basic register types like RegList, it is no longer necessary to include it in the macro assemblers. Next step: split out frame-constants.h from frames.h so that it will be possible to get frame constants without include the stackwalking logic, which needs objects.h. R=mstarzinger@chromium.org Bug: Change-Id: Ia12d3c8a8d46a73106c3c90bcb4b470c85f1eaa7 Reviewed-on: https://chromium-review.googlesource.com/597788 Commit-Queue: Ben Titzer <titzer@chromium.org> Reviewed-by: Yang Guo <yangguo@chromium.org> Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#47114}
2017-08-02 13:15:04 +00:00
#include "src/frames-inl.h"
Use full include paths everywhere - this avoids using relative include paths which are forbidden by the style guide - makes the code more readable since it's clear which header is meant - allows for starting to use checkdeps BUG=none R=jkummerow@chromium.org, danno@chromium.org LOG=n Review URL: https://codereview.chromium.org/304153016 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21625 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-06-03 08:12:43 +00:00
#include "src/macro-assembler.h"
[iwyu] Pre-work for removing unallowed include macro-assembler.h -> assembler-inl.h BUG=v8:5294 Change-Id: If45f25aae8de526027b7851cb4efe0ccf4a7c4b1 Reviewed-on: https://chromium-review.googlesource.com/444226 Commit-Queue: Marja Hölttä <marja@chromium.org> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Reviewed-by: Andreas Haas <ahaas@chromium.org> Reviewed-by: Yang Guo <yangguo@chromium.org> Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#43388}
2017-02-23 11:46:29 +00:00
#include "src/objects-inl.h"
Use full include paths everywhere - this avoids using relative include paths which are forbidden by the style guide - makes the code more readable since it's clear which header is meant - allows for starting to use checkdeps BUG=none R=jkummerow@chromium.org, danno@chromium.org LOG=n Review URL: https://codereview.chromium.org/304153016 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@21625 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-06-03 08:12:43 +00:00
#include "test/cctest/cctest.h"
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
Start preparing test/cctest for jumbo compilation * Avoid "using namespace" statements, which trigger clang's -Wheader-hygiene warnings in jumbo builds. * Undefine created macros at the end of source files. BUG=chromium:746958 Change-Id: I5d25432c314437f607b0e1be22765a6764267ba6 Reviewed-on: https://chromium-review.googlesource.com/610962 Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Mostyn Bramley-Moore <mostynb@opera.com> Cr-Commit-Position: refs/heads/master@{#47347}
2017-08-11 11:22:28 +00:00
namespace v8 {
namespace internal {
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
#define __ assm.
TEST(DisasmX64) {
Unify the way cctest initalizes the VM for each test case. R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/13483017 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@14199 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-04-10 08:29:39 +00:00
CcTest::InitializeVM();
Print properly signed displacement in disassembler. R=titzer@chromium.org BUG= Review URL: https://codereview.chromium.org/178193028 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@19667 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-05 09:28:26 +00:00
Isolate* isolate = CcTest::i_isolate();
HandleScope scope(isolate);
[x64] supplement SSE insturctions for SIMD.js Both legacy and AVX versions BUG= Review-Url: https://codereview.chromium.org/2328843003 Cr-Commit-Position: refs/heads/master@{#39327}
2016-09-12 06:24:06 +00:00
v8::internal::byte buffer[8192];
[turbofan] Thread through AssemblerOptions This CL surfaces AssemblerOptions to CodeAssembler::GenerateCode and to pipeline methods. To allow forward declaring AssemblerOptions, AssemblerBase::Options was moved out of the AssemblerBase class. Bug: v8:6666 Change-Id: If9fc50d3d4767bb5dd39a0c3b6e094021f4cae2b Reviewed-on: https://chromium-review.googlesource.com/1127039 Commit-Queue: Sigurd Schneider <sigurds@chromium.org> Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Reviewed-by: Jakob Gruber <jgruber@chromium.org> Cr-Commit-Position: refs/heads/master@{#54286}
2018-07-06 08:58:43 +00:00
Assembler assm(AssemblerOptions{}, buffer, sizeof buffer);
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
// Short immediate instructions
__ addq(rax, Immediate(12345678));
Introduce andp, notp, orp and xorp for x64 port R=verwaest@chromium.org Review URL: https://codereview.chromium.org/205343013 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20276 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-26 12:15:35 +00:00
__ orq(rax, Immediate(12345678));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ subq(rax, Immediate(12345678));
Introduce andp, notp, orp and xorp for x64 port R=verwaest@chromium.org Review URL: https://codereview.chromium.org/205343013 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20276 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-26 12:15:35 +00:00
__ xorq(rax, Immediate(12345678));
__ andq(rax, Immediate(12345678));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
// ---- This one caused crash
__ movq(rbx, Operand(rsp, rcx, times_2, 0)); // [rsp+rcx*4]
// ---- All instructions that I can think of
__ addq(rdx, rbx);
__ addq(rdx, Operand(rbx, 0));
__ addq(rdx, Operand(rbx, 16));
__ addq(rdx, Operand(rbx, 1999));
Print properly signed displacement in disassembler. R=titzer@chromium.org BUG= Review URL: https://codereview.chromium.org/178193028 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@19667 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-05 09:28:26 +00:00
__ addq(rdx, Operand(rbx, -4));
__ addq(rdx, Operand(rbx, -1999));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ addq(rdx, Operand(rsp, 0));
__ addq(rdx, Operand(rsp, 16));
__ addq(rdx, Operand(rsp, 1999));
Print properly signed displacement in disassembler. R=titzer@chromium.org BUG= Review URL: https://codereview.chromium.org/178193028 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@19667 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-05 09:28:26 +00:00
__ addq(rdx, Operand(rsp, -4));
__ addq(rdx, Operand(rsp, -1999));
__ nop();
__ addq(rsi, Operand(rcx, times_4, 0));
__ addq(rsi, Operand(rcx, times_4, 24));
__ addq(rsi, Operand(rcx, times_4, -4));
__ addq(rsi, Operand(rcx, times_4, -1999));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ nop();
__ addq(rdi, Operand(rbp, rcx, times_4, 0));
__ addq(rdi, Operand(rbp, rcx, times_4, 12));
Print properly signed displacement in disassembler. R=titzer@chromium.org BUG= Review URL: https://codereview.chromium.org/178193028 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@19667 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-05 09:28:26 +00:00
__ addq(rdi, Operand(rbp, rcx, times_4, -8));
__ addq(rdi, Operand(rbp, rcx, times_4, -3999));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ addq(Operand(rbp, rcx, times_4, 12), Immediate(12));
[turbofan] Further optimize DataView accesses. This adds support for unaligned load/store access to the DataView backing store and uses byteswap operations to fix up the endianess when necessary. This changes the Word32ReverseBytes operator to be a required operator and adds the missing support on the Intel and ARM platforms (on 64-bit platforms the Word64ReverseBytes operator is also mandatory now). This further improves the performance on the dataviewperf.js test mentioned in the tracking bug by up to 40%, and at the same time reduces the code complexity in the EffectControlLinearizer. Bug: chromium:225811 Change-Id: I7c1ec826faf46a144a5a9068f8f815a5fd040997 Reviewed-on: https://chromium-review.googlesource.com/1174252 Reviewed-by: Sigurd Schneider <sigurds@chromium.org> Commit-Queue: Benedikt Meurer <bmeurer@chromium.org> Cr-Commit-Position: refs/heads/master@{#55111}
2018-08-14 08:39:05 +00:00
__ bswapl(rax);
__ bswapq(rdi);
[turbofan] Turn Math.clz32 into an inlinable builtin. R=dcarney@chromium.org, yangguo@chromium.org BUG=v8:3952 LOG=n Review URL: https://codereview.chromium.org/1021183002 Cr-Commit-Position: refs/heads/master@{#27329}
2015-03-20 08:37:20 +00:00
__ bsrl(rax, r15);
__ bsrl(r9, Operand(rcx, times_8, 91919));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ nop();
__ addq(rbx, Immediate(12));
__ nop();
__ nop();
Introduce andp, notp, orp and xorp for x64 port R=verwaest@chromium.org Review URL: https://codereview.chromium.org/205343013 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20276 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-26 12:15:35 +00:00
__ andq(rdx, Immediate(3));
__ andq(rdx, Operand(rsp, 4));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ cmpq(rdx, Immediate(3));
__ cmpq(rdx, Operand(rsp, 4));
__ cmpq(Operand(rbp, rcx, times_4, 0), Immediate(1000));
__ cmpb(rbx, Operand(rbp, rcx, times_2, 0));
__ cmpb(Operand(rbp, rcx, times_2, 0), rbx);
Introduce andp, notp, orp and xorp for x64 port R=verwaest@chromium.org Review URL: https://codereview.chromium.org/205343013 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20276 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-26 12:15:35 +00:00
__ orq(rdx, Immediate(3));
__ xorq(rdx, Immediate(3));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ nop();
Introduce addps/subps/mulps/divps for IA32/X64 BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/60093005 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17842 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-11-18 15:24:41 +00:00
__ cpuid();
x64: Make sure that the upper half of a 64bit register contains 0 for int32 values. BUG=360611 LOG=y R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/225393005 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20664 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-04-11 06:32:06 +00:00
__ movsxbl(rdx, Operand(rcx, 0));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ movsxbq(rdx, Operand(rcx, 0));
x64: Make sure that the upper half of a 64bit register contains 0 for int32 values. BUG=360611 LOG=y R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/225393005 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20664 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-04-11 06:32:06 +00:00
__ movsxwl(rdx, Operand(rcx, 0));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ movsxwq(rdx, Operand(rcx, 0));
__ movzxbl(rdx, Operand(rcx, 0));
__ movzxwl(rdx, Operand(rcx, 0));
__ movzxbq(rdx, Operand(rcx, 0));
__ movzxwq(rdx, Operand(rcx, 0));
__ nop();
Introduce addp, idivp, imulp and subp for x64 port R=verwaest@chromium.org Review URL: https://codereview.chromium.org/196893003 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20140 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-21 02:42:10 +00:00
__ imulq(rdx, rcx);
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ shld(rdx, rcx);
__ shrd(rdx, rcx);
[turbofan] support all shift operands on x64 R=bmeurer@chromium.org BUG= Review URL: https://codereview.chromium.org/615223005 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24388 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-10-02 09:08:09 +00:00
__ shlq(Operand(rdi, rax, times_4, 100), Immediate(1));
__ shlq(Operand(rdi, rax, times_4, 100), Immediate(6));
__ shlq(Operand(r15, 0), Immediate(1));
__ shlq(Operand(r15, 0), Immediate(6));
__ shlq_cl(Operand(r15, 0));
__ shlq_cl(Operand(r15, 0));
__ shlq_cl(Operand(rdi, rax, times_4, 100));
__ shlq_cl(Operand(rdi, rax, times_4, 100));
__ shlq(rdx, Immediate(1));
__ shlq(rdx, Immediate(6));
__ shll(Operand(rdi, rax, times_4, 100), Immediate(1));
__ shll(Operand(rdi, rax, times_4, 100), Immediate(6));
__ shll(Operand(r15, 0), Immediate(1));
__ shll(Operand(r15, 0), Immediate(6));
__ shll_cl(Operand(r15, 0));
__ shll_cl(Operand(r15, 0));
__ shll_cl(Operand(rdi, rax, times_4, 100));
__ shll_cl(Operand(rdi, rax, times_4, 100));
__ shll(rdx, Immediate(1));
__ shll(rdx, Immediate(6));
Reland^2 "[Liftoff] Implement f32.copysign and f64.copysign" This is a reland of 6afe7d18154c20b421faf4fe14238c6df0f68a12. The reason for the revert is fixed in https://crrev.com/c/1219633. Original change's description: > [Liftoff] Implement f32.copysign and f64.copysign > > These are two of the few missing instructions. This CL implements them > for ia32 and x64, and bails out on other platforms. > On x64, we are using the BTR instruction since we cannot have 64-bit > immediates. > > Drive-by: Fix naming of existing bt/bts instructions on x64. > > R=titzer@chromium.org > > Bug: v8:6600 > Change-Id: Ib8532ca811160cd61f4ba7c06b04ce093861c872 > Reviewed-on: https://chromium-review.googlesource.com/1174383 > Commit-Queue: Clemens Hammacher <clemensh@chromium.org> > Reviewed-by: Ben Titzer <titzer@chromium.org> > Cr-Commit-Position: refs/heads/master@{#55780} Bug: v8:6600 Change-Id: Ie14ba3a14848ba8e67f97e66d3379178f35dea40 TBR=titzer@chromium.org Change-Id: Ie14ba3a14848ba8e67f97e66d3379178f35dea40 Reviewed-on: https://chromium-review.googlesource.com/1219693 Reviewed-by: Clemens Hammacher <clemensh@chromium.org> Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Cr-Commit-Position: refs/heads/master@{#55817}
2018-09-12 07:29:11 +00:00
__ btq(Operand(rdx, 0), rcx);
__ btsq(Operand(rdx, 0), rcx);
__ btsq(Operand(rbx, rcx, times_4, 0), rcx);
__ btsq(rcx, Immediate(13));
__ btrq(rcx, Immediate(13));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ nop();
Introduce Push and Pop macro instructions for x64 R=verwaest@chromium.org Review URL: https://codereview.chromium.org/199903002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20049 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-19 08:59:04 +00:00
__ pushq(Immediate(12));
__ pushq(Immediate(23456));
__ pushq(rcx);
__ pushq(rsi);
__ pushq(Operand(rbp, JavaScriptFrameConstants::kFunctionOffset));
__ pushq(Operand(rbx, rcx, times_4, 0));
__ pushq(Operand(rbx, rcx, times_4, 0));
__ pushq(Operand(rbx, rcx, times_4, 10000));
__ popq(rdx);
__ popq(rax);
__ popq(Operand(rbx, rcx, times_4, 0));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ nop();
__ addq(rdx, Operand(rsp, 16));
__ addq(rdx, rcx);
__ movb(rdx, Operand(rcx, 0));
__ movb(rcx, Immediate(6));
__ movb(Operand(rsp, 16), rdx);
__ movw(Operand(rsp, 16), rdx);
__ nop();
__ movsxwq(rdx, Operand(rsp, 12));
__ movsxbq(rdx, Operand(rsp, 12));
__ movsxlq(rdx, Operand(rsp, 12));
__ movzxwq(rdx, Operand(rsp, 12));
__ movzxbq(rdx, Operand(rsp, 12));
__ nop();
__ movq(rdx, Immediate(1234567));
__ movq(rdx, Operand(rsp, 12));
__ movq(Operand(rbx, rcx, times_4, 10000), Immediate(12345));
__ movq(Operand(rbx, rcx, times_4, 10000), rdx);
__ nop();
__ decb(rdx);
__ decb(Operand(rax, 10));
__ decb(Operand(rbx, rcx, times_4, 10000));
__ decq(rdx);
__ cdq();
__ nop();
__ idivq(rdx);
[turbofan] Also optimize unsigned division by constant. TEST=cctest,mjsunit,unittests R=jarin@chromium.org Review URL: https://codereview.chromium.org/697663003 Cr-Commit-Position: refs/heads/master@{#25061} git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25061 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-11-03 10:04:37 +00:00
__ mull(rdx);
__ mulq(rdx);
Introduce cmpp, decp, incp, negp, sbbp and testp for x64 port R=verwaest@chromium.org Review URL: https://codereview.chromium.org/207833002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20260 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-26 01:13:09 +00:00
__ negq(rdx);
Introduce andp, notp, orp and xorp for x64 port R=verwaest@chromium.org Review URL: https://codereview.chromium.org/205343013 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20276 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-26 12:15:35 +00:00
__ notq(rdx);
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ testq(Operand(rbx, rcx, times_4, 10000), rdx);
Introduce addp, idivp, imulp and subp for x64 port R=verwaest@chromium.org Review URL: https://codereview.chromium.org/196893003 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20140 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-21 02:42:10 +00:00
__ imulq(rdx, rcx, Immediate(12));
__ imulq(rdx, rcx, Immediate(1000));
fix imul(reg, op, imm) emission on x64 R=bmeurer@chromium.org BUG= Review URL: https://codereview.chromium.org/619903005 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24395 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-10-02 12:22:36 +00:00
__ imulq(rdx, Operand(rbx, rcx, times_4, 10000));
__ imulq(rdx, Operand(rbx, rcx, times_4, 10000), Immediate(12));
[x64] three operand imul supports first operand in memory location R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/596643003 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24199 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-09-25 06:37:23 +00:00
__ imulq(rdx, Operand(rbx, rcx, times_4, 10000), Immediate(1000));
fix imul(reg, op, imm) emission on x64 R=bmeurer@chromium.org BUG= Review URL: https://codereview.chromium.org/619903005 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24395 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-10-02 12:22:36 +00:00
__ imull(r15, rcx, Immediate(12));
__ imull(r15, rcx, Immediate(1000));
__ imull(r15, Operand(rbx, rcx, times_4, 10000));
__ imull(r15, Operand(rbx, rcx, times_4, 10000), Immediate(12));
__ imull(r15, Operand(rbx, rcx, times_4, 10000), Immediate(1000));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ incq(rdx);
__ incq(Operand(rbx, rcx, times_4, 10000));
Introduce Push and Pop macro instructions for x64 R=verwaest@chromium.org Review URL: https://codereview.chromium.org/199903002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20049 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-19 08:59:04 +00:00
__ pushq(Operand(rbx, rcx, times_4, 10000));
__ popq(Operand(rbx, rcx, times_4, 10000));
Print properly signed displacement in disassembler. R=titzer@chromium.org BUG= Review URL: https://codereview.chromium.org/178193028 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@19667 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-05 09:28:26 +00:00
// TODO(mstarzinger): The following is protected.
// __ jmp(Operand(rbx, rcx, times_4, 10000));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
Introduce leap, movzxbp, movzxwp, repmovsp and xchgp for x64 port R=verwaest@chromium.org Review URL: https://codereview.chromium.org/211413008 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20273 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-26 11:17:53 +00:00
__ leaq(rdx, Operand(rbx, rcx, times_4, 10000));
Introduce andp, notp, orp and xorp for x64 port R=verwaest@chromium.org Review URL: https://codereview.chromium.org/205343013 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20276 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-26 12:15:35 +00:00
__ orq(rdx, Immediate(12345));
__ orq(rdx, Operand(rbx, rcx, times_4, 10000));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ nop();
Introduce rolp, rorp, rclp, rcrp, shlp, shrp and sarp for x64 port R=verwaest@chromium.org Review URL: https://codereview.chromium.org/214493002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20320 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-28 04:55:00 +00:00
__ rclq(rdx, Immediate(1));
__ rclq(rdx, Immediate(7));
__ rcrq(rdx, Immediate(1));
__ rcrq(rdx, Immediate(7));
__ sarq(rdx, Immediate(1));
__ sarq(rdx, Immediate(6));
__ sarq_cl(rdx);
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ sbbq(rdx, rbx);
__ shld(rdx, rbx);
Introduce rolp, rorp, rclp, rcrp, shlp, shrp and sarp for x64 port R=verwaest@chromium.org Review URL: https://codereview.chromium.org/214493002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20320 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-28 04:55:00 +00:00
__ shlq(rdx, Immediate(1));
__ shlq(rdx, Immediate(6));
__ shlq_cl(rdx);
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ shrd(rdx, rbx);
Introduce rolp, rorp, rclp, rcrp, shlp, shrp and sarp for x64 port R=verwaest@chromium.org Review URL: https://codereview.chromium.org/214493002 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20320 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-28 04:55:00 +00:00
__ shrq(rdx, Immediate(1));
__ shrq(rdx, Immediate(7));
__ shrq_cl(rdx);
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
// Immediates
__ addq(rbx, Immediate(12));
__ addq(Operand(rdx, rcx, times_4, 10000), Immediate(12));
Introduce andp, notp, orp and xorp for x64 port R=verwaest@chromium.org Review URL: https://codereview.chromium.org/205343013 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20276 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-26 12:15:35 +00:00
__ andq(rbx, Immediate(12345));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ cmpq(rbx, Immediate(12345));
__ cmpq(rbx, Immediate(12));
__ cmpq(Operand(rdx, rcx, times_4, 10000), Immediate(12));
__ cmpb(rax, Immediate(100));
Introduce andp, notp, orp and xorp for x64 port R=verwaest@chromium.org Review URL: https://codereview.chromium.org/205343013 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20276 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-26 12:15:35 +00:00
__ orq(rbx, Immediate(12345));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ subq(rbx, Immediate(12));
__ subq(Operand(rdx, rcx, times_4, 10000), Immediate(12));
Introduce andp, notp, orp and xorp for x64 port R=verwaest@chromium.org Review URL: https://codereview.chromium.org/205343013 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20276 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-26 12:15:35 +00:00
__ xorq(rbx, Immediate(12345));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
Introduce addp, idivp, imulp and subp for x64 port R=verwaest@chromium.org Review URL: https://codereview.chromium.org/196893003 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20140 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-21 02:42:10 +00:00
__ imulq(rdx, rcx, Immediate(12));
__ imulq(rdx, rcx, Immediate(1000));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ cld();
__ subq(rdx, Operand(rbx, rcx, times_4, 10000));
__ subq(rdx, rbx);
__ testq(rdx, Immediate(12345));
__ testq(Operand(rbx, rcx, times_8, 10000), rdx);
__ testb(Operand(rcx, rbx, times_2, 1000), rdx);
__ testb(Operand(rax, -20), Immediate(0x9A));
__ nop();
Introduce andp, notp, orp and xorp for x64 port R=verwaest@chromium.org Review URL: https://codereview.chromium.org/205343013 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20276 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-26 12:15:35 +00:00
__ xorq(rdx, Immediate(12345));
__ xorq(rdx, Operand(rbx, rcx, times_8, 10000));
Add pshufw instruction, fix inconsistencies with pextrw instruction. Current implementation of the pextrw instruction is the legacy SSE2 instruction in the assembler (66 0F C5), and SSE4 implementation(66 0F 3A 15) in disasm-x64.cc, this causes incorrect instruction encodings to be printed when using --print-code flag for debug, in this case, causes over flow of bytes, and subsequent instructions to be incorrectly disassembled. Fixing to use SSE4 encodings in the assembler cosistent with pextrb, pextrd. R=bbudge@chromium.org, mtrofin@chromium.org Review-Url: https://codereview.chromium.org/2771513002 Cr-Commit-Position: refs/heads/master@{#44047}
2017-03-22 20:49:27 +00:00
__ pshufw(xmm5, xmm1, 3);
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ hlt();
__ int3();
__ ret(0);
__ ret(8);
// Calls
Label L1, L2;
__ bind(&L1);
__ nop();
__ call(&L1);
__ call(&L2);
__ nop();
__ bind(&L2);
Print properly signed displacement in disassembler. R=titzer@chromium.org BUG= Review URL: https://codereview.chromium.org/178193028 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@19667 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-05 09:28:26 +00:00
// TODO(mstarzinger): The following is protected.
// __ call(Operand(rbx, rcx, times_4, 10000));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ nop();
Reland "[builtins] Remove Builtins::Name() accessors" This is a reland of 2f79e035602640b9e2b63e3cbdf07c565df7be04 Original change's description: > [builtins] Remove Builtins::Name() accessors > > Instead of auto-generating the Name() convenience accessor, use a macro to > avoid wasting code space. > > BUILTIN_CODE(isolate, Name) > > expands to > > isolate->builtins()->builtin_handle(Builtins::kName); > > This reduces the size of libv8.so by 134,752 bytes on a x64 release build. > > Bug: v8:6624 > Cq-Include-Trybots: master.tryserver.chromium.linux:linux_chromium_rel_ng > Change-Id: Idff7ee5c45e344e73412c0f47e92553c7c7ff75f > Reviewed-on: https://chromium-review.googlesource.com/593607 > Reviewed-by: Andreas Haas <ahaas@chromium.org> > Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> > Commit-Queue: Jakob Gruber <jgruber@chromium.org> > Cr-Commit-Position: refs/heads/master@{#47010} TBR=bmeurer@chromium.org,ahaas@chromium.org Bug: v8:6624 Change-Id: I4733731e56dc8873ee06c2b36cac1918c0a658b2 Reviewed-on: https://chromium-review.googlesource.com/594087 Commit-Queue: Jakob Gruber <jgruber@chromium.org> Reviewed-by: Andreas Haas <ahaas@chromium.org> Reviewed-by: Jakob Gruber <jgruber@chromium.org> Cr-Commit-Position: refs/heads/master@{#47037}
2017-08-01 08:15:46 +00:00
Handle<Code> ic = BUILTIN_CODE(isolate, LoadIC);
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ call(ic, RelocInfo::CODE_TARGET);
__ nop();
__ nop();
__ jmp(&L1);
Print properly signed displacement in disassembler. R=titzer@chromium.org BUG= Review URL: https://codereview.chromium.org/178193028 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@19667 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-05 09:28:26 +00:00
// TODO(mstarzinger): The following is protected.
// __ jmp(Operand(rbx, rcx, times_4, 10000));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ jmp(ic, RelocInfo::CODE_TARGET);
__ nop();
Label Ljcc;
__ nop();
// long jumps
__ j(overflow, &Ljcc);
__ j(no_overflow, &Ljcc);
__ j(below, &Ljcc);
__ j(above_equal, &Ljcc);
__ j(equal, &Ljcc);
__ j(not_equal, &Ljcc);
__ j(below_equal, &Ljcc);
__ j(above, &Ljcc);
__ j(sign, &Ljcc);
__ j(not_sign, &Ljcc);
__ j(parity_even, &Ljcc);
__ j(parity_odd, &Ljcc);
__ j(less, &Ljcc);
__ j(greater_equal, &Ljcc);
__ j(less_equal, &Ljcc);
__ j(greater, &Ljcc);
__ nop();
__ bind(&Ljcc);
// short jumps
__ j(overflow, &Ljcc);
__ j(no_overflow, &Ljcc);
__ j(below, &Ljcc);
__ j(above_equal, &Ljcc);
__ j(equal, &Ljcc);
__ j(not_equal, &Ljcc);
__ j(below_equal, &Ljcc);
__ j(above, &Ljcc);
__ j(sign, &Ljcc);
__ j(not_sign, &Ljcc);
__ j(parity_even, &Ljcc);
__ j(parity_odd, &Ljcc);
__ j(less, &Ljcc);
__ j(greater_equal, &Ljcc);
__ j(less_equal, &Ljcc);
__ j(greater, &Ljcc);
// 0xD9 instructions
__ nop();
__ fld(1);
__ fld1();
__ fldz();
__ fldpi();
__ fabs();
__ fchs();
__ fprem();
__ fprem1();
__ fincstp();
__ ftst();
__ fxch(3);
__ fld_s(Operand(rbx, rcx, times_4, 10000));
__ fstp_s(Operand(rbx, rcx, times_4, 10000));
__ ffree(3);
__ fld_d(Operand(rbx, rcx, times_4, 10000));
__ fstp_d(Operand(rbx, rcx, times_4, 10000));
__ nop();
__ fild_s(Operand(rbx, rcx, times_4, 10000));
__ fistp_s(Operand(rbx, rcx, times_4, 10000));
__ fild_d(Operand(rbx, rcx, times_4, 10000));
__ fistp_d(Operand(rbx, rcx, times_4, 10000));
__ fnstsw_ax();
__ nop();
__ fadd(3);
__ fsub(3);
__ fmul(3);
__ fdiv(3);
__ faddp(3);
__ fsubp(3);
__ fmulp(3);
__ fdivp(3);
__ fcompp();
__ fwait();
[x64] add disasm for two fp instructions BUG= R=yangguo@chromium.org Review URL: https://codereview.chromium.org/146583002 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@19022 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-02-03 08:13:12 +00:00
__ frndint();
__ fninit();
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ nop();
Introduce andps for IA32/X64 replace andpd and pand in Math.abs BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/44153002 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17413 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-10-28 10:38:40 +00:00
// SSE instruction
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
{
Introduce addps/subps/mulps/divps for IA32/X64 BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/60093005 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17842 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-11-18 15:24:41 +00:00
// Move operation
Introduce andps for IA32/X64 replace andpd and pand in Math.abs BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/44153002 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17413 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-10-28 10:38:40 +00:00
__ cvttss2si(rdx, Operand(rbx, rcx, times_4, 10000));
__ cvttss2si(rdx, xmm1);
[turbofan] IA: TruncateFloat64ToFloat32 supports mem operand BUG= R=dcarney@chromium.org Review URL: https://codereview.chromium.org/639283003 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24541 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-10-13 07:12:57 +00:00
__ cvtsd2ss(xmm0, xmm1);
__ cvtsd2ss(xmm0, Operand(rbx, rcx, times_4, 10000));
[x64] Add assembly/disassembly for left-over SIMD ops Change-Id: I55d15fd15cc714732139e4bf12bd75f21f922048 Reviewed-on: https://chromium-review.googlesource.com/1174013 Reviewed-by: Ben Titzer <titzer@chromium.org> Reviewed-by: Bill Budge <bbudge@chromium.org> Commit-Queue: Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/master@{#55174}
2018-08-14 19:38:14 +00:00
__ cvttps2dq(xmm0, xmm1);
__ cvttps2dq(xmm0, Operand(rbx, rcx, times_4, 10000));
Introduce andps for IA32/X64 replace andpd and pand in Math.abs BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/44153002 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17413 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-10-28 10:38:40 +00:00
__ movaps(xmm0, xmm1);
[x64] Implement movdqu in the disassembler I also added a test for movdqa, which was already implemented. R=bmeurer@chromium.org Change-Id: I6dd5cba072f1439dcdfb5f975de116e4534c7581 Reviewed-on: https://chromium-review.googlesource.com/832466 Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Commit-Queue: Andreas Haas <ahaas@chromium.org> Cr-Commit-Position: refs/heads/master@{#50175}
2017-12-18 14:32:23 +00:00
__ movdqa(xmm0, Operand(rsp, 12));
__ movdqa(Operand(rsp, 12), xmm0);
__ movdqu(xmm0, Operand(rsp, 12));
__ movdqu(Operand(rsp, 12), xmm0);
[x64] Fix REX prefix in shufps BUG= Review-Url: https://codereview.chromium.org/2652793004 Cr-Commit-Position: refs/heads/master@{#42673}
2017-01-26 01:38:17 +00:00
__ shufps(xmm0, xmm9, 0x0);
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
Introduce addps/subps/mulps/divps for IA32/X64 BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/60093005 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17842 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-11-18 15:24:41 +00:00
// logic operation
Introduce andps for IA32/X64 replace andpd and pand in Math.abs BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/44153002 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17413 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-10-28 10:38:40 +00:00
__ andps(xmm0, xmm1);
Introduce addps/subps/mulps/divps for IA32/X64 BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/60093005 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17842 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-11-18 15:24:41 +00:00
__ andps(xmm0, Operand(rbx, rcx, times_4, 10000));
Introduce orps for IA32/X64 BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/53573004 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17479 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-11-05 12:04:46 +00:00
__ orps(xmm0, xmm1);
Print properly signed displacement in disassembler. R=titzer@chromium.org BUG= Review URL: https://codereview.chromium.org/178193028 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@19667 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-05 09:28:26 +00:00
__ orps(xmm0, Operand(rbx, rcx, times_4, 10000));
Introduce orps for IA32/X64 BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/53573004 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17479 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-11-05 12:04:46 +00:00
__ xorps(xmm0, xmm1);
Print properly signed displacement in disassembler. R=titzer@chromium.org BUG= Review URL: https://codereview.chromium.org/178193028 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@19667 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-05 09:28:26 +00:00
__ xorps(xmm0, Operand(rbx, rcx, times_4, 10000));
Introduce addps/subps/mulps/divps for IA32/X64 BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/60093005 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17842 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-11-18 15:24:41 +00:00
// Arithmetic operation
[x64] Introduce FMA3 instructions on scalar data elements. R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/757503002 Patch from Weiliang Lin <weiliang.lin@intel.com>. Cr-Commit-Position: refs/heads/master@{#25509}
2014-11-26 05:31:41 +00:00
__ addss(xmm1, xmm0);
__ addss(xmm1, Operand(rbx, rcx, times_4, 10000));
__ mulss(xmm1, xmm0);
__ mulss(xmm1, Operand(rbx, rcx, times_4, 10000));
__ subss(xmm1, xmm0);
__ subss(xmm1, Operand(rbx, rcx, times_4, 10000));
__ divss(xmm1, xmm0);
__ divss(xmm1, Operand(rbx, rcx, times_4, 10000));
[turbofan] Add backend support for float32 operations. This adds the basics necessary to support float32 operations in TurboFan. The actual functionality required to detect safe float32 operations will be added based on this later. Therefore this does not affect production code except for some cleanup/refactoring. In detail, this patchset contains the following features: - Add support for float32 operations to arm, arm64, ia32 and x64 backends. - Add float32 machine operators. - Add support for float32 constants to simplified lowering. - Handle float32 representation for phis in simplified lowering. In addition, contains the following (related) cleanups: - Fix/unify naming of backend instructions. - Use AVX comparisons when available. - Extend ArchOpcodeField to 9 bits (required for arm64). - Refactor some code duplication in instruction selectors. BUG=v8:3589 LOG=n R=dcarney@chromium.org Review URL: https://codereview.chromium.org/1044793002 Cr-Commit-Position: refs/heads/master@{#27509}
2015-03-30 07:33:46 +00:00
__ maxss(xmm1, xmm0);
__ maxss(xmm1, Operand(rbx, rcx, times_4, 10000));
__ minss(xmm1, xmm0);
__ minss(xmm1, Operand(rbx, rcx, times_4, 10000));
[Liftoff] Implement f32.sqrt and f64.sqrt On ia32, support for vsqrtss and vsqrtsd was missing, so I add the implementation of these instructions and disassembly support. On x64, disassembly support for vsqrtss was missing, while vsqrtsd was implemented. Now both are implemented. The implementation of f32.sqrt and f64.sqrt is very straight-forward on ia32 and x64, we can immediately emit the {v}sqrtss or {v}sqrtsd instruction. R=ahaas@chromium.org Bug: v8:6600 Change-Id: Icf3ec05a97a23e94cdf70f4a72f30dd02fbddd13 Reviewed-on: https://chromium-review.googlesource.com/944221 Reviewed-by: Andreas Haas <ahaas@chromium.org> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Cr-Commit-Position: refs/heads/master@{#51724}
2018-03-03 08:53:21 +00:00
__ sqrtss(xmm1, xmm0);
__ sqrtss(xmm1, Operand(rbx, rcx, times_4, 10000));
Introduce addps/subps/mulps/divps for IA32/X64 BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/60093005 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17842 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-11-18 15:24:41 +00:00
__ addps(xmm1, xmm0);
__ addps(xmm1, Operand(rbx, rcx, times_4, 10000));
__ subps(xmm1, xmm0);
__ subps(xmm1, Operand(rbx, rcx, times_4, 10000));
__ mulps(xmm1, xmm0);
Print properly signed displacement in disassembler. R=titzer@chromium.org BUG= Review URL: https://codereview.chromium.org/178193028 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@19667 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-03-05 09:28:26 +00:00
__ mulps(xmm1, Operand(rbx, rcx, times_4, 10000));
Introduce addps/subps/mulps/divps for IA32/X64 BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/60093005 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17842 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-11-18 15:24:41 +00:00
__ divps(xmm1, xmm0);
__ divps(xmm1, Operand(rbx, rcx, times_4, 10000));
[x64] Introduce FMA3 instructions on scalar data elements. R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/757503002 Patch from Weiliang Lin <weiliang.lin@intel.com>. Cr-Commit-Position: refs/heads/master@{#25509}
2014-11-26 05:31:41 +00:00
__ ucomiss(xmm0, xmm1);
__ ucomiss(xmm0, Operand(rbx, rcx, times_4, 10000));
Introduce andps for IA32/X64 replace andpd and pand in Math.abs BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/44153002 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17413 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-10-28 10:38:40 +00:00
}
[x64] supplement SSE insturctions for SIMD.js Both legacy and AVX versions BUG= Review-Url: https://codereview.chromium.org/2328843003 Cr-Commit-Position: refs/heads/master@{#39327}
2016-09-12 06:24:06 +00:00
// SSE2 instructions
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
{
Introduce andps for IA32/X64 replace andpd and pand in Math.abs BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/44153002 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17413 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-10-28 10:38:40 +00:00
__ cvttsd2si(rdx, Operand(rbx, rcx, times_4, 10000));
__ cvttsd2si(rdx, xmm1);
__ cvttsd2siq(rdx, xmm1);
[turbofan] IA: Float64ToUint32 supports mem operand BUG= R=titzer@chromium.org Review URL: https://codereview.chromium.org/582713002 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24092 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-09-19 14:25:13 +00:00
__ cvttsd2siq(rdx, Operand(rbx, rcx, times_4, 10000));
[turbofan] IA: Uint32ToFloat64 supports mem operand. BUG= R=dcarney@chromium.org Review URL: https://codereview.chromium.org/583963002 Patch from Jing Bao <jing.bao@intel.com>. git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24318 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-09-30 10:24:11 +00:00
__ cvtqsi2sd(xmm1, Operand(rbx, rcx, times_4, 10000));
__ cvtqsi2sd(xmm1, rdx);
Introduce andps for IA32/X64 replace andpd and pand in Math.abs BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/44153002 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17413 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-10-28 10:38:40 +00:00
__ movsd(xmm1, Operand(rbx, rcx, times_4, 10000));
__ movsd(Operand(rbx, rcx, times_4, 10000), xmm1);
// 128 bit move instructions.
[x64] add Absps/d and Negps/d macro BUG= Review-Url: https://codereview.chromium.org/2161513002 Cr-Commit-Position: refs/heads/master@{#37937}
2016-07-21 11:01:44 +00:00
__ movupd(xmm0, Operand(rbx, rcx, times_4, 10000));
__ movupd(Operand(rbx, rcx, times_4, 10000), xmm0);
Introduce andps for IA32/X64 replace andpd and pand in Math.abs BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/44153002 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17413 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-10-28 10:38:40 +00:00
__ movdqa(xmm0, Operand(rbx, rcx, times_4, 10000));
__ movdqa(Operand(rbx, rcx, times_4, 10000), xmm0);
__ addsd(xmm1, xmm0);
IA: Double arithmetic binops support memory operand BUG= R=dcarney@chromium.org Review URL: https://codereview.chromium.org/662813002 Patch from Weiliang Lin <weiliang.lin@intel.com>. Cr-Commit-Position: refs/heads/master@{#25052} git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25052 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-11-03 05:56:55 +00:00
__ addsd(xmm1, Operand(rbx, rcx, times_4, 10000));
Introduce andps for IA32/X64 replace andpd and pand in Math.abs BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/44153002 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17413 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-10-28 10:38:40 +00:00
__ mulsd(xmm1, xmm0);
IA: Double arithmetic binops support memory operand BUG= R=dcarney@chromium.org Review URL: https://codereview.chromium.org/662813002 Patch from Weiliang Lin <weiliang.lin@intel.com>. Cr-Commit-Position: refs/heads/master@{#25052} git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25052 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-11-03 05:56:55 +00:00
__ mulsd(xmm1, Operand(rbx, rcx, times_4, 10000));
Introduce andps for IA32/X64 replace andpd and pand in Math.abs BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/44153002 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17413 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-10-28 10:38:40 +00:00
__ subsd(xmm1, xmm0);
IA: Double arithmetic binops support memory operand BUG= R=dcarney@chromium.org Review URL: https://codereview.chromium.org/662813002 Patch from Weiliang Lin <weiliang.lin@intel.com>. Cr-Commit-Position: refs/heads/master@{#25052} git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25052 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-11-03 05:56:55 +00:00
__ subsd(xmm1, Operand(rbx, rcx, times_4, 10000));
Introduce andps for IA32/X64 replace andpd and pand in Math.abs BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/44153002 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17413 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-10-28 10:38:40 +00:00
__ divsd(xmm1, xmm0);
IA: Double arithmetic binops support memory operand BUG= R=dcarney@chromium.org Review URL: https://codereview.chromium.org/662813002 Patch from Weiliang Lin <weiliang.lin@intel.com>. Cr-Commit-Position: refs/heads/master@{#25052} git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@25052 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-11-03 05:56:55 +00:00
__ divsd(xmm1, Operand(rbx, rcx, times_4, 10000));
[turbofan] Introduce optional Float64Min and Float64Max machine operators. Basically recognize certain x < y ? x : y constructs and turn that into Float64Min/Float64Max operations, if the target machine supports that. On x86 we lower to (v)minsd/(v)maxsd. R=dcarney@chromium.org Review URL: https://codereview.chromium.org/998283002 Cr-Commit-Position: refs/heads/master@{#27160}
2015-03-12 14:07:28 +00:00
__ minsd(xmm1, xmm0);
__ minsd(xmm1, Operand(rbx, rcx, times_4, 10000));
__ maxsd(xmm1, xmm0);
__ maxsd(xmm1, Operand(rbx, rcx, times_4, 10000));
[Liftoff] Implement f32.sqrt and f64.sqrt On ia32, support for vsqrtss and vsqrtsd was missing, so I add the implementation of these instructions and disassembly support. On x64, disassembly support for vsqrtss was missing, while vsqrtsd was implemented. Now both are implemented. The implementation of f32.sqrt and f64.sqrt is very straight-forward on ia32 and x64, we can immediately emit the {v}sqrtss or {v}sqrtsd instruction. R=ahaas@chromium.org Bug: v8:6600 Change-Id: Icf3ec05a97a23e94cdf70f4a72f30dd02fbddd13 Reviewed-on: https://chromium-review.googlesource.com/944221 Reviewed-by: Andreas Haas <ahaas@chromium.org> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Cr-Commit-Position: refs/heads/master@{#51724}
2018-03-03 08:53:21 +00:00
__ sqrtsd(xmm1, xmm0);
__ sqrtsd(xmm1, Operand(rbx, rcx, times_4, 10000));
Introduce andps for IA32/X64 replace andpd and pand in Math.abs BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/44153002 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17413 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-10-28 10:38:40 +00:00
__ ucomisd(xmm0, xmm1);
__ andpd(xmm0, xmm1);
[x64] add Absps/d and Negps/d macro BUG= Review-Url: https://codereview.chromium.org/2161513002 Cr-Commit-Position: refs/heads/master@{#37937}
2016-07-21 11:01:44 +00:00
__ andpd(xmm0, Operand(rbx, rcx, times_4, 10000));
__ orpd(xmm0, xmm1);
__ orpd(xmm0, Operand(rbx, rcx, times_4, 10000));
__ xorpd(xmm0, xmm1);
__ xorpd(xmm0, Operand(rbx, rcx, times_4, 10000));
[x64] simply tweak materialization of float/double constants port 24485 Fixed a bug of "psllq" instruction in x64 R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/658813003 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@24673 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-10-17 04:18:38 +00:00
__ pslld(xmm0, 6);
__ psrld(xmm0, 6);
__ psllq(xmm0, 6);
__ psrlq(xmm0, 6);
__ pcmpeqd(xmm1, xmm0);
[turbofan] Support for %_DoubleHi, %_DoubleLo and %_ConstructDouble. This adds support for the double bits intrinsics to TurboFan, and is a first step towards fast Math functions inlined into TurboFan code or even compiled by themselves with TurboFan. Review URL: https://codereview.chromium.org/974313002 Cr-Commit-Position: refs/heads/master@{#27006}
2015-03-05 09:22:26 +00:00
__ punpckldq(xmm1, xmm11);
[x64] Small fixes in the assembler and disassembler. Disassembler: added decoding of a few instructions that were previously unsupported, fixed the decoding of pextr. Assembler: pmulld(XMMRegister, Operand) was actually emitting a pmuludq. punpckldq(XMMRegister, XMMRegister) was implemented a second time as punpackldq. BUG= Review-Url: https://codereview.chromium.org/2070863002 Cr-Commit-Position: refs/heads/master@{#37059}
2016-06-17 09:26:58 +00:00
__ punpckldq(xmm5, Operand(rdx, 4));
[turbofan] Support for %_DoubleHi, %_DoubleLo and %_ConstructDouble. This adds support for the double bits intrinsics to TurboFan, and is a first step towards fast Math functions inlined into TurboFan code or even compiled by themselves with TurboFan. Review URL: https://codereview.chromium.org/974313002 Cr-Commit-Position: refs/heads/master@{#27006}
2015-03-05 09:22:26 +00:00
__ punpckhdq(xmm8, xmm15);
[x64] supplement SSE insturctions for SIMD.js Both legacy and AVX versions BUG= Review-Url: https://codereview.chromium.org/2328843003 Cr-Commit-Position: refs/heads/master@{#39327}
2016-09-12 06:24:06 +00:00
[wasm] Implement wasm x64 I16x8 Ops - Add I16x8 Splat, ExtractLane, ReplaceLane, shift ops, Some BinOps and compare ops - Add pshufhw, pshuflw in the assembler, disassembler - Fix incorrect modrm for pextrw, this bug disregards the register allocated and always makes pextrw use rax. - Fix pextrw disasm to take the 0 - 7 bits of the immediate instead of 0 - 3. - Pextrw, pinsrw are in the assembler use 128 bit encodings, pextrw, pinsrw in the disassembler use legacy encodings, fix inconsistencies causing weird code gen when --print-code is used. Review-Url: https://codereview.chromium.org/2767983002 Cr-Commit-Position: refs/heads/master@{#44664}
2017-04-17 18:47:46 +00:00
__ pshuflw(xmm2, xmm4, 3);
__ pshufhw(xmm1, xmm9, 6);
[x64] supplement SSE insturctions for SIMD.js Both legacy and AVX versions BUG= Review-Url: https://codereview.chromium.org/2328843003 Cr-Commit-Position: refs/heads/master@{#39327}
2016-09-12 06:24:06 +00:00
#define EMIT_SSE2_INSTR(instruction, notUsed1, notUsed2, notUsed3) \
__ instruction(xmm5, xmm1); \
__ instruction(xmm5, Operand(rdx, 4));
SSE2_INSTRUCTION_LIST(EMIT_SSE2_INSTR)
#undef EMIT_SSE2_INSTR
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
}
Introduce andps for IA32/X64 replace andpd and pand in Math.abs BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/44153002 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17413 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-10-28 10:38:40 +00:00
// cmov.
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
{
Introduce andps for IA32/X64 replace andpd and pand in Math.abs BUG= R=svenpanne@chromium.org Review URL: https://codereview.chromium.org/44153002 Patch from Weiliang Lin <weiliang.lin@intel.com>. git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17413 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-10-28 10:38:40 +00:00
__ cmovq(overflow, rax, Operand(rax, 0));
__ cmovq(no_overflow, rax, Operand(rax, 1));
__ cmovq(below, rax, Operand(rax, 2));
__ cmovq(above_equal, rax, Operand(rax, 3));
__ cmovq(equal, rax, Operand(rbx, 0));
__ cmovq(not_equal, rax, Operand(rbx, 1));
__ cmovq(below_equal, rax, Operand(rbx, 2));
__ cmovq(above, rax, Operand(rbx, 3));
__ cmovq(sign, rax, Operand(rcx, 0));
__ cmovq(not_sign, rax, Operand(rcx, 1));
__ cmovq(parity_even, rax, Operand(rcx, 2));
__ cmovq(parity_odd, rax, Operand(rcx, 3));
__ cmovq(less, rax, Operand(rdx, 0));
__ cmovq(greater_equal, rax, Operand(rdx, 1));
__ cmovq(less_equal, rax, Operand(rdx, 2));
__ cmovq(greater, rax, Operand(rdx, 3));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
}
[x64] supplement SSE insturctions for SIMD.js Both legacy and AVX versions BUG= Review-Url: https://codereview.chromium.org/2328843003 Cr-Commit-Position: refs/heads/master@{#39327}
2016-09-12 06:24:06 +00:00
{
if (CpuFeatures::IsSupported(SSE3)) {
CpuFeatureScope scope(&assm, SSE3);
Add phaddd/vphaddd, phaddw/vphaddw and vhaddps to ia32 Also Add vhaddps to x64 Fix haddps for SSE3 scope and disassembler on ia32/x64 Change-Id: If511e6428fa1ce034b4281943dfee1405c9d4ffc Reviewed-on: https://chromium-review.googlesource.com/939265 Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Jing Bao <jing.bao@intel.com> Cr-Commit-Position: refs/heads/master@{#51642}
2018-02-28 06:28:08 +00:00
__ haddps(xmm1, xmm0);
__ haddps(xmm1, Operand(rbx, rcx, times_4, 10000));
[x64] supplement SSE insturctions for SIMD.js Both legacy and AVX versions BUG= Review-Url: https://codereview.chromium.org/2328843003 Cr-Commit-Position: refs/heads/master@{#39327}
2016-09-12 06:24:06 +00:00
__ lddqu(xmm1, Operand(rdx, 4));
}
}
#define EMIT_SSE34_INSTR(instruction, notUsed1, notUsed2, notUsed3, notUsed4) \
__ instruction(xmm5, xmm1); \
__ instruction(xmm5, Operand(rdx, 4));
{
if (CpuFeatures::IsSupported(SSSE3)) {
CpuFeatureScope scope(&assm, SSSE3);
[x64] Add assembly/disassembly for left-over SIMD ops Change-Id: I55d15fd15cc714732139e4bf12bd75f21f922048 Reviewed-on: https://chromium-review.googlesource.com/1174013 Reviewed-by: Ben Titzer <titzer@chromium.org> Reviewed-by: Bill Budge <bbudge@chromium.org> Commit-Queue: Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/master@{#55174}
2018-08-14 19:38:14 +00:00
__ palignr(xmm5, xmm1, 5);
__ palignr(xmm5, Operand(rdx, 4), 5);
[x64] supplement SSE insturctions for SIMD.js Both legacy and AVX versions BUG= Review-Url: https://codereview.chromium.org/2328843003 Cr-Commit-Position: refs/heads/master@{#39327}
2016-09-12 06:24:06 +00:00
SSSE3_INSTRUCTION_LIST(EMIT_SSE34_INSTR)
}
}
Fixed bug in extractps instruction on ia32 and x64 This is a fixed version of https://codereview.chromium.org/27097002/ which was originally written by weiliang.lin@intel.com. R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/27301003 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17217 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-10-15 12:51:58 +00:00
{
if (CpuFeatures::IsSupported(SSE4_1)) {
CpuFeatureScope scope(&assm, SSE4_1);
Adding x64 simd assembler support. Based on assembler changes from this patch: https://codereview.chromium.org/90643003/ BUG=https://bugs.chromium.org/p/v8/issues/detail?id=4124 R=titzer@chromium.org,bbudge@chromium.org LOG=N Review-Url: https://codereview.chromium.org/1994083003 Cr-Commit-Position: refs/heads/master@{#36383}
2016-05-19 19:52:59 +00:00
__ insertps(xmm5, xmm1, 123);
Fixed bug in extractps instruction on ia32 and x64 This is a fixed version of https://codereview.chromium.org/27097002/ which was originally written by weiliang.lin@intel.com. R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/27301003 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17217 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-10-15 12:51:58 +00:00
__ extractps(rax, xmm1, 0);
Add pshufw instruction, fix inconsistencies with pextrw instruction. Current implementation of the pextrw instruction is the legacy SSE2 instruction in the assembler (66 0F C5), and SSE4 implementation(66 0F 3A 15) in disasm-x64.cc, this causes incorrect instruction encodings to be printed when using --print-code flag for debug, in this case, causes over flow of bytes, and subsequent instructions to be incorrectly disassembled. Fixing to use SSE4 encodings in the assembler cosistent with pextrb, pextrd. R=bbudge@chromium.org, mtrofin@chromium.org Review-Url: https://codereview.chromium.org/2771513002 Cr-Commit-Position: refs/heads/master@{#44047}
2017-03-22 20:49:27 +00:00
__ pextrw(rbx, xmm2, 1);
[wasm] Implement wasm x64 I16x8 Ops - Add I16x8 Splat, ExtractLane, ReplaceLane, shift ops, Some BinOps and compare ops - Add pshufhw, pshuflw in the assembler, disassembler - Fix incorrect modrm for pextrw, this bug disregards the register allocated and always makes pextrw use rax. - Fix pextrw disasm to take the 0 - 7 bits of the immediate instead of 0 - 3. - Pextrw, pinsrw are in the assembler use 128 bit encodings, pextrw, pinsrw in the disassembler use legacy encodings, fix inconsistencies causing weird code gen when --print-code is used. Review-Url: https://codereview.chromium.org/2767983002 Cr-Commit-Position: refs/heads/master@{#44664}
2017-04-17 18:47:46 +00:00
__ pinsrw(xmm2, rcx, 1);
[turbofan] Support for %_DoubleHi, %_DoubleLo and %_ConstructDouble. This adds support for the double bits intrinsics to TurboFan, and is a first step towards fast Math functions inlined into TurboFan code or even compiled by themselves with TurboFan. Review URL: https://codereview.chromium.org/974313002 Cr-Commit-Position: refs/heads/master@{#27006}
2015-03-05 09:22:26 +00:00
__ pextrd(rbx, xmm15, 0);
__ pextrd(r12, xmm0, 1);
__ pinsrd(xmm9, r9, 0);
Adding x64 simd assembler support. Based on assembler changes from this patch: https://codereview.chromium.org/90643003/ BUG=https://bugs.chromium.org/p/v8/issues/detail?id=4124 R=titzer@chromium.org,bbudge@chromium.org LOG=N Review-Url: https://codereview.chromium.org/1994083003 Cr-Commit-Position: refs/heads/master@{#36383}
2016-05-19 19:52:59 +00:00
__ pinsrd(xmm5, Operand(rax, 4), 1);
[x64] Add assembly/disassembly for left-over SIMD ops Change-Id: I55d15fd15cc714732139e4bf12bd75f21f922048 Reviewed-on: https://chromium-review.googlesource.com/1174013 Reviewed-by: Ben Titzer <titzer@chromium.org> Reviewed-by: Bill Budge <bbudge@chromium.org> Commit-Queue: Deepti Gandluri <gdeepti@chromium.org> Cr-Commit-Position: refs/heads/master@{#55174}
2018-08-14 19:38:14 +00:00
__ pblendw(xmm5, xmm1, 1);
__ pblendw(xmm9, Operand(rax, 4), 1);
Adding x64 simd assembler support. Based on assembler changes from this patch: https://codereview.chromium.org/90643003/ BUG=https://bugs.chromium.org/p/v8/issues/detail?id=4124 R=titzer@chromium.org,bbudge@chromium.org LOG=N Review-Url: https://codereview.chromium.org/1994083003 Cr-Commit-Position: refs/heads/master@{#36383}
2016-05-19 19:52:59 +00:00
__ cmpps(xmm5, xmm1, 1);
[x64]: add cmpps/cmppd instructions BUG= Review-Url: https://codereview.chromium.org/2170323002 Cr-Commit-Position: refs/heads/master@{#38307}
2016-08-03 15:23:57 +00:00
__ cmpps(xmm5, Operand(rbx, rcx, times_4, 10000), 1);
Adding x64 simd assembler support. Based on assembler changes from this patch: https://codereview.chromium.org/90643003/ BUG=https://bugs.chromium.org/p/v8/issues/detail?id=4124 R=titzer@chromium.org,bbudge@chromium.org LOG=N Review-Url: https://codereview.chromium.org/1994083003 Cr-Commit-Position: refs/heads/master@{#36383}
2016-05-19 19:52:59 +00:00
__ cmpeqps(xmm5, xmm1);
[x64]: add cmpps/cmppd instructions BUG= Review-Url: https://codereview.chromium.org/2170323002 Cr-Commit-Position: refs/heads/master@{#38307}
2016-08-03 15:23:57 +00:00
__ cmpeqps(xmm5, Operand(rbx, rcx, times_4, 10000));
Adding x64 simd assembler support. Based on assembler changes from this patch: https://codereview.chromium.org/90643003/ BUG=https://bugs.chromium.org/p/v8/issues/detail?id=4124 R=titzer@chromium.org,bbudge@chromium.org LOG=N Review-Url: https://codereview.chromium.org/1994083003 Cr-Commit-Position: refs/heads/master@{#36383}
2016-05-19 19:52:59 +00:00
__ cmpltps(xmm5, xmm1);
[x64]: add cmpps/cmppd instructions BUG= Review-Url: https://codereview.chromium.org/2170323002 Cr-Commit-Position: refs/heads/master@{#38307}
2016-08-03 15:23:57 +00:00
__ cmpltps(xmm5, Operand(rbx, rcx, times_4, 10000));
Adding x64 simd assembler support. Based on assembler changes from this patch: https://codereview.chromium.org/90643003/ BUG=https://bugs.chromium.org/p/v8/issues/detail?id=4124 R=titzer@chromium.org,bbudge@chromium.org LOG=N Review-Url: https://codereview.chromium.org/1994083003 Cr-Commit-Position: refs/heads/master@{#36383}
2016-05-19 19:52:59 +00:00
__ cmpleps(xmm5, xmm1);
[x64]: add cmpps/cmppd instructions BUG= Review-Url: https://codereview.chromium.org/2170323002 Cr-Commit-Position: refs/heads/master@{#38307}
2016-08-03 15:23:57 +00:00
__ cmpleps(xmm5, Operand(rbx, rcx, times_4, 10000));
Adding x64 simd assembler support. Based on assembler changes from this patch: https://codereview.chromium.org/90643003/ BUG=https://bugs.chromium.org/p/v8/issues/detail?id=4124 R=titzer@chromium.org,bbudge@chromium.org LOG=N Review-Url: https://codereview.chromium.org/1994083003 Cr-Commit-Position: refs/heads/master@{#36383}
2016-05-19 19:52:59 +00:00
__ cmpneqps(xmm5, xmm1);
[x64]: add cmpps/cmppd instructions BUG= Review-Url: https://codereview.chromium.org/2170323002 Cr-Commit-Position: refs/heads/master@{#38307}
2016-08-03 15:23:57 +00:00
__ cmpneqps(xmm5, Operand(rbx, rcx, times_4, 10000));
Adding x64 simd assembler support. Based on assembler changes from this patch: https://codereview.chromium.org/90643003/ BUG=https://bugs.chromium.org/p/v8/issues/detail?id=4124 R=titzer@chromium.org,bbudge@chromium.org LOG=N Review-Url: https://codereview.chromium.org/1994083003 Cr-Commit-Position: refs/heads/master@{#36383}
2016-05-19 19:52:59 +00:00
__ cmpnltps(xmm5, xmm1);
[x64]: add cmpps/cmppd instructions BUG= Review-Url: https://codereview.chromium.org/2170323002 Cr-Commit-Position: refs/heads/master@{#38307}
2016-08-03 15:23:57 +00:00
__ cmpnltps(xmm5, Operand(rbx, rcx, times_4, 10000));
Adding x64 simd assembler support. Based on assembler changes from this patch: https://codereview.chromium.org/90643003/ BUG=https://bugs.chromium.org/p/v8/issues/detail?id=4124 R=titzer@chromium.org,bbudge@chromium.org LOG=N Review-Url: https://codereview.chromium.org/1994083003 Cr-Commit-Position: refs/heads/master@{#36383}
2016-05-19 19:52:59 +00:00
__ cmpnleps(xmm5, xmm1);
[x64]: add cmpps/cmppd instructions BUG= Review-Url: https://codereview.chromium.org/2170323002 Cr-Commit-Position: refs/heads/master@{#38307}
2016-08-03 15:23:57 +00:00
__ cmpnleps(xmm5, Operand(rbx, rcx, times_4, 10000));
__ cmppd(xmm5, xmm1, 1);
__ cmppd(xmm5, Operand(rbx, rcx, times_4, 10000), 1);
__ cmpeqpd(xmm5, xmm1);
__ cmpeqpd(xmm5, Operand(rbx, rcx, times_4, 10000));
__ cmpltpd(xmm5, xmm1);
__ cmpltpd(xmm5, Operand(rbx, rcx, times_4, 10000));
__ cmplepd(xmm5, xmm1);
__ cmplepd(xmm5, Operand(rbx, rcx, times_4, 10000));
__ cmpneqpd(xmm5, xmm1);
__ cmpneqpd(xmm5, Operand(rbx, rcx, times_4, 10000));
__ cmpnltpd(xmm5, xmm1);
__ cmpnltpd(xmm5, Operand(rbx, rcx, times_4, 10000));
__ cmpnlepd(xmm5, xmm1);
__ cmpnlepd(xmm5, Operand(rbx, rcx, times_4, 10000));
Adding x64 simd assembler support. Based on assembler changes from this patch: https://codereview.chromium.org/90643003/ BUG=https://bugs.chromium.org/p/v8/issues/detail?id=4124 R=titzer@chromium.org,bbudge@chromium.org LOG=N Review-Url: https://codereview.chromium.org/1994083003 Cr-Commit-Position: refs/heads/master@{#36383}
2016-05-19 19:52:59 +00:00
__ minps(xmm5, xmm1);
__ minps(xmm5, Operand(rdx, 4));
__ maxps(xmm5, xmm1);
__ maxps(xmm5, Operand(rdx, 4));
__ rcpps(xmm5, xmm1);
__ rcpps(xmm5, Operand(rdx, 4));
__ sqrtps(xmm5, xmm1);
__ sqrtps(xmm5, Operand(rdx, 4));
__ movups(xmm5, xmm1);
__ movups(xmm5, Operand(rdx, 4));
__ movups(Operand(rdx, 4), xmm5);
__ pmulld(xmm5, xmm1);
__ pmulld(xmm5, Operand(rdx, 4));
[x64] supplement SSE insturctions for SIMD.js Both legacy and AVX versions BUG= Review-Url: https://codereview.chromium.org/2328843003 Cr-Commit-Position: refs/heads/master@{#39327}
2016-09-12 06:24:06 +00:00
__ pmullw(xmm5, xmm1);
__ pmullw(xmm5, Operand(rdx, 4));
Adding x64 simd assembler support. Based on assembler changes from this patch: https://codereview.chromium.org/90643003/ BUG=https://bugs.chromium.org/p/v8/issues/detail?id=4124 R=titzer@chromium.org,bbudge@chromium.org LOG=N Review-Url: https://codereview.chromium.org/1994083003 Cr-Commit-Position: refs/heads/master@{#36383}
2016-05-19 19:52:59 +00:00
__ pmuludq(xmm5, xmm1);
__ pmuludq(xmm5, Operand(rdx, 4));
__ psrldq(xmm5, 123);
__ pshufd(xmm5, xmm1, 3);
__ cvtps2dq(xmm5, xmm1);
__ cvtps2dq(xmm5, Operand(rdx, 4));
__ cvtdq2ps(xmm5, xmm1);
__ cvtdq2ps(xmm5, Operand(rdx, 4));
[x64] supplement SSE insturctions for SIMD.js Both legacy and AVX versions BUG= Review-Url: https://codereview.chromium.org/2328843003 Cr-Commit-Position: refs/heads/master@{#39327}
2016-09-12 06:24:06 +00:00
SSE4_INSTRUCTION_LIST(EMIT_SSE34_INSTR)
Fixed bug in extractps instruction on ia32 and x64 This is a fixed version of https://codereview.chromium.org/27097002/ which was originally written by weiliang.lin@intel.com. R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/27301003 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17217 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-10-15 12:51:58 +00:00
}
}
[x64] supplement SSE insturctions for SIMD.js Both legacy and AVX versions BUG= Review-Url: https://codereview.chromium.org/2328843003 Cr-Commit-Position: refs/heads/master@{#39327}
2016-09-12 06:24:06 +00:00
#undef EMIT_SSE34_INSTR
Fixed bug in extractps instruction on ia32 and x64 This is a fixed version of https://codereview.chromium.org/27097002/ which was originally written by weiliang.lin@intel.com. R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/27301003 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@17217 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2013-10-15 12:51:58 +00:00
[x64] introduce vex prefix version of float64 arithmetic binop BUG= R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/764863002 Patch from Weiliang Lin <weiliang.lin@intel.com>. Cr-Commit-Position: refs/heads/master@{#25582}
2014-12-01 10:45:02 +00:00
// AVX instruction
{
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(&assm, AVX);
[x64] Replace movaps with appropriate vmov* instructions when AVX is enabled. BUG=v8:4406 LOG=N Review URL: https://codereview.chromium.org/1416663004 Cr-Commit-Position: refs/heads/master@{#31391}
2015-10-20 04:58:07 +00:00
__ vmovss(xmm6, xmm14, xmm2);
__ vmovss(xmm9, Operand(rbx, rcx, times_4, 10000));
__ vmovss(Operand(rbx, rcx, times_4, 10000), xmm0);
[turbofan] Add backend support for float32 operations. This adds the basics necessary to support float32 operations in TurboFan. The actual functionality required to detect safe float32 operations will be added based on this later. Therefore this does not affect production code except for some cleanup/refactoring. In detail, this patchset contains the following features: - Add support for float32 operations to arm, arm64, ia32 and x64 backends. - Add float32 machine operators. - Add support for float32 constants to simplified lowering. - Handle float32 representation for phis in simplified lowering. In addition, contains the following (related) cleanups: - Fix/unify naming of backend instructions. - Use AVX comparisons when available. - Extend ArchOpcodeField to 9 bits (required for arm64). - Refactor some code duplication in instruction selectors. BUG=v8:3589 LOG=n R=dcarney@chromium.org Review URL: https://codereview.chromium.org/1044793002 Cr-Commit-Position: refs/heads/master@{#27509}
2015-03-30 07:33:46 +00:00
__ vaddss(xmm0, xmm1, xmm2);
__ vaddss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vmulss(xmm0, xmm1, xmm2);
__ vmulss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vsubss(xmm0, xmm1, xmm2);
__ vsubss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vdivss(xmm0, xmm1, xmm2);
__ vdivss(xmm0, xmm1, Operand(rbx, rcx, times_2, 10000));
__ vminss(xmm8, xmm1, xmm2);
__ vminss(xmm9, xmm1, Operand(rbx, rcx, times_8, 10000));
__ vmaxss(xmm8, xmm1, xmm2);
__ vmaxss(xmm9, xmm1, Operand(rbx, rcx, times_1, 10000));
[Liftoff] Implement f32.sqrt and f64.sqrt On ia32, support for vsqrtss and vsqrtsd was missing, so I add the implementation of these instructions and disassembly support. On x64, disassembly support for vsqrtss was missing, while vsqrtsd was implemented. Now both are implemented. The implementation of f32.sqrt and f64.sqrt is very straight-forward on ia32 and x64, we can immediately emit the {v}sqrtss or {v}sqrtsd instruction. R=ahaas@chromium.org Bug: v8:6600 Change-Id: Icf3ec05a97a23e94cdf70f4a72f30dd02fbddd13 Reviewed-on: https://chromium-review.googlesource.com/944221 Reviewed-by: Andreas Haas <ahaas@chromium.org> Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Cr-Commit-Position: refs/heads/master@{#51724}
2018-03-03 08:53:21 +00:00
__ vsqrtss(xmm8, xmm1, xmm2);
__ vsqrtss(xmm9, xmm1, Operand(rbx, rcx, times_1, 10000));
[x64] Emit vmovss when AVX is enabled. BUG=v8:4406 LOG=N Review URL: https://codereview.chromium.org/1413183002 Cr-Commit-Position: refs/heads/master@{#31385}
2015-10-19 20:35:17 +00:00
__ vmovss(xmm9, Operand(r11, rcx, times_8, -10000));
__ vmovss(Operand(rbx, r9, times_4, 10000), xmm1);
[turbofan] Add backend support for float32 operations. This adds the basics necessary to support float32 operations in TurboFan. The actual functionality required to detect safe float32 operations will be added based on this later. Therefore this does not affect production code except for some cleanup/refactoring. In detail, this patchset contains the following features: - Add support for float32 operations to arm, arm64, ia32 and x64 backends. - Add float32 machine operators. - Add support for float32 constants to simplified lowering. - Handle float32 representation for phis in simplified lowering. In addition, contains the following (related) cleanups: - Fix/unify naming of backend instructions. - Use AVX comparisons when available. - Extend ArchOpcodeField to 9 bits (required for arm64). - Refactor some code duplication in instruction selectors. BUG=v8:3589 LOG=n R=dcarney@chromium.org Review URL: https://codereview.chromium.org/1044793002 Cr-Commit-Position: refs/heads/master@{#27509}
2015-03-30 07:33:46 +00:00
__ vucomiss(xmm9, xmm1);
__ vucomiss(xmm8, Operand(rbx, rdx, times_2, 10981));
[x64] Implement vmovd and vmovq AVX instructions. BUG=v8:4406 LOG=N Review URL: https://codereview.chromium.org/1409873002 Cr-Commit-Position: refs/heads/master@{#31322}
2015-10-16 05:20:31 +00:00
__ vmovd(xmm5, rdi);
__ vmovd(xmm9, Operand(rbx, rcx, times_4, 10000));
__ vmovd(r9, xmm6);
__ vmovq(xmm5, rdi);
__ vmovq(xmm9, Operand(rbx, rcx, times_4, 10000));
__ vmovq(r9, xmm6);
[x64] Replace movaps with appropriate vmov* instructions when AVX is enabled. BUG=v8:4406 LOG=N Review URL: https://codereview.chromium.org/1416663004 Cr-Commit-Position: refs/heads/master@{#31391}
2015-10-20 04:58:07 +00:00
__ vmovsd(xmm6, xmm14, xmm2);
[x64] Use vmovapd and vmovsd when AVX is enabled. R=bmeurer@chromium.org BUG=v8:4406 LOG=N Review URL: https://codereview.chromium.org/1391963005 Cr-Commit-Position: refs/heads/master@{#31275}
2015-10-15 04:14:31 +00:00
__ vmovsd(xmm9, Operand(rbx, rcx, times_4, 10000));
__ vmovsd(Operand(rbx, rcx, times_4, 10000), xmm0);
[x64] introduce vex prefix version of float64 arithmetic binop BUG= R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/764863002 Patch from Weiliang Lin <weiliang.lin@intel.com>. Cr-Commit-Position: refs/heads/master@{#25582}
2014-12-01 10:45:02 +00:00
__ vaddsd(xmm0, xmm1, xmm2);
__ vaddsd(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vmulsd(xmm0, xmm1, xmm2);
__ vmulsd(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vsubsd(xmm0, xmm1, xmm2);
__ vsubsd(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vdivsd(xmm0, xmm1, xmm2);
[turbofan] Introduce optional Float64Min and Float64Max machine operators. Basically recognize certain x < y ? x : y constructs and turn that into Float64Min/Float64Max operations, if the target machine supports that. On x86 we lower to (v)minsd/(v)maxsd. R=dcarney@chromium.org Review URL: https://codereview.chromium.org/998283002 Cr-Commit-Position: refs/heads/master@{#27160}
2015-03-12 14:07:28 +00:00
__ vdivsd(xmm0, xmm1, Operand(rbx, rcx, times_2, 10000));
__ vminsd(xmm8, xmm1, xmm2);
__ vminsd(xmm9, xmm1, Operand(rbx, rcx, times_8, 10000));
__ vmaxsd(xmm8, xmm1, xmm2);
__ vmaxsd(xmm9, xmm1, Operand(rbx, rcx, times_1, 10000));
[x64] Implemennt vroundsd AVX instruction. BUG=v8:4406 LOG=N Review URL: https://codereview.chromium.org/1420653005 Cr-Commit-Position: refs/heads/master@{#31493}
2015-10-23 07:48:54 +00:00
__ vroundsd(xmm8, xmm3, xmm0, kRoundDown);
[x64] Implement vsqrtsd AVX instruction. BUG=v8:4406 LOG=N Review URL: https://codereview.chromium.org/1420543003 Cr-Commit-Position: refs/heads/master@{#31490}
2015-10-23 06:47:13 +00:00
__ vsqrtsd(xmm8, xmm1, xmm2);
__ vsqrtsd(xmm9, xmm1, Operand(rbx, rcx, times_1, 10000));
[turbofan] Add backend support for float32 operations. This adds the basics necessary to support float32 operations in TurboFan. The actual functionality required to detect safe float32 operations will be added based on this later. Therefore this does not affect production code except for some cleanup/refactoring. In detail, this patchset contains the following features: - Add support for float32 operations to arm, arm64, ia32 and x64 backends. - Add float32 machine operators. - Add support for float32 constants to simplified lowering. - Handle float32 representation for phis in simplified lowering. In addition, contains the following (related) cleanups: - Fix/unify naming of backend instructions. - Use AVX comparisons when available. - Extend ArchOpcodeField to 9 bits (required for arm64). - Refactor some code duplication in instruction selectors. BUG=v8:3589 LOG=n R=dcarney@chromium.org Review URL: https://codereview.chromium.org/1044793002 Cr-Commit-Position: refs/heads/master@{#27509}
2015-03-30 07:33:46 +00:00
__ vucomisd(xmm9, xmm1);
__ vucomisd(xmm8, Operand(rbx, rdx, times_2, 10981));
[x64] Emit vcvttsd2si[q] when AVX is enabled. BUG=v8:4406 LOG=N Review URL: https://codereview.chromium.org/1406353003 Cr-Commit-Position: refs/heads/master@{#31348}
2015-10-18 15:43:07 +00:00
[x64] Emit vcvtss2sd & vcvtsd2ss when AVX is enabled. BUG=v8:4406 LOG=N Review URL: https://codereview.chromium.org/1411743003 Cr-Commit-Position: refs/heads/master@{#31349}
2015-10-18 16:11:11 +00:00
__ vcvtss2sd(xmm4, xmm9, xmm11);
__ vcvtsd2ss(xmm9, xmm3, xmm2);
__ vcvtss2sd(xmm4, xmm9, Operand(rbx, rcx, times_1, 10000));
__ vcvtsd2ss(xmm9, xmm3, Operand(rbx, rcx, times_1, 10000));
[x64] Use vcvtlsi2sd when AVX is enabled BUG=v8:4406 LOG=N Committed: https://crrev.com/adcbe619a959fe1d8f21d06fbf5984868c4f6b9a Cr-Commit-Position: refs/heads/master@{#31276} Review URL: https://codereview.chromium.org/1404903004 Cr-Commit-Position: refs/heads/master@{#31315}
2015-10-15 17:50:03 +00:00
__ vcvtlsi2sd(xmm5, xmm9, rcx);
__ vcvtlsi2sd(xmm9, xmm3, Operand(rbx, r9, times_4, 10000));
[x64] Implement vcvtqsi2sd AVX instruction. BUG=v8:4406 LOG=N Review URL: https://codereview.chromium.org/1413013003 Cr-Commit-Position: refs/heads/master@{#31538}
2015-10-24 16:49:35 +00:00
__ vcvtqsi2sd(xmm5, xmm9, r11);
[x64] Emit vcvttsd2si[q] when AVX is enabled. BUG=v8:4406 LOG=N Review URL: https://codereview.chromium.org/1406353003 Cr-Commit-Position: refs/heads/master@{#31348}
2015-10-18 15:43:07 +00:00
__ vcvttsd2si(r9, xmm6);
__ vcvttsd2si(rax, Operand(rbx, r9, times_4, 10000));
__ vcvttsd2siq(rdi, xmm9);
__ vcvttsd2siq(r8, Operand(r9, rbx, times_4, 10000));
[x64] Implement vcvtsd2si AVX instruction. BUG=v8:4406 LOG=N Review URL: https://codereview.chromium.org/1413903003 Cr-Commit-Position: refs/heads/master@{#31539}
2015-10-24 18:55:27 +00:00
__ vcvtsd2si(rdi, xmm9);
[x86] Introduce vandps/vandpd/vxorps/vxorpd. R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/1072343002 Cr-Commit-Position: refs/heads/master@{#27768}
2015-04-11 01:02:22 +00:00
[x64] Replace movaps with appropriate vmov* instructions when AVX is enabled. BUG=v8:4406 LOG=N Review URL: https://codereview.chromium.org/1416663004 Cr-Commit-Position: refs/heads/master@{#31391}
2015-10-20 04:58:07 +00:00
__ vmovaps(xmm10, xmm11);
[x64] Emit vmovmskpd when AVX is enabled. BUG=v8:4406 LOG=N Review URL: https://codereview.chromium.org/1411023002 Cr-Commit-Position: refs/heads/master@{#31350}
2015-10-18 16:12:24 +00:00
__ vmovapd(xmm7, xmm0);
[x64] add Absps/d and Negps/d macro BUG= Review-Url: https://codereview.chromium.org/2161513002 Cr-Commit-Position: refs/heads/master@{#37937}
2016-07-21 11:01:44 +00:00
__ vmovupd(xmm0, Operand(rbx, rcx, times_4, 10000));
__ vmovupd(Operand(rbx, rcx, times_4, 10000), xmm0);
[x64] Emit vmovmskpd when AVX is enabled. BUG=v8:4406 LOG=N Review URL: https://codereview.chromium.org/1411023002 Cr-Commit-Position: refs/heads/master@{#31350}
2015-10-18 16:12:24 +00:00
__ vmovmskpd(r9, xmm4);
[Turbofan] Support 128 bit moves/swaps for x64. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2139513002 Cr-Commit-Position: refs/heads/master@{#37654}
2016-07-11 18:18:17 +00:00
__ vmovups(xmm5, xmm1);
__ vmovups(xmm5, Operand(rdx, 4));
__ vmovups(Operand(rdx, 4), xmm5);
[x86] Introduce vandps/vandpd/vxorps/vxorpd. R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/1072343002 Cr-Commit-Position: refs/heads/master@{#27768}
2015-04-11 01:02:22 +00:00
__ vandps(xmm0, xmm9, xmm2);
__ vandps(xmm9, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vxorps(xmm0, xmm1, xmm9);
__ vxorps(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
Add phaddd/vphaddd, phaddw/vphaddw and vhaddps to ia32 Also Add vhaddps to x64 Fix haddps for SSE3 scope and disassembler on ia32/x64 Change-Id: If511e6428fa1ce034b4281943dfee1405c9d4ffc Reviewed-on: https://chromium-review.googlesource.com/939265 Reviewed-by: Deepti Gandluri <gdeepti@chromium.org> Commit-Queue: Jing Bao <jing.bao@intel.com> Cr-Commit-Position: refs/heads/master@{#51642}
2018-02-28 06:28:08 +00:00
__ vhaddps(xmm0, xmm1, xmm9);
__ vhaddps(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
[x86] Introduce vandps/vandpd/vxorps/vxorpd. R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/1072343002 Cr-Commit-Position: refs/heads/master@{#27768}
2015-04-11 01:02:22 +00:00
__ vandpd(xmm0, xmm9, xmm2);
__ vandpd(xmm9, xmm1, Operand(rbx, rcx, times_4, 10000));
[x64] Make MathMinMax use AVX instructions when available. BUG=v8:4406 LOG=N Review URL: https://codereview.chromium.org/1421733003 Cr-Commit-Position: refs/heads/master@{#31488}
2015-10-23 06:10:20 +00:00
__ vorpd(xmm0, xmm1, xmm9);
__ vorpd(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
[x86] Introduce vandps/vandpd/vxorps/vxorpd. R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/1072343002 Cr-Commit-Position: refs/heads/master@{#27768}
2015-04-11 01:02:22 +00:00
__ vxorpd(xmm0, xmm1, xmm9);
__ vxorpd(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
[x64] Implement vpcmpeqd, vpslld, vpsrld AVX instructions. BUG=v8:4406 LOG=N Review URL: https://codereview.chromium.org/1419983002 Cr-Commit-Position: refs/heads/master@{#31452}
2015-10-22 07:00:57 +00:00
__ vpcmpeqd(xmm0, xmm15, xmm5);
__ vpcmpeqd(xmm15, xmm0, Operand(rbx, rcx, times_4, 10000));
__ vpsllq(xmm0, xmm15, 21);
__ vpsrlq(xmm15, xmm0, 21);
[x64]: add cmpps/cmppd instructions BUG= Review-Url: https://codereview.chromium.org/2170323002 Cr-Commit-Position: refs/heads/master@{#38307}
2016-08-03 15:23:57 +00:00
__ vcmpps(xmm5, xmm4, xmm1, 1);
__ vcmpps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000), 1);
__ vcmpeqps(xmm5, xmm4, xmm1);
__ vcmpeqps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmpltps(xmm5, xmm4, xmm1);
__ vcmpltps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmpleps(xmm5, xmm4, xmm1);
__ vcmpleps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmpneqps(xmm5, xmm4, xmm1);
__ vcmpneqps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmpnltps(xmm5, xmm4, xmm1);
__ vcmpnltps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmpnleps(xmm5, xmm4, xmm1);
__ vcmpnleps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmppd(xmm5, xmm4, xmm1, 1);
__ vcmppd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000), 1);
__ vcmpeqpd(xmm5, xmm4, xmm1);
__ vcmpeqpd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmpltpd(xmm5, xmm4, xmm1);
__ vcmpltpd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmplepd(xmm5, xmm4, xmm1);
__ vcmplepd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmpneqpd(xmm5, xmm4, xmm1);
__ vcmpneqpd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmpnltpd(xmm5, xmm4, xmm1);
__ vcmpnltpd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
__ vcmpnlepd(xmm5, xmm4, xmm1);
__ vcmpnlepd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
[x64] supplement SSE insturctions for SIMD.js Both legacy and AVX versions BUG= Review-Url: https://codereview.chromium.org/2328843003 Cr-Commit-Position: refs/heads/master@{#39327}
2016-09-12 06:24:06 +00:00
#define EMIT_SSE2_AVXINSTR(instruction, notUsed1, notUsed2, notUsed3) \
__ v##instruction(xmm10, xmm5, xmm1); \
__ v##instruction(xmm10, xmm5, Operand(rdx, 4));
#define EMIT_SSE34_AVXINSTR(instruction, notUsed1, notUsed2, notUsed3, \
notUsed4) \
__ v##instruction(xmm10, xmm5, xmm1); \
__ v##instruction(xmm10, xmm5, Operand(rdx, 4));
SSE2_INSTRUCTION_LIST(EMIT_SSE2_AVXINSTR)
SSSE3_INSTRUCTION_LIST(EMIT_SSE34_AVXINSTR)
SSE4_INSTRUCTION_LIST(EMIT_SSE34_AVXINSTR)
#undef EMIT_SSE2_AVXINSTR
#undef EMIT_SSE34_AVXINSTR
__ vlddqu(xmm1, Operand(rbx, rcx, times_4, 10000));
__ vpsllw(xmm0, xmm15, 21);
__ vpsrlw(xmm0, xmm15, 21);
__ vpsraw(xmm0, xmm15, 21);
__ vpsrad(xmm0, xmm15, 21);
__ vpextrb(rax, xmm2, 12);
__ vpextrb(Operand(rbx, rcx, times_4, 10000), xmm2, 12);
__ vpextrw(rax, xmm2, 5);
__ vpextrw(Operand(rbx, rcx, times_4, 10000), xmm2, 5);
__ vpextrd(rax, xmm2, 2);
__ vpextrd(Operand(rbx, rcx, times_4, 10000), xmm2, 2);
__ vpinsrb(xmm1, xmm2, rax, 12);
__ vpinsrb(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 12);
__ vpinsrw(xmm1, xmm2, rax, 5);
__ vpinsrw(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 5);
__ vpinsrd(xmm1, xmm2, rax, 2);
__ vpinsrd(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 2);
__ vpshufd(xmm1, xmm2, 85);
[x64] introduce vex prefix version of float64 arithmetic binop BUG= R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/764863002 Patch from Weiliang Lin <weiliang.lin@intel.com>. Cr-Commit-Position: refs/heads/master@{#25582}
2014-12-01 10:45:02 +00:00
}
}
[x64] Introduce FMA3 instructions on scalar data elements. R=bmeurer@chromium.org Review URL: https://codereview.chromium.org/757503002 Patch from Weiliang Lin <weiliang.lin@intel.com>. Cr-Commit-Position: refs/heads/master@{#25509}
2014-11-26 05:31:41 +00:00
// FMA3 instruction
{
if (CpuFeatures::IsSupported(FMA3)) {
CpuFeatureScope scope(&assm, FMA3);
__ vfmadd132sd(xmm0, xmm1, xmm2);
__ vfmadd132sd(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfmadd213sd(xmm0, xmm1, xmm2);
__ vfmadd213sd(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfmadd231sd(xmm0, xmm1, xmm2);
__ vfmadd231sd(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfmadd132sd(xmm9, xmm10, xmm11);
__ vfmadd132sd(xmm9, xmm10, Operand(r9, r11, times_4, 10000));
__ vfmadd213sd(xmm9, xmm10, xmm11);
__ vfmadd213sd(xmm9, xmm10, Operand(r9, r11, times_4, 10000));
__ vfmadd231sd(xmm9, xmm10, xmm11);
__ vfmadd231sd(xmm9, xmm10, Operand(r9, r11, times_4, 10000));
__ vfmsub132sd(xmm0, xmm1, xmm2);
__ vfmsub132sd(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfmsub213sd(xmm0, xmm1, xmm2);
__ vfmsub213sd(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfmsub231sd(xmm0, xmm1, xmm2);
__ vfmsub231sd(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfnmadd132sd(xmm0, xmm1, xmm2);
__ vfnmadd132sd(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfnmadd213sd(xmm0, xmm1, xmm2);
__ vfnmadd213sd(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfnmadd231sd(xmm0, xmm1, xmm2);
__ vfnmadd231sd(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfnmsub132sd(xmm0, xmm1, xmm2);
__ vfnmsub132sd(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfnmsub213sd(xmm0, xmm1, xmm2);
__ vfnmsub213sd(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfnmsub231sd(xmm0, xmm1, xmm2);
__ vfnmsub231sd(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfmadd132ss(xmm0, xmm1, xmm2);
__ vfmadd132ss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfmadd213ss(xmm0, xmm1, xmm2);
__ vfmadd213ss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfmadd231ss(xmm0, xmm1, xmm2);
__ vfmadd231ss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfmsub132ss(xmm0, xmm1, xmm2);
__ vfmsub132ss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfmsub213ss(xmm0, xmm1, xmm2);
__ vfmsub213ss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfmsub231ss(xmm0, xmm1, xmm2);
__ vfmsub231ss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfnmadd132ss(xmm0, xmm1, xmm2);
__ vfnmadd132ss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfnmadd213ss(xmm0, xmm1, xmm2);
__ vfnmadd213ss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfnmadd231ss(xmm0, xmm1, xmm2);
__ vfnmadd231ss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfnmsub132ss(xmm0, xmm1, xmm2);
__ vfnmsub132ss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfnmsub213ss(xmm0, xmm1, xmm2);
__ vfnmsub213ss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
__ vfnmsub231ss(xmm0, xmm1, xmm2);
__ vfnmsub231ss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
}
}
[x64] Introduce BMI instructions. BUG=v8:4015 LOG=n Review URL: https://codereview.chromium.org/1040603002 Cr-Commit-Position: refs/heads/master@{#27648}
2015-04-08 07:15:51 +00:00
// BMI1 instructions
{
if (CpuFeatures::IsSupported(BMI1)) {
CpuFeatureScope scope(&assm, BMI1);
__ andnq(rax, rbx, rcx);
__ andnq(rax, rbx, Operand(rbx, rcx, times_4, 10000));
__ andnl(rax, rbx, rcx);
__ andnl(rax, rbx, Operand(rbx, rcx, times_4, 10000));
__ bextrq(rax, rbx, rcx);
__ bextrq(rax, Operand(rbx, rcx, times_4, 10000), rbx);
__ bextrl(rax, rbx, rcx);
__ bextrl(rax, Operand(rbx, rcx, times_4, 10000), rbx);
__ blsiq(rax, rbx);
__ blsiq(rax, Operand(rbx, rcx, times_4, 10000));
__ blsil(rax, rbx);
__ blsil(rax, Operand(rbx, rcx, times_4, 10000));
__ blsmskq(rax, rbx);
__ blsmskq(rax, Operand(rbx, rcx, times_4, 10000));
__ blsmskl(rax, rbx);
__ blsmskl(rax, Operand(rbx, rcx, times_4, 10000));
__ blsrq(rax, rbx);
__ blsrq(rax, Operand(rbx, rcx, times_4, 10000));
__ blsrl(rax, rbx);
__ blsrl(rax, Operand(rbx, rcx, times_4, 10000));
__ tzcntq(rax, rbx);
__ tzcntq(rax, Operand(rbx, rcx, times_4, 10000));
__ tzcntl(rax, rbx);
__ tzcntl(rax, Operand(rbx, rcx, times_4, 10000));
}
}
// LZCNT instructions
{
if (CpuFeatures::IsSupported(LZCNT)) {
CpuFeatureScope scope(&assm, LZCNT);
__ lzcntq(rax, rbx);
__ lzcntq(rax, Operand(rbx, rcx, times_4, 10000));
__ lzcntl(rax, rbx);
__ lzcntl(rax, Operand(rbx, rcx, times_4, 10000));
}
}
// POPCNT instructions
{
if (CpuFeatures::IsSupported(POPCNT)) {
CpuFeatureScope scope(&assm, POPCNT);
__ popcntq(rax, rbx);
__ popcntq(rax, Operand(rbx, rcx, times_4, 10000));
__ popcntl(rax, rbx);
__ popcntl(rax, Operand(rbx, rcx, times_4, 10000));
}
}
// BMI2 instructions
{
if (CpuFeatures::IsSupported(BMI2)) {
CpuFeatureScope scope(&assm, BMI2);
__ bzhiq(rax, rbx, rcx);
__ bzhiq(rax, Operand(rbx, rcx, times_4, 10000), rbx);
__ bzhil(rax, rbx, rcx);
__ bzhil(rax, Operand(rbx, rcx, times_4, 10000), rbx);
__ mulxq(rax, rbx, rcx);
__ mulxq(rax, rbx, Operand(rbx, rcx, times_4, 10000));
__ mulxl(rax, rbx, rcx);
__ mulxl(rax, rbx, Operand(rbx, rcx, times_4, 10000));
__ pdepq(rax, rbx, rcx);
__ pdepq(rax, rbx, Operand(rbx, rcx, times_4, 10000));
__ pdepl(rax, rbx, rcx);
__ pdepl(rax, rbx, Operand(rbx, rcx, times_4, 10000));
__ pextq(rax, rbx, rcx);
__ pextq(rax, rbx, Operand(rbx, rcx, times_4, 10000));
__ pextl(rax, rbx, rcx);
__ pextl(rax, rbx, Operand(rbx, rcx, times_4, 10000));
__ sarxq(rax, rbx, rcx);
__ sarxq(rax, Operand(rbx, rcx, times_4, 10000), rbx);
__ sarxl(rax, rbx, rcx);
__ sarxl(rax, Operand(rbx, rcx, times_4, 10000), rbx);
__ shlxq(rax, rbx, rcx);
__ shlxq(rax, Operand(rbx, rcx, times_4, 10000), rbx);
__ shlxl(rax, rbx, rcx);
__ shlxl(rax, Operand(rbx, rcx, times_4, 10000), rbx);
__ shrxq(rax, rbx, rcx);
__ shrxq(rax, Operand(rbx, rcx, times_4, 10000), rbx);
__ shrxl(rax, rbx, rcx);
__ shrxl(rax, Operand(rbx, rcx, times_4, 10000), rbx);
__ rorxq(rax, rbx, 63);
__ rorxq(rax, Operand(rbx, rcx, times_4, 10000), 63);
__ rorxl(rax, rbx, 31);
__ rorxl(rax, Operand(rbx, rcx, times_4, 10000), 31);
}
}
Land the Fan (disabled) R=mstarzinger@chromium.org Review URL: https://codereview.chromium.org/426233002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22709 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-07-30 13:54:45 +00:00
// xchg.
{
Add cmpxchg and lock instructions to x64 and ia32 {dis,}assemblers Review-Url: https://codereview.chromium.org/1986113004 Cr-Commit-Position: refs/heads/master@{#36341}
2016-05-19 00:55:08 +00:00
__ xchgb(rax, Operand(rax, 8));
__ xchgw(rax, Operand(rbx, 8));
Land the Fan (disabled) R=mstarzinger@chromium.org Review URL: https://codereview.chromium.org/426233002 git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22709 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-07-30 13:54:45 +00:00
__ xchgq(rax, rax);
__ xchgq(rax, rbx);
__ xchgq(rbx, rbx);
__ xchgq(rbx, Operand(rsp, 12));
}
Add cmpxchg and lock instructions to x64 and ia32 {dis,}assemblers Review-Url: https://codereview.chromium.org/1986113004 Cr-Commit-Position: refs/heads/master@{#36341}
2016-05-19 00:55:08 +00:00
// cmpxchg.
{
__ cmpxchgb(Operand(rsp, 12), rax);
__ cmpxchgw(Operand(rbx, rcx, times_4, 10000), rax);
__ cmpxchgl(Operand(rbx, rcx, times_4, 10000), rax);
__ cmpxchgq(Operand(rbx, rcx, times_4, 10000), rax);
}
// lock prefix.
{
__ lock();
__ cmpxchgl(Operand(rsp, 12), rbx);
__ lock();
__ xchgw(rax, Operand(rcx, 8));
}
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
// Nop instructions
for (int i = 0; i < 16; i++) {
__ Nop(i);
}
[x64] Add disassembler support for 'pause' The 'pause' instruction is used for implementing retpolines. It is currently being printed as 'nop', which is incorrect. R=titzer@chromium.org Change-Id: I134b6dae332103fd7f9b3c4e5520f0d5db06ba74 Reviewed-on: https://chromium-review.googlesource.com/1051789 Reviewed-by: Ben Titzer <titzer@chromium.org> Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Cr-Commit-Position: refs/heads/master@{#53109}
2018-05-09 15:02:15 +00:00
__ pause();
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
__ ret(0);
CodeDesc desc;
[compiler] Delay allocation of code-embedded heap numbers. Instead of allocating and embedding certain heap numbers into the code during code assembly, emit dummies but record the allocation requests. Later then, in Assembler::GetCode, allocate the heap numbers and patch the code by replacing the dummies with the actual objects. The RelocInfos for the embedded objects are already recorded correctly when emitting the dummies. R=jarin@chromium.org BUG=v8:6048 Review-Url: https://codereview.chromium.org/2900683002 Cr-Commit-Position: refs/heads/master@{#45635}
2017-05-31 14:00:11 +00:00
assm.GetCode(isolate, &desc);
Remove ComputeFlags, simply pass in Code::Kind instead of Code::Flags TBR: ofrobots@google.com, yangguo@chromium.org Bug: Change-Id: I6cb0704acabf9a7f2334de539a6600db8607baef Reviewed-on: https://chromium-review.googlesource.com/691720 Commit-Queue: Toon Verwaest <verwaest@chromium.org> Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#48237}
2017-09-29 14:59:24 +00:00
Handle<Code> code =
isolate->factory()->NewCode(desc, Code::STUB, Handle<Code>());
Fix unused variable warnings. TBR=jarin@chromium.org Review URL: https://codereview.chromium.org/238543008 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@20797 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2014-04-16 11:50:24 +00:00
USE(code);
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
#ifdef OBJECT_PRINT
Reland "Introduce StdoutStream which prints to Android log or stdout" This is a reland of 0909dbe3d6eba64725218f89f7f11a97537bab6e. Added missing V8_EXPORT_PRIVATE to AndroidLogStream. TBR=mstarzinger@chromium.org Original change's description: > Introduce StdoutStream which prints to Android log or stdout > > The often used construct {OFStream(stdout)} does not work on Android. > This CL introduces an {StdoutStream} which behaves exactly like > {OFStream(stdout)} on non-android platforms, and redirects to the > Android log on appropriate systems and configurations. > > R=mstarzinger@chromium.org > > Bug: v8:7820 > Change-Id: Ia682fdf6d064e37c605c19b032f5a10b96ac825b > Reviewed-on: https://chromium-review.googlesource.com/1088911 > Reviewed-by: Benedikt Meurer <bmeurer@chromium.org> > Reviewed-by: Jakob Gruber <jgruber@chromium.org> > Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> > Commit-Queue: Clemens Hammacher <clemensh@chromium.org> > Cr-Commit-Position: refs/heads/master@{#53692} Bug: v8:7820 Change-Id: I8164bad78a401dbe4246c9ffcacd050fe511ed58 Reviewed-on: https://chromium-review.googlesource.com/1100636 Reviewed-by: Clemens Hammacher <clemensh@chromium.org> Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Cr-Commit-Position: refs/heads/master@{#53733}
2018-06-14 12:46:07 +00:00
StdoutStream os;
[cleanup] Remove Isolate parameter from object print With ReadOnlyRoots and GetIsolate on JSReceiver, we can remove almost every isolate parameter from <Object>::Print. The remaining ones, like Map, are special-caseable for read-only maps, and as a result we can remove isolate parameters from <Object>::Print entirely. This patch also opportunistically cleans up a few places where isolates were only needed for Object::Print, such as TransitionAccessors and DescriptorArrays. TBR=yangguo@chromium.org,mstarzinger@chromium.org Bug: v8:7786 Change-Id: Id44bd53b9893e679eea5f37b9548257595a1bfd9 Reviewed-on: https://chromium-review.googlesource.com/1133385 Reviewed-by: Leszek Swirski <leszeks@chromium.org> Reviewed-by: Dan Elphick <delphick@chromium.org> Commit-Queue: Leszek Swirski <leszeks@chromium.org> Cr-Commit-Position: refs/heads/master@{#54401}
2018-07-12 10:06:42 +00:00
code->Print(os);
[ubsan] Change Address typedef to uintptr_t The "Address" type is V8's general-purpose type for manipulating memory addresses. Per the C++ spec, pointer arithmetic and pointer comparisons are undefined behavior except within the same array; since we generally don't operate within a C++ array, our general-purpose type shouldn't be a pointer type. Bug: v8:3770 Cq-Include-Trybots: luci.chromium.try:linux_chromium_rel_ng;master.tryserver.blink:linux_trusty_blink_rel Change-Id: Ib96016c24a0f18bcdba916dabd83e3f24a1b5779 Reviewed-on: https://chromium-review.googlesource.com/988657 Commit-Queue: Jakob Kummerow <jkummerow@chromium.org> Reviewed-by: Leszek Swirski <leszeks@chromium.org> Cr-Commit-Position: refs/heads/master@{#52601}
2018-04-13 22:28:05 +00:00
Address begin = code->raw_instruction_start();
Address end = code->raw_instruction_end();
disasm::Disassembler::Disassemble(stdout, reinterpret_cast<byte*>(begin),
reinterpret_cast<byte*>(end));
Clean up multi byte nop support on x64 to more closely match IA32. Fix missing instruction in disassembler. Fix wrong disassembly of multi-byte NOP on x64 Add test of disassembler on 64 bit! Review URL: http://codereview.chromium.org/8773039 git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10147 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2011-12-05 08:58:01 +00:00
#endif
}
#undef __
Start preparing test/cctest for jumbo compilation * Avoid "using namespace" statements, which trigger clang's -Wheader-hygiene warnings in jumbo builds. * Undefine created macros at the end of source files. BUG=chromium:746958 Change-Id: I5d25432c314437f607b0e1be22765a6764267ba6 Reviewed-on: https://chromium-review.googlesource.com/610962 Reviewed-by: Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Mostyn Bramley-Moore <mostynb@opera.com> Cr-Commit-Position: refs/heads/master@{#47347}
2017-08-11 11:22:28 +00:00
} // namespace internal
} // namespace v8
Reference in New Issue Copy Permalink