2011-04-06 09:06:23 +00:00
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// Copyright 2011 the V8 project authors. All rights reserved.
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2008-08-22 13:33:59 +00:00
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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2019-05-15 12:51:26 +00:00
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#include <cinttypes>
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#include <cstdlib>
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2008-08-22 13:33:59 +00:00
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2018-04-23 15:44:01 +00:00
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// The C++ style guide recommends using <re2> instead of <regex>. However, the
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// former isn't available in V8.
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#include <regex> // NOLINT(build/c++11)
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2019-05-21 09:30:15 +00:00
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#include "src/codegen/assembler-inl.h"
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#include "src/codegen/macro-assembler.h"
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2015-07-31 11:07:50 +00:00
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#include "src/debug/debug.h"
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2019-05-20 09:15:06 +00:00
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#include "src/diagnostics/disasm.h"
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#include "src/diagnostics/disassembler.h"
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2019-05-22 07:55:37 +00:00
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#include "src/execution/frames-inl.h"
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2019-05-24 13:51:59 +00:00
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#include "src/init/v8.h"
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2019-05-15 18:28:45 +00:00
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#include "src/numbers/double.h"
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2019-05-23 08:51:46 +00:00
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#include "src/objects/objects-inl.h"
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2019-05-24 13:51:59 +00:00
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#include "src/utils/boxed-float.h"
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2014-06-03 08:12:43 +00:00
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#include "test/cctest/cctest.h"
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2008-08-22 13:33:59 +00:00
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2017-08-31 12:34:55 +00:00
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namespace v8 {
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namespace internal {
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2008-08-22 13:33:59 +00:00
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2018-04-23 15:44:01 +00:00
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enum UseRegex { kRawString, kRegexString };
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2017-06-22 10:00:56 +00:00
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template <typename... S>
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2018-04-23 15:44:01 +00:00
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bool DisassembleAndCompare(byte* begin, UseRegex use_regex,
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S... expected_strings) {
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2008-11-05 19:18:10 +00:00
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disasm::NameConverter converter;
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disasm::Disassembler disasm(converter);
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2017-06-22 10:00:56 +00:00
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EmbeddedVector<char, 128> buffer;
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std::vector<std::string> expected_disassembly = {expected_strings...};
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size_t n_expected = expected_disassembly.size();
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2018-08-07 11:31:32 +00:00
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byte* end = begin + (n_expected * kInstrSize);
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2017-06-22 10:00:56 +00:00
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std::vector<std::string> disassembly;
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for (byte* pc = begin; pc < end;) {
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pc += disasm.InstructionDecode(buffer, pc);
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2019-04-29 11:06:49 +00:00
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disassembly.emplace_back(buffer.begin());
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2008-08-22 13:33:59 +00:00
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}
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2017-06-22 10:00:56 +00:00
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bool test_passed = true;
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for (size_t i = 0; i < disassembly.size(); i++) {
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2018-04-23 15:44:01 +00:00
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if (use_regex == kRawString) {
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if (expected_disassembly[i] != disassembly[i]) {
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fprintf(stderr,
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"expected: \n"
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"%s\n"
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"disassembled: \n"
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"%s\n\n",
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expected_disassembly[i].c_str(), disassembly[i].c_str());
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test_passed = false;
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}
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} else {
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DCHECK_EQ(use_regex, kRegexString);
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if (!std::regex_match(disassembly[i],
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std::regex(expected_disassembly[i]))) {
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fprintf(stderr,
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"expected (regex): \n"
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"%s\n"
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"disassembled: \n"
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"%s\n\n",
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expected_disassembly[i].c_str(), disassembly[i].c_str());
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test_passed = false;
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}
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2017-06-22 10:00:56 +00:00
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}
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}
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[arm] Support splitting add with immediate instructions
When an immediate does not fit an add instruction we use a temporary register to
hold the value, using movw/movt to encode it. However, in order to remove a use
of r9 in TurboFan's code generator, we need to cope with no scratch registers
being available. That is to say that the destination and source registers are
the same, and `ip` is not available to use.
In this case, we can split an add instruction into a sequence of additions:
```
UseScratchRegisterScope temps(...);
Register my_scratch = temps.Acquire();
__ add(r0, r0, Operand(0xabcd); // add r0, r0, #0xcd
// add r0, r0, #0xab00
```
As a drive-by fix, make the disassembler test fail if we expected a different
number of instructions generated.
Bug: v8:6553
Change-Id: Ib7fcc765d28bccafe39257f47cd73f922c5873bf
Reviewed-on: https://chromium-review.googlesource.com/685014
Reviewed-by: Benedikt Meurer <bmeurer@chromium.org>
Commit-Queue: Pierre Langlois <pierre.langlois@arm.com>
Cr-Commit-Position: refs/heads/master@{#48491}
2017-10-11 12:00:21 +00:00
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// Fail after printing expected disassembly if we expected a different number
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// of instructions.
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if (disassembly.size() != expected_disassembly.size()) {
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return false;
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}
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2017-06-22 10:00:56 +00:00
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return test_passed;
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}
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2008-08-22 13:33:59 +00:00
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2012-01-13 13:09:52 +00:00
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// Set up V8 to a state where we can at least run the assembler and
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2008-11-05 19:18:10 +00:00
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// disassembler. Declare the variables and allocate the data structures used
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// in the rest of the macros.
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2019-01-16 18:29:52 +00:00
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#define SET_UP() \
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CcTest::InitializeVM(); \
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Isolate* isolate = CcTest::i_isolate(); \
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HandleScope scope(isolate); \
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byte* buffer = reinterpret_cast<byte*>(malloc(4 * 1024)); \
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Assembler assm(AssemblerOptions{}, \
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ExternalAssemblerBuffer(buffer, 4 * 1024)); \
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2008-08-22 13:33:59 +00:00
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bool failure = false;
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2008-11-05 19:18:10 +00:00
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// This macro assembles one instruction using the preallocated assembler and
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// disassembles the generated instruction, comparing the output to the expected
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// value. If the comparison fails an error message is printed, but the test
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// continues to run until the end.
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2018-04-23 15:44:01 +00:00
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#define BASE_COMPARE(asm_, use_regex, ...) \
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{ \
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int pc_offset = assm.pc_offset(); \
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byte* progcounter = &buffer[pc_offset]; \
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assm.asm_; \
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if (!DisassembleAndCompare(progcounter, use_regex, __VA_ARGS__)) { \
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failure = true; \
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} \
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2008-08-22 13:33:59 +00:00
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}
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2018-04-23 15:44:01 +00:00
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#define COMPARE(asm_, ...) BASE_COMPARE(asm_, kRawString, __VA_ARGS__)
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#define COMPARE_REGEX(asm_, ...) BASE_COMPARE(asm_, kRegexString, __VA_ARGS__)
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2012-06-12 17:26:28 +00:00
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// Force emission of any pending literals into a pool.
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#define EMIT_PENDING_LITERALS() \
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assm.CheckConstPool(true, false)
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2008-08-22 13:33:59 +00:00
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2008-11-05 19:18:10 +00:00
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// Verify that all invocations of the COMPARE macro passed successfully.
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// Exit with a failure if at least one of the tests failed.
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2019-05-10 18:55:22 +00:00
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#define VERIFY_RUN() \
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if (failure) { \
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FATAL("ARM Disassembler tests failed.\n"); \
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2008-08-22 13:33:59 +00:00
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}
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2015-03-30 07:33:46 +00:00
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// clang-format off
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2008-08-22 13:33:59 +00:00
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TEST(Type0) {
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2012-01-13 13:09:52 +00:00
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SET_UP();
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2008-08-22 13:33:59 +00:00
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COMPARE(and_(r0, r1, Operand(r2)),
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"e0010002 and r0, r1, r2");
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COMPARE(and_(r1, r2, Operand(r3), LeaveCC),
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"e0021003 and r1, r2, r3");
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COMPARE(and_(r2, r3, Operand(r4), SetCC),
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"e0132004 ands r2, r3, r4");
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COMPARE(and_(r3, r4, Operand(r5), LeaveCC, eq),
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"00043005 andeq r3, r4, r5");
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COMPARE(eor(r4, r5, Operand(r6, LSL, 0)),
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"e0254006 eor r4, r5, r6");
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COMPARE(eor(r4, r5, Operand(r7, LSL, 1), SetCC),
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"e0354087 eors r4, r5, r7, lsl #1");
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COMPARE(eor(r4, r5, Operand(r8, LSL, 2), LeaveCC, ne),
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"10254108 eorne r4, r5, r8, lsl #2");
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COMPARE(eor(r4, r5, Operand(r9, LSL, 3), SetCC, cs),
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"20354189 eorcss r4, r5, r9, lsl #3");
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COMPARE(sub(r5, r6, Operand(r10, LSL, 31), LeaveCC, hs),
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2009-08-24 11:57:57 +00:00
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"20465f8a subcs r5, r6, r10, lsl #31");
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2008-08-22 13:33:59 +00:00
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COMPARE(sub(r5, r6, Operand(r10, LSL, 30), SetCC, cc),
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2009-08-24 11:57:57 +00:00
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"30565f0a subccs r5, r6, r10, lsl #30");
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2008-08-22 13:33:59 +00:00
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COMPARE(sub(r5, r6, Operand(r10, LSL, 24), LeaveCC, lo),
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2009-08-24 11:57:57 +00:00
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"30465c0a subcc r5, r6, r10, lsl #24");
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2008-08-22 13:33:59 +00:00
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COMPARE(sub(r5, r6, Operand(r10, LSL, 16), SetCC, mi),
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2009-08-24 11:57:57 +00:00
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"4056580a submis r5, r6, r10, lsl #16");
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2008-08-22 13:33:59 +00:00
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COMPARE(rsb(r6, r7, Operand(fp)),
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"e067600b rsb r6, r7, fp");
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COMPARE(rsb(r6, r7, Operand(fp, LSR, 1)),
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"e06760ab rsb r6, r7, fp, lsr #1");
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COMPARE(rsb(r6, r7, Operand(fp, LSR, 0), SetCC),
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"e077602b rsbs r6, r7, fp, lsr #32");
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COMPARE(rsb(r6, r7, Operand(fp, LSR, 31), LeaveCC, pl),
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"50676fab rsbpl r6, r7, fp, lsr #31");
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COMPARE(add(r7, r8, Operand(ip, ASR, 1)),
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"e08870cc add r7, r8, ip, asr #1");
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COMPARE(add(r7, r8, Operand(ip, ASR, 0)),
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"e088704c add r7, r8, ip, asr #32");
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COMPARE(add(r7, r8, Operand(ip), SetCC),
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"e098700c adds r7, r8, ip");
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COMPARE(add(r7, r8, Operand(ip, ASR, 31), SetCC, vs),
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"60987fcc addvss r7, r8, ip, asr #31");
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COMPARE(adc(r7, fp, Operand(ip, ASR, 5)),
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"e0ab72cc adc r7, fp, ip, asr #5");
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COMPARE(adc(r4, ip, Operand(ip, ASR, 1), LeaveCC, vc),
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"70ac40cc adcvc r4, ip, ip, asr #1");
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COMPARE(adc(r5, sp, Operand(ip), SetCC),
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"e0bd500c adcs r5, sp, ip");
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COMPARE(adc(r8, lr, Operand(ip, ASR, 31), SetCC, vc),
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"70be8fcc adcvcs r8, lr, ip, asr #31");
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COMPARE(sbc(r7, r1, Operand(ip, ROR, 1), LeaveCC, hi),
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"80c170ec sbchi r7, r1, ip, ror #1");
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COMPARE(sbc(r7, r9, Operand(ip, ROR, 4)),
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"e0c9726c sbc r7, r9, ip, ror #4");
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COMPARE(sbc(r7, r10, Operand(ip), SetCC),
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2009-08-24 11:57:57 +00:00
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"e0da700c sbcs r7, r10, ip");
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2008-08-22 13:33:59 +00:00
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COMPARE(sbc(r7, ip, Operand(ip, ROR, 31), SetCC, hi),
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"80dc7fec sbchis r7, ip, ip, ror #31");
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COMPARE(rsc(r7, r8, Operand(ip, LSL, r0)),
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"e0e8701c rsc r7, r8, ip, lsl r0");
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COMPARE(rsc(r7, r8, Operand(ip, LSL, r1)),
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"e0e8711c rsc r7, r8, ip, lsl r1");
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COMPARE(rsc(r7, r8, Operand(ip), SetCC),
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"e0f8700c rscs r7, r8, ip");
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COMPARE(rsc(r7, r8, Operand(ip, LSL, r3), SetCC, ls),
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"90f8731c rsclss r7, r8, ip, lsl r3");
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COMPARE(tst(r7, Operand(r5, ASR, ip), ge),
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"a1170c55 tstge r7, r5, asr ip");
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COMPARE(tst(r7, Operand(r6, ASR, sp)),
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"e1170d56 tst r7, r6, asr sp");
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COMPARE(tst(r7, Operand(r7), ge),
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"a1170007 tstge r7, r7");
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COMPARE(tst(r7, Operand(r8, ASR, fp), ge),
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"a1170b58 tstge r7, r8, asr fp");
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COMPARE(teq(r7, Operand(r5, ROR, r0), lt),
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"b1370075 teqlt r7, r5, ror r0");
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COMPARE(teq(r7, Operand(r6, ROR, lr)),
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"e1370e76 teq r7, r6, ror lr");
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COMPARE(teq(r7, Operand(r7), lt),
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"b1370007 teqlt r7, r7");
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|
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COMPARE(teq(r7, Operand(r8, ROR, r1)),
|
|
|
|
|
"e1370178 teq r7, r8, ror r1");
|
|
|
|
|
|
|
|
|
|
COMPARE(cmp(r7, Operand(r4)),
|
|
|
|
|
"e1570004 cmp r7, r4");
|
|
|
|
|
COMPARE(cmp(r7, Operand(r6, LSL, 1), gt),
|
|
|
|
|
"c1570086 cmpgt r7, r6, lsl #1");
|
|
|
|
|
COMPARE(cmp(r7, Operand(r8, LSR, 3), gt),
|
|
|
|
|
"c15701a8 cmpgt r7, r8, lsr #3");
|
|
|
|
|
COMPARE(cmp(r7, Operand(r8, ASR, 19)),
|
|
|
|
|
"e15709c8 cmp r7, r8, asr #19");
|
|
|
|
|
|
|
|
|
|
COMPARE(cmn(r0, Operand(r4)),
|
|
|
|
|
"e1700004 cmn r0, r4");
|
|
|
|
|
COMPARE(cmn(r1, Operand(r6, ROR, 1)),
|
|
|
|
|
"e17100e6 cmn r1, r6, ror #1");
|
|
|
|
|
COMPARE(cmn(r2, Operand(r8)),
|
|
|
|
|
"e1720008 cmn r2, r8");
|
|
|
|
|
COMPARE(cmn(r3, Operand(fp), le),
|
|
|
|
|
"d173000b cmnle r3, fp");
|
|
|
|
|
|
|
|
|
|
COMPARE(orr(r7, r8, Operand(lr), LeaveCC, al),
|
|
|
|
|
"e188700e orr r7, r8, lr");
|
|
|
|
|
COMPARE(orr(r7, r8, Operand(fp)),
|
|
|
|
|
"e188700b orr r7, r8, fp");
|
|
|
|
|
COMPARE(orr(r7, r8, Operand(sp), SetCC),
|
|
|
|
|
"e198700d orrs r7, r8, sp");
|
|
|
|
|
COMPARE(orr(r7, r8, Operand(ip), SetCC, al),
|
|
|
|
|
"e198700c orrs r7, r8, ip");
|
|
|
|
|
|
|
|
|
|
COMPARE(mov(r0, Operand(r1), LeaveCC, eq),
|
|
|
|
|
"01a00001 moveq r0, r1");
|
|
|
|
|
COMPARE(mov(r0, Operand(r2)),
|
|
|
|
|
"e1a00002 mov r0, r2");
|
|
|
|
|
COMPARE(mov(r0, Operand(r3), SetCC),
|
|
|
|
|
"e1b00003 movs r0, r3");
|
|
|
|
|
COMPARE(mov(r0, Operand(r4), SetCC, pl),
|
|
|
|
|
"51b00004 movpls r0, r4");
|
|
|
|
|
|
|
|
|
|
COMPARE(bic(r0, lr, Operand(r1), LeaveCC, vs),
|
|
|
|
|
"61ce0001 bicvs r0, lr, r1");
|
|
|
|
|
COMPARE(bic(r0, r9, Operand(r2), LeaveCC, vc),
|
|
|
|
|
"71c90002 bicvc r0, r9, r2");
|
|
|
|
|
COMPARE(bic(r0, r5, Operand(r3), SetCC),
|
|
|
|
|
"e1d50003 bics r0, r5, r3");
|
|
|
|
|
COMPARE(bic(r0, r1, Operand(r4), SetCC, pl),
|
|
|
|
|
"51d10004 bicpls r0, r1, r4");
|
|
|
|
|
|
|
|
|
|
COMPARE(mvn(r10, Operand(r1)),
|
2009-08-24 11:57:57 +00:00
|
|
|
"e1e0a001 mvn r10, r1");
|
2008-08-22 13:33:59 +00:00
|
|
|
COMPARE(mvn(r9, Operand(r2)),
|
|
|
|
|
"e1e09002 mvn r9, r2");
|
|
|
|
|
COMPARE(mvn(r0, Operand(r3), SetCC),
|
|
|
|
|
"e1f00003 mvns r0, r3");
|
|
|
|
|
COMPARE(mvn(r5, Operand(r4), SetCC, cc),
|
|
|
|
|
"31f05004 mvnccs r5, r4");
|
|
|
|
|
|
2010-06-14 11:20:36 +00:00
|
|
|
// Instructions autotransformed by the assembler.
|
|
|
|
|
// mov -> mvn.
|
|
|
|
|
COMPARE(mov(r3, Operand(-1), LeaveCC, al),
|
|
|
|
|
"e3e03000 mvn r3, #0");
|
|
|
|
|
COMPARE(mov(r4, Operand(-2), SetCC, al),
|
|
|
|
|
"e3f04001 mvns r4, #1");
|
2017-12-02 00:30:37 +00:00
|
|
|
COMPARE(mov(r5, Operand(0x0FFFFFF0), SetCC, ne),
|
2010-06-14 11:20:36 +00:00
|
|
|
"13f052ff mvnnes r5, #-268435441");
|
|
|
|
|
COMPARE(mov(r6, Operand(-1), LeaveCC, ne),
|
|
|
|
|
"13e06000 mvnne r6, #0");
|
|
|
|
|
|
|
|
|
|
// mvn -> mov.
|
|
|
|
|
COMPARE(mvn(r3, Operand(-1), LeaveCC, al),
|
|
|
|
|
"e3a03000 mov r3, #0");
|
|
|
|
|
COMPARE(mvn(r4, Operand(-2), SetCC, al),
|
|
|
|
|
"e3b04001 movs r4, #1");
|
2017-12-02 00:30:37 +00:00
|
|
|
COMPARE(mvn(r5, Operand(0x0FFFFFF0), SetCC, ne),
|
2010-06-14 11:20:36 +00:00
|
|
|
"13b052ff movnes r5, #-268435441");
|
|
|
|
|
COMPARE(mvn(r6, Operand(-1), LeaveCC, ne),
|
|
|
|
|
"13a06000 movne r6, #0");
|
|
|
|
|
|
2010-06-22 08:38:32 +00:00
|
|
|
// mov -> movw.
|
2011-03-31 16:17:37 +00:00
|
|
|
if (CpuFeatures::IsSupported(ARMv7)) {
|
2010-06-22 08:38:32 +00:00
|
|
|
COMPARE(mov(r5, Operand(0x01234), LeaveCC, ne),
|
|
|
|
|
"13015234 movwne r5, #4660");
|
|
|
|
|
COMPARE(eor(r5, r4, Operand(0x1234), LeaveCC, ne),
|
2017-06-22 10:00:56 +00:00
|
|
|
"13015234 movwne r5, #4660",
|
|
|
|
|
"10245005 eorne r5, r4, r5");
|
|
|
|
|
// Movw can't do setcc, so first move to r5, then the following instruction
|
|
|
|
|
// sets the flags. Mov immediate with setcc is pretty strange anyway.
|
2010-06-22 08:38:32 +00:00
|
|
|
COMPARE(mov(r5, Operand(0x01234), SetCC, ne),
|
2017-06-22 10:00:56 +00:00
|
|
|
"13015234 movwne r5, #4660",
|
|
|
|
|
"11b05005 movnes r5, r5");
|
2012-06-12 17:26:28 +00:00
|
|
|
// Emit a literal pool now, otherwise this could be dumped later, in the
|
|
|
|
|
// middle of a different test.
|
|
|
|
|
EMIT_PENDING_LITERALS();
|
|
|
|
|
|
2010-06-22 08:38:32 +00:00
|
|
|
// The eor does the setcc so we get a movw here.
|
|
|
|
|
COMPARE(eor(r5, r4, Operand(0x1234), SetCC, ne),
|
2017-06-22 10:00:56 +00:00
|
|
|
"13015234 movwne r5, #4660",
|
|
|
|
|
"10345005 eornes r5, r4, r5");
|
2010-06-22 08:38:32 +00:00
|
|
|
|
|
|
|
|
COMPARE(movt(r5, 0x4321, ne),
|
|
|
|
|
"13445321 movtne r5, #17185");
|
2017-12-02 00:30:37 +00:00
|
|
|
COMPARE(movw(r5, 0xABCD, eq),
|
2010-06-22 08:38:32 +00:00
|
|
|
"030a5bcd movweq r5, #43981");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Eor doesn't have an eor-negative variant, but we can do an mvn followed by
|
|
|
|
|
// an eor to get the same effect.
|
2017-12-02 00:30:37 +00:00
|
|
|
COMPARE(eor(r5, r4, Operand(0xFFFFFF34), SetCC, ne),
|
2017-06-22 10:00:56 +00:00
|
|
|
"13e050cb mvnne r5, #203",
|
|
|
|
|
"10345005 eornes r5, r4, r5");
|
2010-06-22 08:38:32 +00:00
|
|
|
|
2010-06-14 11:20:36 +00:00
|
|
|
// and <-> bic.
|
2017-12-02 00:30:37 +00:00
|
|
|
COMPARE(and_(r3, r5, Operand(0xFC03FFFF)),
|
2010-06-14 11:20:36 +00:00
|
|
|
"e3c537ff bic r3, r5, #66846720");
|
2017-12-02 00:30:37 +00:00
|
|
|
COMPARE(bic(r3, r5, Operand(0xFC03FFFF)),
|
2010-06-14 11:20:36 +00:00
|
|
|
"e20537ff and r3, r5, #66846720");
|
|
|
|
|
|
|
|
|
|
// sub <-> add.
|
|
|
|
|
COMPARE(add(r3, r5, Operand(-1024)),
|
|
|
|
|
"e2453b01 sub r3, r5, #1024");
|
|
|
|
|
COMPARE(sub(r3, r5, Operand(-1024)),
|
|
|
|
|
"e2853b01 add r3, r5, #1024");
|
|
|
|
|
|
|
|
|
|
// cmp <-> cmn.
|
|
|
|
|
COMPARE(cmp(r3, Operand(-1024)),
|
|
|
|
|
"e3730b01 cmn r3, #1024");
|
|
|
|
|
COMPARE(cmn(r3, Operand(-1024)),
|
|
|
|
|
"e3530b01 cmp r3, #1024");
|
|
|
|
|
|
2010-04-08 13:30:48 +00:00
|
|
|
// Miscellaneous instructions encoded as type 0.
|
|
|
|
|
COMPARE(blx(ip),
|
|
|
|
|
"e12fff3c blx ip");
|
|
|
|
|
COMPARE(bkpt(0),
|
|
|
|
|
"e1200070 bkpt 0");
|
2017-12-02 00:30:37 +00:00
|
|
|
COMPARE(bkpt(0xFFFF),
|
2010-04-08 13:30:48 +00:00
|
|
|
"e12fff7f bkpt 65535");
|
|
|
|
|
COMPARE(clz(r6, r7),
|
|
|
|
|
"e16f6f17 clz r6, r7");
|
|
|
|
|
|
2008-11-05 19:18:10 +00:00
|
|
|
VERIFY_RUN();
|
2008-08-22 13:33:59 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TEST(Type1) {
|
2012-01-13 13:09:52 +00:00
|
|
|
SET_UP();
|
2008-08-22 13:33:59 +00:00
|
|
|
|
|
|
|
|
COMPARE(and_(r0, r1, Operand(0x00000000)),
|
|
|
|
|
"e2010000 and r0, r1, #0");
|
|
|
|
|
COMPARE(and_(r1, r2, Operand(0x00000001), LeaveCC),
|
|
|
|
|
"e2021001 and r1, r2, #1");
|
|
|
|
|
COMPARE(and_(r2, r3, Operand(0x00000010), SetCC),
|
|
|
|
|
"e2132010 ands r2, r3, #16");
|
|
|
|
|
COMPARE(and_(r3, r4, Operand(0x00000100), LeaveCC, eq),
|
|
|
|
|
"02043c01 andeq r3, r4, #256");
|
|
|
|
|
COMPARE(and_(r4, r5, Operand(0x00001000), SetCC, ne),
|
|
|
|
|
"12154a01 andnes r4, r5, #4096");
|
|
|
|
|
|
|
|
|
|
COMPARE(eor(r4, r5, Operand(0x00001000)),
|
|
|
|
|
"e2254a01 eor r4, r5, #4096");
|
|
|
|
|
COMPARE(eor(r4, r4, Operand(0x00010000), LeaveCC),
|
|
|
|
|
"e2244801 eor r4, r4, #65536");
|
|
|
|
|
COMPARE(eor(r4, r3, Operand(0x00100000), SetCC),
|
|
|
|
|
"e2334601 eors r4, r3, #1048576");
|
|
|
|
|
COMPARE(eor(r4, r2, Operand(0x01000000), LeaveCC, cs),
|
|
|
|
|
"22224401 eorcs r4, r2, #16777216");
|
|
|
|
|
COMPARE(eor(r4, r1, Operand(0x10000000), SetCC, cc),
|
|
|
|
|
"32314201 eorccs r4, r1, #268435456");
|
|
|
|
|
|
2008-11-05 19:18:10 +00:00
|
|
|
VERIFY_RUN();
|
2008-08-22 13:33:59 +00:00
|
|
|
}
|
2010-05-27 13:46:18 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
TEST(Type3) {
|
2012-01-13 13:09:52 +00:00
|
|
|
SET_UP();
|
2010-05-27 13:46:18 +00:00
|
|
|
|
2011-03-31 16:17:37 +00:00
|
|
|
if (CpuFeatures::IsSupported(ARMv7)) {
|
2016-02-16 11:14:01 +00:00
|
|
|
CpuFeatureScope scope(&assm, ARMv7);
|
2010-05-27 13:46:18 +00:00
|
|
|
COMPARE(ubfx(r0, r1, 5, 10),
|
|
|
|
|
"e7e902d1 ubfx r0, r1, #5, #10");
|
|
|
|
|
COMPARE(ubfx(r1, r0, 5, 10),
|
|
|
|
|
"e7e912d0 ubfx r1, r0, #5, #10");
|
|
|
|
|
COMPARE(ubfx(r0, r1, 31, 1),
|
|
|
|
|
"e7e00fd1 ubfx r0, r1, #31, #1");
|
|
|
|
|
COMPARE(ubfx(r1, r0, 31, 1),
|
|
|
|
|
"e7e01fd0 ubfx r1, r0, #31, #1");
|
|
|
|
|
|
|
|
|
|
COMPARE(sbfx(r0, r1, 5, 10),
|
|
|
|
|
"e7a902d1 sbfx r0, r1, #5, #10");
|
|
|
|
|
COMPARE(sbfx(r1, r0, 5, 10),
|
|
|
|
|
"e7a912d0 sbfx r1, r0, #5, #10");
|
|
|
|
|
COMPARE(sbfx(r0, r1, 31, 1),
|
|
|
|
|
"e7a00fd1 sbfx r0, r1, #31, #1");
|
|
|
|
|
COMPARE(sbfx(r1, r0, 31, 1),
|
|
|
|
|
"e7a01fd0 sbfx r1, r0, #31, #1");
|
|
|
|
|
|
|
|
|
|
COMPARE(bfc(r0, 5, 10),
|
|
|
|
|
"e7ce029f bfc r0, #5, #10");
|
|
|
|
|
COMPARE(bfc(r1, 5, 10),
|
|
|
|
|
"e7ce129f bfc r1, #5, #10");
|
|
|
|
|
COMPARE(bfc(r0, 31, 1),
|
|
|
|
|
"e7df0f9f bfc r0, #31, #1");
|
|
|
|
|
COMPARE(bfc(r1, 31, 1),
|
|
|
|
|
"e7df1f9f bfc r1, #31, #1");
|
|
|
|
|
|
|
|
|
|
COMPARE(bfi(r0, r1, 5, 10),
|
|
|
|
|
"e7ce0291 bfi r0, r1, #5, #10");
|
|
|
|
|
COMPARE(bfi(r1, r0, 5, 10),
|
|
|
|
|
"e7ce1290 bfi r1, r0, #5, #10");
|
|
|
|
|
COMPARE(bfi(r0, r1, 31, 1),
|
|
|
|
|
"e7df0f91 bfi r0, r1, #31, #1");
|
|
|
|
|
COMPARE(bfi(r1, r0, 31, 1),
|
|
|
|
|
"e7df1f90 bfi r1, r0, #31, #1");
|
2010-07-21 07:42:51 +00:00
|
|
|
|
2013-07-10 15:32:39 +00:00
|
|
|
COMPARE(pkhbt(r3, r4, Operand(r5, LSL, 17)),
|
|
|
|
|
"e6843895 pkhbt r3, r4, r5, lsl #17");
|
|
|
|
|
COMPARE(pkhtb(r3, r4, Operand(r5, ASR, 17)),
|
|
|
|
|
"e68438d5 pkhtb r3, r4, r5, asr #17");
|
2014-11-10 05:48:38 +00:00
|
|
|
|
|
|
|
|
COMPARE(sxtb(r1, r7, 0, eq), "06af1077 sxtbeq r1, r7");
|
|
|
|
|
COMPARE(sxtb(r0, r0, 8, ne), "16af0470 sxtbne r0, r0, ror #8");
|
|
|
|
|
COMPARE(sxtb(r9, r10, 16), "e6af987a sxtb r9, r10, ror #16");
|
|
|
|
|
COMPARE(sxtb(r4, r3, 24), "e6af4c73 sxtb r4, r3, ror #24");
|
|
|
|
|
|
|
|
|
|
COMPARE(sxtab(r3, r4, r5), "e6a43075 sxtab r3, r4, r5");
|
|
|
|
|
|
|
|
|
|
COMPARE(sxth(r5, r0), "e6bf5070 sxth r5, r0");
|
|
|
|
|
COMPARE(sxth(r5, r9, 8), "e6bf5479 sxth r5, r9, ror #8");
|
|
|
|
|
COMPARE(sxth(r5, r9, 16, hi), "86bf5879 sxthhi r5, r9, ror #16");
|
|
|
|
|
COMPARE(sxth(r8, r9, 24, cc), "36bf8c79 sxthcc r8, r9, ror #24");
|
|
|
|
|
|
|
|
|
|
COMPARE(sxtah(r3, r4, r5, 16), "e6b43875 sxtah r3, r4, r5, ror #16");
|
|
|
|
|
|
|
|
|
|
COMPARE(uxtb(r9, r10), "e6ef907a uxtb r9, r10");
|
|
|
|
|
COMPARE(uxtb(r3, r4, 8), "e6ef3474 uxtb r3, r4, ror #8");
|
|
|
|
|
|
|
|
|
|
COMPARE(uxtab(r3, r4, r5, 8), "e6e43475 uxtab r3, r4, r5, ror #8");
|
|
|
|
|
|
|
|
|
|
COMPARE(uxtb16(r3, r4, 8), "e6cf3474 uxtb16 r3, r4, ror #8");
|
|
|
|
|
|
|
|
|
|
COMPARE(uxth(r9, r10), "e6ff907a uxth r9, r10");
|
|
|
|
|
COMPARE(uxth(r3, r4, 8), "e6ff3474 uxth r3, r4, ror #8");
|
|
|
|
|
|
|
|
|
|
COMPARE(uxtah(r3, r4, r5, 24), "e6f43c75 uxtah r3, r4, r5, ror #24");
|
2016-02-16 11:14:01 +00:00
|
|
|
|
|
|
|
|
COMPARE(rbit(r1, r2), "e6ff1f32 rbit r1, r2");
|
|
|
|
|
COMPARE(rbit(r10, ip), "e6ffaf3c rbit r10, ip");
|
2018-08-14 08:39:05 +00:00
|
|
|
|
|
|
|
|
COMPARE(rev(r1, r2), "e6bf1f32 rev r1, r2");
|
|
|
|
|
COMPARE(rev(r10, ip), "e6bfaf3c rev r10, ip");
|
2010-05-27 13:46:18 +00:00
|
|
|
}
|
|
|
|
|
|
2016-05-12 18:18:23 +00:00
|
|
|
COMPARE(usat(r0, 1, Operand(r1)),
|
|
|
|
|
"e6e10011 usat r0, #1, r1");
|
|
|
|
|
COMPARE(usat(r2, 7, Operand(lr)),
|
|
|
|
|
"e6e7201e usat r2, #7, lr");
|
|
|
|
|
COMPARE(usat(r3, 31, Operand(r4, LSL, 31)),
|
|
|
|
|
"e6ff3f94 usat r3, #31, r4, lsl #31");
|
|
|
|
|
COMPARE(usat(r8, 0, Operand(r5, ASR, 17)),
|
|
|
|
|
"e6e088d5 usat r8, #0, r5, asr #17");
|
|
|
|
|
|
2014-10-14 05:03:04 +00:00
|
|
|
COMPARE(smmla(r0, r1, r2, r3), "e7503211 smmla r0, r1, r2, r3");
|
|
|
|
|
COMPARE(smmla(r10, r9, r8, r7), "e75a7819 smmla r10, r9, r8, r7");
|
|
|
|
|
|
|
|
|
|
COMPARE(smmul(r0, r1, r2), "e750f211 smmul r0, r1, r2");
|
|
|
|
|
COMPARE(smmul(r8, r9, r10), "e758fa19 smmul r8, r9, r10");
|
|
|
|
|
|
2010-05-27 13:46:18 +00:00
|
|
|
VERIFY_RUN();
|
|
|
|
|
}
|
|
|
|
|
|
2010-06-29 09:40:36 +00:00
|
|
|
|
2016-03-10 11:38:17 +00:00
|
|
|
TEST(msr_mrs_disasm) {
|
|
|
|
|
SET_UP();
|
|
|
|
|
|
|
|
|
|
SRegisterFieldMask CPSR_all = CPSR_f | CPSR_s | CPSR_x | CPSR_c;
|
|
|
|
|
SRegisterFieldMask SPSR_all = SPSR_f | SPSR_s | SPSR_x | SPSR_c;
|
|
|
|
|
|
|
|
|
|
COMPARE(msr(CPSR_f, Operand(r0)), "e128f000 msr CPSR_f, r0");
|
|
|
|
|
COMPARE(msr(CPSR_s, Operand(r1)), "e124f001 msr CPSR_s, r1");
|
|
|
|
|
COMPARE(msr(CPSR_x, Operand(r2)), "e122f002 msr CPSR_x, r2");
|
|
|
|
|
COMPARE(msr(CPSR_c, Operand(r3)), "e121f003 msr CPSR_c, r3");
|
|
|
|
|
COMPARE(msr(CPSR_all, Operand(ip)), "e12ff00c msr CPSR_fsxc, ip");
|
|
|
|
|
COMPARE(msr(SPSR_f, Operand(r0)), "e168f000 msr SPSR_f, r0");
|
|
|
|
|
COMPARE(msr(SPSR_s, Operand(r1)), "e164f001 msr SPSR_s, r1");
|
|
|
|
|
COMPARE(msr(SPSR_x, Operand(r2)), "e162f002 msr SPSR_x, r2");
|
|
|
|
|
COMPARE(msr(SPSR_c, Operand(r3)), "e161f003 msr SPSR_c, r3");
|
|
|
|
|
COMPARE(msr(SPSR_all, Operand(ip)), "e16ff00c msr SPSR_fsxc, ip");
|
|
|
|
|
COMPARE(msr(CPSR_f, Operand(r0), eq), "0128f000 msreq CPSR_f, r0");
|
|
|
|
|
COMPARE(msr(CPSR_s, Operand(r1), ne), "1124f001 msrne CPSR_s, r1");
|
|
|
|
|
COMPARE(msr(CPSR_x, Operand(r2), cs), "2122f002 msrcs CPSR_x, r2");
|
|
|
|
|
COMPARE(msr(CPSR_c, Operand(r3), cc), "3121f003 msrcc CPSR_c, r3");
|
|
|
|
|
COMPARE(msr(CPSR_all, Operand(ip), mi), "412ff00c msrmi CPSR_fsxc, ip");
|
|
|
|
|
COMPARE(msr(SPSR_f, Operand(r0), pl), "5168f000 msrpl SPSR_f, r0");
|
|
|
|
|
COMPARE(msr(SPSR_s, Operand(r1), vs), "6164f001 msrvs SPSR_s, r1");
|
|
|
|
|
COMPARE(msr(SPSR_x, Operand(r2), vc), "7162f002 msrvc SPSR_x, r2");
|
|
|
|
|
COMPARE(msr(SPSR_c, Operand(r3), hi), "8161f003 msrhi SPSR_c, r3");
|
|
|
|
|
COMPARE(msr(SPSR_all, Operand(ip), ls), "916ff00c msrls SPSR_fsxc, ip");
|
|
|
|
|
|
|
|
|
|
// Other combinations of mask bits.
|
|
|
|
|
COMPARE(msr(CPSR_s | CPSR_x, Operand(r4)),
|
|
|
|
|
"e126f004 msr CPSR_sx, r4");
|
|
|
|
|
COMPARE(msr(SPSR_s | SPSR_x | SPSR_c, Operand(r5)),
|
|
|
|
|
"e167f005 msr SPSR_sxc, r5");
|
|
|
|
|
COMPARE(msr(SPSR_s | SPSR_c, Operand(r6)),
|
|
|
|
|
"e165f006 msr SPSR_sc, r6");
|
|
|
|
|
COMPARE(msr(SPSR_f | SPSR_c, Operand(r7)),
|
|
|
|
|
"e169f007 msr SPSR_fc, r7");
|
|
|
|
|
// MSR with no mask is UNPREDICTABLE, and checked by the assembler, but check
|
|
|
|
|
// that the disassembler does something sensible.
|
2017-12-02 00:30:37 +00:00
|
|
|
COMPARE(dd(0xE120F008), "e120f008 msr CPSR_(none), r8");
|
2016-03-10 11:38:17 +00:00
|
|
|
|
|
|
|
|
COMPARE(mrs(r0, CPSR), "e10f0000 mrs r0, CPSR");
|
|
|
|
|
COMPARE(mrs(r1, SPSR), "e14f1000 mrs r1, SPSR");
|
|
|
|
|
COMPARE(mrs(r2, CPSR, ge), "a10f2000 mrsge r2, CPSR");
|
|
|
|
|
COMPARE(mrs(r3, SPSR, lt), "b14f3000 mrslt r3, SPSR");
|
|
|
|
|
|
|
|
|
|
VERIFY_RUN();
|
|
|
|
|
}
|
|
|
|
|
|
2010-06-29 09:40:36 +00:00
|
|
|
|
|
|
|
|
TEST(Vfp) {
|
2012-01-13 13:09:52 +00:00
|
|
|
SET_UP();
|
2010-06-29 09:40:36 +00:00
|
|
|
|
2016-09-23 15:29:11 +00:00
|
|
|
if (CpuFeatures::IsSupported(VFPv3)) {
|
|
|
|
|
CpuFeatureScope scope(&assm, VFPv3);
|
2013-01-23 16:29:48 +00:00
|
|
|
COMPARE(vmov(d0, r2, r3),
|
|
|
|
|
"ec432b10 vmov d0, r2, r3");
|
|
|
|
|
COMPARE(vmov(r2, r3, d0),
|
|
|
|
|
"ec532b10 vmov r2, r3, d0");
|
2017-07-13 10:07:46 +00:00
|
|
|
COMPARE(vmov(r4, ip, d1),
|
|
|
|
|
"ec5c4b11 vmov r4, ip, d1");
|
2010-06-30 12:22:15 +00:00
|
|
|
COMPARE(vmov(d0, d1),
|
|
|
|
|
"eeb00b41 vmov.f64 d0, d1");
|
|
|
|
|
COMPARE(vmov(d3, d3, eq),
|
2013-02-27 11:52:45 +00:00
|
|
|
"0eb03b43 vmoveq.f64 d3, d3");
|
2010-06-30 12:22:15 +00:00
|
|
|
|
2010-08-26 08:53:00 +00:00
|
|
|
COMPARE(vmov(s0, s31),
|
|
|
|
|
"eeb00a6f vmov.f32 s0, s31");
|
|
|
|
|
COMPARE(vmov(s31, s0),
|
|
|
|
|
"eef0fa40 vmov.f32 s31, s0");
|
|
|
|
|
COMPARE(vmov(r0, s0),
|
|
|
|
|
"ee100a10 vmov r0, s0");
|
|
|
|
|
COMPARE(vmov(r10, s31),
|
|
|
|
|
"ee1faa90 vmov r10, s31");
|
|
|
|
|
COMPARE(vmov(s0, r0),
|
|
|
|
|
"ee000a10 vmov s0, r0");
|
|
|
|
|
COMPARE(vmov(s31, r10),
|
|
|
|
|
"ee0faa90 vmov s31, r10");
|
|
|
|
|
|
2011-01-31 10:16:28 +00:00
|
|
|
COMPARE(vabs(d0, d1),
|
2011-05-12 14:44:49 +00:00
|
|
|
"eeb00bc1 vabs.f64 d0, d1");
|
2011-01-31 10:16:28 +00:00
|
|
|
COMPARE(vabs(d3, d4, mi),
|
2013-02-27 11:52:45 +00:00
|
|
|
"4eb03bc4 vabsmi.f64 d3, d4");
|
2011-01-31 10:16:28 +00:00
|
|
|
|
2015-03-30 07:33:46 +00:00
|
|
|
COMPARE(vabs(s0, s1),
|
|
|
|
|
"eeb00ae0 vabs.f32 s0, s1");
|
|
|
|
|
COMPARE(vabs(s3, s4, mi),
|
|
|
|
|
"4ef01ac2 vabsmi.f32 s3, s4");
|
|
|
|
|
|
2011-03-15 11:19:13 +00:00
|
|
|
COMPARE(vneg(d0, d1),
|
2011-05-12 14:44:49 +00:00
|
|
|
"eeb10b41 vneg.f64 d0, d1");
|
2011-03-15 11:19:13 +00:00
|
|
|
COMPARE(vneg(d3, d4, mi),
|
2013-02-27 11:52:45 +00:00
|
|
|
"4eb13b44 vnegmi.f64 d3, d4");
|
2011-03-15 11:19:13 +00:00
|
|
|
|
2015-03-30 07:33:46 +00:00
|
|
|
COMPARE(vneg(s0, s1),
|
|
|
|
|
"eeb10a60 vneg.f32 s0, s1");
|
|
|
|
|
COMPARE(vneg(s3, s4, mi),
|
|
|
|
|
"4ef11a42 vnegmi.f32 s3, s4");
|
|
|
|
|
|
2010-06-30 08:46:19 +00:00
|
|
|
COMPARE(vadd(d0, d1, d2),
|
|
|
|
|
"ee310b02 vadd.f64 d0, d1, d2");
|
|
|
|
|
COMPARE(vadd(d3, d4, d5, mi),
|
2013-02-27 11:52:45 +00:00
|
|
|
"4e343b05 vaddmi.f64 d3, d4, d5");
|
2010-06-30 08:46:19 +00:00
|
|
|
|
2015-03-30 07:33:46 +00:00
|
|
|
COMPARE(vadd(s0, s1, s2),
|
|
|
|
|
"ee300a81 vadd.f32 s0, s1, s2");
|
|
|
|
|
COMPARE(vadd(s3, s4, s5, mi),
|
|
|
|
|
"4e721a22 vaddmi.f32 s3, s4, s5");
|
|
|
|
|
|
2010-06-30 08:46:19 +00:00
|
|
|
COMPARE(vsub(d0, d1, d2),
|
|
|
|
|
"ee310b42 vsub.f64 d0, d1, d2");
|
|
|
|
|
COMPARE(vsub(d3, d4, d5, ne),
|
2013-02-27 11:52:45 +00:00
|
|
|
"1e343b45 vsubne.f64 d3, d4, d5");
|
2010-06-30 08:46:19 +00:00
|
|
|
|
2015-03-30 07:33:46 +00:00
|
|
|
COMPARE(vsub(s0, s1, s2),
|
|
|
|
|
"ee300ac1 vsub.f32 s0, s1, s2");
|
|
|
|
|
COMPARE(vsub(s3, s4, s5, ne),
|
|
|
|
|
"1e721a62 vsubne.f32 s3, s4, s5");
|
|
|
|
|
|
2010-06-30 08:46:19 +00:00
|
|
|
COMPARE(vmul(d2, d1, d0),
|
|
|
|
|
"ee212b00 vmul.f64 d2, d1, d0");
|
|
|
|
|
COMPARE(vmul(d6, d4, d5, cc),
|
2013-02-27 11:52:45 +00:00
|
|
|
"3e246b05 vmulcc.f64 d6, d4, d5");
|
2010-06-30 08:46:19 +00:00
|
|
|
|
2015-03-30 07:33:46 +00:00
|
|
|
COMPARE(vmul(s2, s1, s0),
|
|
|
|
|
"ee201a80 vmul.f32 s2, s1, s0");
|
|
|
|
|
COMPARE(vmul(s6, s4, s5, cc),
|
|
|
|
|
"3e223a22 vmulcc.f32 s6, s4, s5");
|
|
|
|
|
|
2010-06-30 08:46:19 +00:00
|
|
|
COMPARE(vdiv(d2, d2, d2),
|
|
|
|
|
"ee822b02 vdiv.f64 d2, d2, d2");
|
|
|
|
|
COMPARE(vdiv(d6, d7, d7, hi),
|
2013-02-27 11:52:45 +00:00
|
|
|
"8e876b07 vdivhi.f64 d6, d7, d7");
|
2010-06-30 08:46:19 +00:00
|
|
|
|
2015-03-30 07:33:46 +00:00
|
|
|
COMPARE(vdiv(s2, s2, s2),
|
|
|
|
|
"ee811a01 vdiv.f32 s2, s2, s2");
|
|
|
|
|
COMPARE(vdiv(s6, s7, s7, hi),
|
|
|
|
|
"8e833aa3 vdivhi.f32 s6, s7, s7");
|
|
|
|
|
|
2013-01-23 16:29:48 +00:00
|
|
|
COMPARE(vcmp(d0, d1),
|
|
|
|
|
"eeb40b41 vcmp.f64 d0, d1");
|
|
|
|
|
COMPARE(vcmp(d0, 0.0),
|
|
|
|
|
"eeb50b40 vcmp.f64 d0, #0.0");
|
|
|
|
|
|
2015-03-30 07:33:46 +00:00
|
|
|
COMPARE(vcmp(s0, s1),
|
|
|
|
|
"eeb40a60 vcmp.f32 s0, s1");
|
|
|
|
|
COMPARE(vcmp(s0, 0.0f),
|
|
|
|
|
"eeb50a40 vcmp.f32 s0, #0.0");
|
|
|
|
|
|
2010-06-29 09:40:36 +00:00
|
|
|
COMPARE(vsqrt(d0, d0),
|
|
|
|
|
"eeb10bc0 vsqrt.f64 d0, d0");
|
2010-06-30 08:46:19 +00:00
|
|
|
COMPARE(vsqrt(d2, d3, ne),
|
2013-02-27 11:52:45 +00:00
|
|
|
"1eb12bc3 vsqrtne.f64 d2, d3");
|
2010-07-08 12:38:02 +00:00
|
|
|
|
2015-03-30 07:33:46 +00:00
|
|
|
COMPARE(vsqrt(s0, s0),
|
|
|
|
|
"eeb10ac0 vsqrt.f32 s0, s0");
|
|
|
|
|
COMPARE(vsqrt(s2, s3, ne),
|
|
|
|
|
"1eb11ae1 vsqrtne.f32 s2, s3");
|
|
|
|
|
|
2017-07-05 13:48:12 +00:00
|
|
|
COMPARE(vmov(d0, Double(1.0)),
|
2010-07-08 12:38:02 +00:00
|
|
|
"eeb70b00 vmov.f64 d0, #1");
|
2017-07-05 13:48:12 +00:00
|
|
|
COMPARE(vmov(d2, Double(-13.0)),
|
2010-07-08 12:38:02 +00:00
|
|
|
"eeba2b0a vmov.f64 d2, #-13");
|
2010-08-26 08:53:00 +00:00
|
|
|
|
2017-07-07 11:32:01 +00:00
|
|
|
COMPARE(vmov(s1, Float32(-1.0f)),
|
2016-03-14 15:30:13 +00:00
|
|
|
"eeff0a00 vmov.f32 s1, #-1");
|
2017-07-07 11:32:01 +00:00
|
|
|
COMPARE(vmov(s3, Float32(13.0f)),
|
2016-03-14 15:30:13 +00:00
|
|
|
"eef21a0a vmov.f32 s3, #13");
|
|
|
|
|
|
2018-07-24 16:56:27 +00:00
|
|
|
COMPARE(vmov(NeonS32, d0, 0, r0),
|
2013-01-23 16:29:48 +00:00
|
|
|
"ee000b10 vmov.32 d0[0], r0");
|
2018-07-24 16:56:27 +00:00
|
|
|
COMPARE(vmov(NeonS32, d0, 1, r0),
|
2013-01-23 16:29:48 +00:00
|
|
|
"ee200b10 vmov.32 d0[1], r0");
|
|
|
|
|
|
2018-07-24 16:56:27 +00:00
|
|
|
COMPARE(vmov(NeonS32, r2, d15, 0),
|
2013-07-25 15:04:38 +00:00
|
|
|
"ee1f2b10 vmov.32 r2, d15[0]");
|
2018-07-24 16:56:27 +00:00
|
|
|
COMPARE(vmov(NeonS32, r3, d14, 1),
|
2013-07-25 15:04:38 +00:00
|
|
|
"ee3e3b10 vmov.32 r3, d14[1]");
|
|
|
|
|
|
2010-08-26 08:53:00 +00:00
|
|
|
COMPARE(vldr(s0, r0, 0),
|
|
|
|
|
"ed900a00 vldr s0, [r0 + 4*0]");
|
|
|
|
|
COMPARE(vldr(s1, r1, 4),
|
|
|
|
|
"edd10a01 vldr s1, [r1 + 4*1]");
|
|
|
|
|
COMPARE(vldr(s15, r4, 16),
|
|
|
|
|
"edd47a04 vldr s15, [r4 + 4*4]");
|
|
|
|
|
COMPARE(vldr(s16, r5, 20),
|
|
|
|
|
"ed958a05 vldr s16, [r5 + 4*5]");
|
|
|
|
|
COMPARE(vldr(s31, r10, 1020),
|
|
|
|
|
"eddafaff vldr s31, [r10 + 4*255]");
|
2017-07-13 10:07:46 +00:00
|
|
|
COMPARE(vldr(s31, ip, 1020),
|
|
|
|
|
"eddcfaff vldr s31, [ip + 4*255]");
|
2010-08-26 08:53:00 +00:00
|
|
|
|
|
|
|
|
COMPARE(vstr(s0, r0, 0),
|
|
|
|
|
"ed800a00 vstr s0, [r0 + 4*0]");
|
|
|
|
|
COMPARE(vstr(s1, r1, 4),
|
|
|
|
|
"edc10a01 vstr s1, [r1 + 4*1]");
|
|
|
|
|
COMPARE(vstr(s15, r8, 8),
|
|
|
|
|
"edc87a02 vstr s15, [r8 + 4*2]");
|
|
|
|
|
COMPARE(vstr(s16, r9, 12),
|
|
|
|
|
"ed898a03 vstr s16, [r9 + 4*3]");
|
|
|
|
|
COMPARE(vstr(s31, r10, 1020),
|
|
|
|
|
"edcafaff vstr s31, [r10 + 4*255]");
|
|
|
|
|
|
|
|
|
|
COMPARE(vldr(d0, r0, 0),
|
|
|
|
|
"ed900b00 vldr d0, [r0 + 4*0]");
|
|
|
|
|
COMPARE(vldr(d1, r1, 4),
|
|
|
|
|
"ed911b01 vldr d1, [r1 + 4*1]");
|
|
|
|
|
COMPARE(vldr(d15, r10, 1020),
|
|
|
|
|
"ed9afbff vldr d15, [r10 + 4*255]");
|
|
|
|
|
COMPARE(vstr(d0, r0, 0),
|
|
|
|
|
"ed800b00 vstr d0, [r0 + 4*0]");
|
|
|
|
|
COMPARE(vstr(d1, r1, 4),
|
|
|
|
|
"ed811b01 vstr d1, [r1 + 4*1]");
|
|
|
|
|
COMPARE(vstr(d15, r10, 1020),
|
|
|
|
|
"ed8afbff vstr d15, [r10 + 4*255]");
|
2010-11-15 10:21:57 +00:00
|
|
|
|
|
|
|
|
COMPARE(vmsr(r5),
|
|
|
|
|
"eee15a10 vmsr FPSCR, r5");
|
|
|
|
|
COMPARE(vmsr(r10, pl),
|
|
|
|
|
"5ee1aa10 vmsrpl FPSCR, r10");
|
|
|
|
|
COMPARE(vmsr(pc),
|
|
|
|
|
"eee1fa10 vmsr FPSCR, APSR");
|
|
|
|
|
COMPARE(vmrs(r5),
|
|
|
|
|
"eef15a10 vmrs r5, FPSCR");
|
|
|
|
|
COMPARE(vmrs(r10, ge),
|
|
|
|
|
"aef1aa10 vmrsge r10, FPSCR");
|
|
|
|
|
COMPARE(vmrs(pc),
|
|
|
|
|
"eef1fa10 vmrs APSR, FPSCR");
|
2011-04-06 09:06:23 +00:00
|
|
|
|
|
|
|
|
COMPARE(vstm(ia, r0, d1, d3),
|
|
|
|
|
"ec801b06 vstmia r0, {d1-d3}");
|
|
|
|
|
COMPARE(vldm(ia, r1, d2, d5),
|
|
|
|
|
"ec912b08 vldmia r1, {d2-d5}");
|
|
|
|
|
COMPARE(vstm(ia, r2, d0, d15),
|
|
|
|
|
"ec820b20 vstmia r2, {d0-d15}");
|
|
|
|
|
COMPARE(vldm(ia, r3, d0, d15),
|
|
|
|
|
"ec930b20 vldmia r3, {d0-d15}");
|
|
|
|
|
COMPARE(vstm(ia, r4, s1, s3),
|
|
|
|
|
"ecc40a03 vstmia r4, {s1-s3}");
|
|
|
|
|
COMPARE(vldm(ia, r5, s2, s5),
|
|
|
|
|
"ec951a04 vldmia r5, {s2-s5}");
|
|
|
|
|
COMPARE(vstm(ia, r6, s0, s31),
|
|
|
|
|
"ec860a20 vstmia r6, {s0-s31}");
|
|
|
|
|
COMPARE(vldm(ia, r7, s0, s31),
|
|
|
|
|
"ec970a20 vldmia r7, {s0-s31}");
|
2012-11-14 11:01:18 +00:00
|
|
|
|
|
|
|
|
COMPARE(vmla(d2, d1, d0),
|
|
|
|
|
"ee012b00 vmla.f64 d2, d1, d0");
|
|
|
|
|
COMPARE(vmla(d6, d4, d5, cc),
|
2013-02-27 11:52:45 +00:00
|
|
|
"3e046b05 vmlacc.f64 d6, d4, d5");
|
2013-01-23 16:29:48 +00:00
|
|
|
|
2015-03-30 07:33:46 +00:00
|
|
|
COMPARE(vmla(s2, s1, s0),
|
|
|
|
|
"ee001a80 vmla.f32 s2, s1, s0");
|
|
|
|
|
COMPARE(vmla(s6, s4, s5, cc),
|
|
|
|
|
"3e023a22 vmlacc.f32 s6, s4, s5");
|
|
|
|
|
|
2013-02-27 10:24:40 +00:00
|
|
|
COMPARE(vmls(d2, d1, d0),
|
|
|
|
|
"ee012b40 vmls.f64 d2, d1, d0");
|
|
|
|
|
COMPARE(vmls(d6, d4, d5, cc),
|
2013-02-27 11:52:45 +00:00
|
|
|
"3e046b45 vmlscc.f64 d6, d4, d5");
|
2013-02-27 10:24:40 +00:00
|
|
|
|
2015-03-30 07:33:46 +00:00
|
|
|
COMPARE(vmls(s2, s1, s0),
|
|
|
|
|
"ee001ac0 vmls.f32 s2, s1, s0");
|
|
|
|
|
COMPARE(vmls(s6, s4, s5, cc),
|
|
|
|
|
"3e023a62 vmlscc.f32 s6, s4, s5");
|
|
|
|
|
|
2016-02-08 11:45:17 +00:00
|
|
|
COMPARE(vcvt_f32_f64(s31, d15),
|
|
|
|
|
"eef7fbcf vcvt.f32.f64 s31, d15");
|
|
|
|
|
COMPARE(vcvt_f32_s32(s30, s29),
|
|
|
|
|
"eeb8faee vcvt.f32.s32 s30, s29");
|
|
|
|
|
COMPARE(vcvt_f64_f32(d14, s28),
|
|
|
|
|
"eeb7eace vcvt.f64.f32 d14, s28");
|
|
|
|
|
COMPARE(vcvt_f64_s32(d13, s27),
|
|
|
|
|
"eeb8dbed vcvt.f64.s32 d13, s27");
|
|
|
|
|
COMPARE(vcvt_f64_u32(d12, s26),
|
|
|
|
|
"eeb8cb4d vcvt.f64.u32 d12, s26");
|
|
|
|
|
COMPARE(vcvt_s32_f32(s25, s24),
|
|
|
|
|
"eefdcacc vcvt.s32.f32 s25, s24");
|
|
|
|
|
COMPARE(vcvt_s32_f64(s23, d11),
|
|
|
|
|
"eefdbbcb vcvt.s32.f64 s23, d11");
|
|
|
|
|
COMPARE(vcvt_u32_f32(s22, s21),
|
|
|
|
|
"eebcbaea vcvt.u32.f32 s22, s21");
|
|
|
|
|
COMPARE(vcvt_u32_f64(s20, d10),
|
|
|
|
|
"eebcabca vcvt.u32.f64 s20, d10");
|
|
|
|
|
|
|
|
|
|
COMPARE(vcvt_f64_s32(d9, 2),
|
|
|
|
|
"eeba9bcf vcvt.f64.s32 d9, d9, #2");
|
2013-01-23 16:29:48 +00:00
|
|
|
|
|
|
|
|
if (CpuFeatures::IsSupported(VFP32DREGS)) {
|
2016-09-23 15:29:11 +00:00
|
|
|
CpuFeatureScope scope(&assm, VFP32DREGS);
|
2013-01-23 16:29:48 +00:00
|
|
|
COMPARE(vmov(d3, d27),
|
|
|
|
|
"eeb03b6b vmov.f64 d3, d27");
|
|
|
|
|
COMPARE(vmov(d18, d7),
|
|
|
|
|
"eef02b47 vmov.f64 d18, d7");
|
|
|
|
|
COMPARE(vmov(d18, r2, r3),
|
|
|
|
|
"ec432b32 vmov d18, r2, r3");
|
|
|
|
|
COMPARE(vmov(r2, r3, d18),
|
|
|
|
|
"ec532b32 vmov r2, r3, d18");
|
|
|
|
|
COMPARE(vmov(d20, d31),
|
|
|
|
|
"eef04b6f vmov.f64 d20, d31");
|
|
|
|
|
|
|
|
|
|
COMPARE(vabs(d16, d31),
|
|
|
|
|
"eef00bef vabs.f64 d16, d31");
|
|
|
|
|
|
|
|
|
|
COMPARE(vneg(d16, d31),
|
|
|
|
|
"eef10b6f vneg.f64 d16, d31");
|
|
|
|
|
|
|
|
|
|
COMPARE(vadd(d16, d17, d18),
|
|
|
|
|
"ee710ba2 vadd.f64 d16, d17, d18");
|
|
|
|
|
|
|
|
|
|
COMPARE(vsub(d16, d17, d18),
|
|
|
|
|
"ee710be2 vsub.f64 d16, d17, d18");
|
|
|
|
|
|
|
|
|
|
COMPARE(vmul(d16, d17, d18),
|
|
|
|
|
"ee610ba2 vmul.f64 d16, d17, d18");
|
|
|
|
|
|
|
|
|
|
COMPARE(vdiv(d16, d17, d18),
|
|
|
|
|
"eec10ba2 vdiv.f64 d16, d17, d18");
|
|
|
|
|
|
|
|
|
|
COMPARE(vcmp(d16, d17),
|
|
|
|
|
"eef40b61 vcmp.f64 d16, d17");
|
|
|
|
|
COMPARE(vcmp(d16, 0.0),
|
|
|
|
|
"eef50b40 vcmp.f64 d16, #0.0");
|
|
|
|
|
|
|
|
|
|
COMPARE(vsqrt(d16, d17),
|
|
|
|
|
"eef10be1 vsqrt.f64 d16, d17");
|
|
|
|
|
|
2017-07-05 13:48:12 +00:00
|
|
|
COMPARE(vmov(d30, Double(16.0)),
|
2013-01-23 16:29:48 +00:00
|
|
|
"eef3eb00 vmov.f64 d30, #16");
|
|
|
|
|
|
2018-07-24 16:56:27 +00:00
|
|
|
COMPARE(vmov(NeonS32, d31, 0, r7),
|
2013-01-23 16:29:48 +00:00
|
|
|
"ee0f7b90 vmov.32 d31[0], r7");
|
2018-07-24 16:56:27 +00:00
|
|
|
COMPARE(vmov(NeonS32, d31, 1, r7),
|
2013-01-23 16:29:48 +00:00
|
|
|
"ee2f7b90 vmov.32 d31[1], r7");
|
|
|
|
|
|
|
|
|
|
COMPARE(vldr(d25, r0, 0),
|
|
|
|
|
"edd09b00 vldr d25, [r0 + 4*0]");
|
|
|
|
|
COMPARE(vldr(d26, r1, 4),
|
|
|
|
|
"edd1ab01 vldr d26, [r1 + 4*1]");
|
|
|
|
|
COMPARE(vldr(d31, r10, 1020),
|
|
|
|
|
"eddafbff vldr d31, [r10 + 4*255]");
|
|
|
|
|
|
|
|
|
|
COMPARE(vstr(d16, r0, 0),
|
|
|
|
|
"edc00b00 vstr d16, [r0 + 4*0]");
|
|
|
|
|
COMPARE(vstr(d17, r1, 4),
|
|
|
|
|
"edc11b01 vstr d17, [r1 + 4*1]");
|
|
|
|
|
COMPARE(vstr(d31, r10, 1020),
|
|
|
|
|
"edcafbff vstr d31, [r10 + 4*255]");
|
|
|
|
|
|
|
|
|
|
COMPARE(vstm(ia, r0, d16, d31),
|
|
|
|
|
"ecc00b20 vstmia r0, {d16-d31}");
|
|
|
|
|
COMPARE(vldm(ia, r3, d16, d31),
|
|
|
|
|
"ecd30b20 vldmia r3, {d16-d31}");
|
|
|
|
|
COMPARE(vstm(ia, r0, d23, d27),
|
|
|
|
|
"ecc07b0a vstmia r0, {d23-d27}");
|
|
|
|
|
COMPARE(vldm(ia, r3, d23, d27),
|
|
|
|
|
"ecd37b0a vldmia r3, {d23-d27}");
|
|
|
|
|
|
|
|
|
|
COMPARE(vmla(d16, d17, d18),
|
|
|
|
|
"ee410ba2 vmla.f64 d16, d17, d18");
|
|
|
|
|
|
2016-02-08 11:45:17 +00:00
|
|
|
COMPARE(vcvt_f32_f64(s0, d31),
|
|
|
|
|
"eeb70bef vcvt.f32.f64 s0, d31");
|
|
|
|
|
COMPARE(vcvt_f32_s32(s1, s2),
|
|
|
|
|
"eef80ac1 vcvt.f32.s32 s1, s2");
|
|
|
|
|
COMPARE(vcvt_f64_f32(d30, s3),
|
|
|
|
|
"eef7eae1 vcvt.f64.f32 d30, s3");
|
|
|
|
|
COMPARE(vcvt_f64_s32(d29, s4),
|
|
|
|
|
"eef8dbc2 vcvt.f64.s32 d29, s4");
|
|
|
|
|
COMPARE(vcvt_f64_u32(d28, s5),
|
|
|
|
|
"eef8cb62 vcvt.f64.u32 d28, s5");
|
|
|
|
|
COMPARE(vcvt_s32_f32(s6, s7),
|
|
|
|
|
"eebd3ae3 vcvt.s32.f32 s6, s7");
|
|
|
|
|
COMPARE(vcvt_s32_f64(s8, d27),
|
|
|
|
|
"eebd4beb vcvt.s32.f64 s8, d27");
|
|
|
|
|
COMPARE(vcvt_u32_f32(s9, s10),
|
|
|
|
|
"eefc4ac5 vcvt.u32.f32 s9, s10");
|
|
|
|
|
COMPARE(vcvt_u32_f64(s11, d26),
|
|
|
|
|
"eefc5bea vcvt.u32.f64 s11, d26");
|
|
|
|
|
|
|
|
|
|
COMPARE(vcvt_f64_s32(d25, 2),
|
|
|
|
|
"eefa9bcf vcvt.f64.s32 d25, d25, #2");
|
2013-01-23 16:29:48 +00:00
|
|
|
}
|
2010-06-29 09:40:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
VERIFY_RUN();
|
|
|
|
|
}
|
2011-05-12 14:44:49 +00:00
|
|
|
|
|
|
|
|
|
2014-10-30 11:00:47 +00:00
|
|
|
TEST(ARMv8_vrintX_disasm) {
|
|
|
|
|
SET_UP();
|
|
|
|
|
|
|
|
|
|
if (CpuFeatures::IsSupported(ARMv8)) {
|
2016-09-23 15:29:11 +00:00
|
|
|
CpuFeatureScope scope(&assm, ARMv8);
|
2014-10-30 11:00:47 +00:00
|
|
|
COMPARE(vrinta(d0, d0), "feb80b40 vrinta.f64.f64 d0, d0");
|
|
|
|
|
COMPARE(vrinta(d2, d3), "feb82b43 vrinta.f64.f64 d2, d3");
|
|
|
|
|
|
|
|
|
|
COMPARE(vrintp(d0, d0), "feba0b40 vrintp.f64.f64 d0, d0");
|
|
|
|
|
COMPARE(vrintp(d2, d3), "feba2b43 vrintp.f64.f64 d2, d3");
|
|
|
|
|
|
|
|
|
|
COMPARE(vrintn(d0, d0), "feb90b40 vrintn.f64.f64 d0, d0");
|
|
|
|
|
COMPARE(vrintn(d2, d3), "feb92b43 vrintn.f64.f64 d2, d3");
|
|
|
|
|
|
|
|
|
|
COMPARE(vrintm(d0, d0), "febb0b40 vrintm.f64.f64 d0, d0");
|
|
|
|
|
COMPARE(vrintm(d2, d3), "febb2b43 vrintm.f64.f64 d2, d3");
|
|
|
|
|
|
|
|
|
|
COMPARE(vrintz(d0, d0), "eeb60bc0 vrintz.f64.f64 d0, d0");
|
|
|
|
|
COMPARE(vrintz(d2, d3, ne), "1eb62bc3 vrintzne.f64.f64 d2, d3");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
VERIFY_RUN();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2016-09-06 08:46:17 +00:00
|
|
|
TEST(ARMv8_vminmax_disasm) {
|
|
|
|
|
SET_UP();
|
|
|
|
|
|
|
|
|
|
if (CpuFeatures::IsSupported(ARMv8)) {
|
2016-09-23 15:29:11 +00:00
|
|
|
CpuFeatureScope scope(&assm, ARMv8);
|
2016-09-06 08:46:17 +00:00
|
|
|
COMPARE(vmaxnm(d0, d1, d2), "fe810b02 vmaxnm.f64 d0, d1, d2");
|
|
|
|
|
COMPARE(vminnm(d3, d4, d5), "fe843b45 vminnm.f64 d3, d4, d5");
|
|
|
|
|
COMPARE(vmaxnm(s6, s7, s8), "fe833a84 vmaxnm.f32 s6, s7, s8");
|
|
|
|
|
COMPARE(vminnm(s9, s10, s11), "fec54a65 vminnm.f32 s9, s10, s11");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
VERIFY_RUN();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2016-04-06 10:17:14 +00:00
|
|
|
TEST(ARMv8_vselX_disasm) {
|
|
|
|
|
SET_UP();
|
|
|
|
|
|
|
|
|
|
if (CpuFeatures::IsSupported(ARMv8)) {
|
2016-09-23 15:29:11 +00:00
|
|
|
CpuFeatureScope scope(&assm, ARMv8);
|
2016-04-06 10:17:14 +00:00
|
|
|
// Native instructions.
|
|
|
|
|
COMPARE(vsel(eq, d0, d1, d2),
|
|
|
|
|
"fe010b02 vseleq.f64 d0, d1, d2");
|
|
|
|
|
COMPARE(vsel(eq, s0, s1, s2),
|
|
|
|
|
"fe000a81 vseleq.f32 s0, s1, s2");
|
|
|
|
|
COMPARE(vsel(ge, d0, d1, d2),
|
|
|
|
|
"fe210b02 vselge.f64 d0, d1, d2");
|
|
|
|
|
COMPARE(vsel(ge, s0, s1, s2),
|
|
|
|
|
"fe200a81 vselge.f32 s0, s1, s2");
|
|
|
|
|
COMPARE(vsel(gt, d0, d1, d2),
|
|
|
|
|
"fe310b02 vselgt.f64 d0, d1, d2");
|
|
|
|
|
COMPARE(vsel(gt, s0, s1, s2),
|
|
|
|
|
"fe300a81 vselgt.f32 s0, s1, s2");
|
|
|
|
|
COMPARE(vsel(vs, d0, d1, d2),
|
|
|
|
|
"fe110b02 vselvs.f64 d0, d1, d2");
|
|
|
|
|
COMPARE(vsel(vs, s0, s1, s2),
|
|
|
|
|
"fe100a81 vselvs.f32 s0, s1, s2");
|
|
|
|
|
|
|
|
|
|
// Inverted conditions (and swapped inputs).
|
|
|
|
|
COMPARE(vsel(ne, d0, d1, d2),
|
|
|
|
|
"fe020b01 vseleq.f64 d0, d2, d1");
|
|
|
|
|
COMPARE(vsel(ne, s0, s1, s2),
|
|
|
|
|
"fe010a20 vseleq.f32 s0, s2, s1");
|
|
|
|
|
COMPARE(vsel(lt, d0, d1, d2),
|
|
|
|
|
"fe220b01 vselge.f64 d0, d2, d1");
|
|
|
|
|
COMPARE(vsel(lt, s0, s1, s2),
|
|
|
|
|
"fe210a20 vselge.f32 s0, s2, s1");
|
|
|
|
|
COMPARE(vsel(le, d0, d1, d2),
|
|
|
|
|
"fe320b01 vselgt.f64 d0, d2, d1");
|
|
|
|
|
COMPARE(vsel(le, s0, s1, s2),
|
|
|
|
|
"fe310a20 vselgt.f32 s0, s2, s1");
|
|
|
|
|
COMPARE(vsel(vc, d0, d1, d2),
|
|
|
|
|
"fe120b01 vselvs.f64 d0, d2, d1");
|
|
|
|
|
COMPARE(vsel(vc, s0, s1, s2),
|
|
|
|
|
"fe110a20 vselvs.f32 s0, s2, s1");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
VERIFY_RUN();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2013-07-10 15:32:39 +00:00
|
|
|
TEST(Neon) {
|
|
|
|
|
SET_UP();
|
|
|
|
|
|
|
|
|
|
if (CpuFeatures::IsSupported(NEON)) {
|
|
|
|
|
CpuFeatureScope scope(&assm, NEON);
|
|
|
|
|
COMPARE(vld1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(r1)),
|
|
|
|
|
"f421420f vld1.8 {d4, d5, d6, d7}, [r1]");
|
|
|
|
|
COMPARE(vst1(Neon16, NeonListOperand(d17, 4), NeonMemOperand(r9)),
|
|
|
|
|
"f449124f vst1.16 {d17, d18, d19, d20}, [r9]");
|
2017-03-27 18:23:42 +00:00
|
|
|
COMPARE(vmovl(NeonU8, q3, d1), "f3886a11 vmovl.u8 q3, d1");
|
|
|
|
|
COMPARE(vmovl(NeonU8, q4, d2), "f3888a12 vmovl.u8 q4, d2");
|
|
|
|
|
COMPARE(vmovl(NeonS16, q4, d2), "f2908a12 vmovl.s16 q4, d2");
|
|
|
|
|
COMPARE(vmovl(NeonU32, q4, d2), "f3a08a12 vmovl.u32 q4, d2");
|
|
|
|
|
|
[wasm-simd] Fix unsigned narrow instructions
These instructions should always treat inputs as signed, and saturate to
unsigned min/max values.
E.g. given -1, it should saturate to 0.
The spec text,
https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#integer-to-integer-narrowing,
has been updated to describe this.
The changes here include codegen changes to ia32, x64, arm, and arm64,
changes to arm simulator, assembler, and disassembler to handle the case
of treating input as signed and narrowing to unsigned. The vqmovn
instruction can handle this case, our assembler wasn't allowing callers
to specify this.
The interpreter and scalar lowering are also fixed with this change.
Bug: v8:9729
Change-Id: I6f72baa825f59037f7754485df6a2964af59fe31
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1879423
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Reviewed-by: Michael Starzinger <mstarzinger@chromium.org>
Reviewed-by: Bill Budge <bbudge@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#65051}
2019-10-28 18:05:16 +00:00
|
|
|
COMPARE(vqmovn(NeonU8, NeonU8, d16, q8),
|
|
|
|
|
"f3f202e0 vqmovn.u16 d16, q8");
|
|
|
|
|
COMPARE(vqmovn(NeonS16, NeonS16, d16, q8),
|
|
|
|
|
"f3f602a0 vqmovn.s32 d16, q8");
|
|
|
|
|
COMPARE(vqmovn(NeonU32, NeonU32, d2, q4),
|
|
|
|
|
"f3ba22c8 vqmovn.u64 d2, q4");
|
|
|
|
|
COMPARE(vqmovn(NeonU32, NeonS32, d2, q4),
|
|
|
|
|
"f3ba2248 vqmovun.s64 d2, q4");
|
2016-12-15 18:15:23 +00:00
|
|
|
|
|
|
|
|
COMPARE(vmov(NeonS8, d0, 0, r0), "ee400b10 vmov.8 d0[0], r0");
|
|
|
|
|
COMPARE(vmov(NeonU8, d1, 1, r1), "ee411b30 vmov.8 d1[1], r1");
|
|
|
|
|
COMPARE(vmov(NeonS8, d2, 2, r2), "ee422b50 vmov.8 d2[2], r2");
|
|
|
|
|
COMPARE(vmov(NeonU8, d3, 3, r8), "ee438b70 vmov.8 d3[3], r8");
|
2017-07-13 10:07:46 +00:00
|
|
|
COMPARE(vmov(NeonU8, d3, 3, ip), "ee43cb70 vmov.8 d3[3], ip");
|
2016-12-15 18:15:23 +00:00
|
|
|
COMPARE(vmov(NeonS8, d4, 4, r0), "ee640b10 vmov.8 d4[4], r0");
|
|
|
|
|
COMPARE(vmov(NeonU8, d5, 5, r1), "ee651b30 vmov.8 d5[5], r1");
|
|
|
|
|
COMPARE(vmov(NeonS8, d6, 6, r2), "ee662b50 vmov.8 d6[6], r2");
|
|
|
|
|
COMPARE(vmov(NeonU8, d7, 7, r8), "ee678b70 vmov.8 d7[7], r8");
|
|
|
|
|
COMPARE(vmov(NeonS16, d0, 0, r0), "ee000b30 vmov.16 d0[0], r0");
|
|
|
|
|
COMPARE(vmov(NeonS16, d1, 1, r1), "ee011b70 vmov.16 d1[1], r1");
|
|
|
|
|
COMPARE(vmov(NeonS16, d2, 2, r2), "ee222b30 vmov.16 d2[2], r2");
|
|
|
|
|
COMPARE(vmov(NeonS16, d3, 3, r7), "ee237b70 vmov.16 d3[3], r7");
|
2017-07-13 10:07:46 +00:00
|
|
|
COMPARE(vmov(NeonS16, d3, 3, ip), "ee23cb70 vmov.16 d3[3], ip");
|
2016-12-15 18:15:23 +00:00
|
|
|
COMPARE(vmov(NeonS32, d0, 0, r0), "ee000b10 vmov.32 d0[0], r0");
|
|
|
|
|
COMPARE(vmov(NeonU32, d0, 1, r0), "ee200b10 vmov.32 d0[1], r0");
|
|
|
|
|
|
|
|
|
|
COMPARE(vmov(NeonS8, r0, d0, 0), "ee500b10 vmov.s8 r0, d0[0]");
|
|
|
|
|
COMPARE(vmov(NeonU8, r1, d1, 1), "eed11b30 vmov.u8 r1, d1[1]");
|
|
|
|
|
COMPARE(vmov(NeonS8, r2, d2, 2), "ee522b50 vmov.s8 r2, d2[2]");
|
|
|
|
|
COMPARE(vmov(NeonU8, r8, d3, 3), "eed38b70 vmov.u8 r8, d3[3]");
|
|
|
|
|
COMPARE(vmov(NeonS8, r0, d4, 4), "ee740b10 vmov.s8 r0, d4[4]");
|
|
|
|
|
COMPARE(vmov(NeonU8, r1, d5, 5), "eef51b30 vmov.u8 r1, d5[5]");
|
|
|
|
|
COMPARE(vmov(NeonS8, r2, d6, 6), "ee762b50 vmov.s8 r2, d6[6]");
|
|
|
|
|
COMPARE(vmov(NeonU8, r8, d7, 7), "eef78b70 vmov.u8 r8, d7[7]");
|
2017-07-13 10:07:46 +00:00
|
|
|
COMPARE(vmov(NeonU8, ip, d7, 7), "eef7cb70 vmov.u8 ip, d7[7]");
|
2016-12-15 18:15:23 +00:00
|
|
|
COMPARE(vmov(NeonS16, r0, d0, 0), "ee100b30 vmov.s16 r0, d0[0]");
|
|
|
|
|
COMPARE(vmov(NeonU16, r1, d1, 1), "ee911b70 vmov.u16 r1, d1[1]");
|
|
|
|
|
COMPARE(vmov(NeonS16, r2, d2, 2), "ee322b30 vmov.s16 r2, d2[2]");
|
|
|
|
|
COMPARE(vmov(NeonU16, r7, d3, 3), "eeb37b70 vmov.u16 r7, d3[3]");
|
|
|
|
|
COMPARE(vmov(NeonS32, r2, d15, 0), "ee1f2b10 vmov.32 r2, d15[0]");
|
|
|
|
|
COMPARE(vmov(NeonS32, r3, d14, 1), "ee3e3b10 vmov.32 r3, d14[1]");
|
|
|
|
|
|
2016-11-25 19:36:45 +00:00
|
|
|
COMPARE(vmov(q0, q15),
|
|
|
|
|
"f22e01fe vmov q0, q15");
|
|
|
|
|
COMPARE(vmov(q8, q9),
|
|
|
|
|
"f26201f2 vmov q8, q9");
|
2019-11-13 18:12:30 +00:00
|
|
|
COMPARE(vmov(q1, 0),
|
|
|
|
|
"f2802050 vmov.i32 q1, 0");
|
|
|
|
|
COMPARE(vmov(q1, 0x0000001200000012),
|
|
|
|
|
"f2812052 vmov.i32 q1, 18");
|
2016-12-15 18:15:23 +00:00
|
|
|
COMPARE(vmvn(q0, q15),
|
|
|
|
|
"f3b005ee vmvn q0, q15");
|
|
|
|
|
COMPARE(vmvn(q8, q9),
|
|
|
|
|
"f3f005e2 vmvn q8, q9");
|
2016-09-08 07:11:32 +00:00
|
|
|
COMPARE(vswp(d0, d31),
|
|
|
|
|
"f3b2002f vswp d0, d31");
|
|
|
|
|
COMPARE(vswp(d16, d14),
|
|
|
|
|
"f3f2000e vswp d16, d14");
|
2016-11-25 19:36:45 +00:00
|
|
|
COMPARE(vswp(q0, q15),
|
|
|
|
|
"f3b2006e vswp q0, q15");
|
|
|
|
|
COMPARE(vswp(q8, q9),
|
|
|
|
|
"f3f20062 vswp q8, q9");
|
2016-12-15 18:15:23 +00:00
|
|
|
COMPARE(vdup(Neon8, q0, r0),
|
|
|
|
|
"eee00b10 vdup.8 q0, r0");
|
|
|
|
|
COMPARE(vdup(Neon16, q1, r4),
|
|
|
|
|
"eea24b30 vdup.16 q1, r4");
|
|
|
|
|
COMPARE(vdup(Neon32, q15, r1),
|
|
|
|
|
"eeae1b90 vdup.32 q15, r1");
|
2017-05-16 20:37:16 +00:00
|
|
|
COMPARE(vdup(Neon32, q0, d1, 1),
|
|
|
|
|
"f3bc0c41 vdup.32 q0, d1[1]");
|
|
|
|
|
COMPARE(vdup(Neon32, q15, d1, 0),
|
|
|
|
|
"f3f4ec41 vdup.32 q15, d1[0]");
|
|
|
|
|
COMPARE(vdup(Neon16, q7, d8, 3),
|
|
|
|
|
"f3beec48 vdup.16 q7, d8[3]");
|
|
|
|
|
COMPARE(vdup(Neon32, d0, d30, 0),
|
|
|
|
|
"f3b40c2e vdup.32 d0, d30[0]");
|
2016-12-15 18:15:23 +00:00
|
|
|
COMPARE(vcvt_f32_s32(q15, q1),
|
|
|
|
|
"f3fbe642 vcvt.f32.s32 q15, q1");
|
|
|
|
|
COMPARE(vcvt_f32_u32(q8, q9),
|
|
|
|
|
"f3fb06e2 vcvt.f32.u32 q8, q9");
|
|
|
|
|
COMPARE(vcvt_s32_f32(q15, q1),
|
|
|
|
|
"f3fbe742 vcvt.s32.f32 q15, q1");
|
|
|
|
|
COMPARE(vcvt_u32_f32(q8, q9),
|
|
|
|
|
"f3fb07e2 vcvt.u32.f32 q8, q9");
|
2016-12-17 21:56:26 +00:00
|
|
|
COMPARE(vabs(q0, q1),
|
|
|
|
|
"f3b90742 vabs.f32 q0, q1");
|
|
|
|
|
COMPARE(vabs(Neon8, q6, q7),
|
|
|
|
|
"f3b1c34e vabs.s8 q6, q7");
|
|
|
|
|
COMPARE(vabs(Neon16, q0, q1),
|
|
|
|
|
"f3b50342 vabs.s16 q0, q1");
|
|
|
|
|
COMPARE(vabs(Neon32, q0, q1),
|
|
|
|
|
"f3b90342 vabs.s32 q0, q1");
|
|
|
|
|
COMPARE(vneg(q0, q1),
|
|
|
|
|
"f3b907c2 vneg.f32 q0, q1");
|
|
|
|
|
COMPARE(vneg(Neon8, q6, q7),
|
|
|
|
|
"f3b1c3ce vneg.s8 q6, q7");
|
|
|
|
|
COMPARE(vneg(Neon16, q0, q1),
|
|
|
|
|
"f3b503c2 vneg.s16 q0, q1");
|
|
|
|
|
COMPARE(vneg(Neon32, q0, q1),
|
|
|
|
|
"f3b903c2 vneg.s32 q0, q1");
|
2016-11-25 19:36:45 +00:00
|
|
|
COMPARE(veor(d0, d1, d2),
|
|
|
|
|
"f3010112 veor d0, d1, d2");
|
|
|
|
|
COMPARE(veor(d0, d30, d31),
|
|
|
|
|
"f30e01bf veor d0, d30, d31");
|
|
|
|
|
COMPARE(veor(q0, q1, q2),
|
|
|
|
|
"f3020154 veor q0, q1, q2");
|
|
|
|
|
COMPARE(veor(q15, q0, q8),
|
|
|
|
|
"f340e170 veor q15, q0, q8");
|
2017-01-12 15:36:29 +00:00
|
|
|
COMPARE(vand(q15, q0, q8),
|
|
|
|
|
"f240e170 vand q15, q0, q8");
|
2020-01-14 20:20:20 +00:00
|
|
|
COMPARE(vbic(q15, q0, q8),
|
|
|
|
|
"f250e170 vbic q15, q0, q8");
|
2017-01-12 15:36:29 +00:00
|
|
|
COMPARE(vorr(q15, q0, q8),
|
|
|
|
|
"f260e170 vorr q15, q0, q8");
|
2017-01-16 19:36:25 +00:00
|
|
|
COMPARE(vmin(q15, q0, q8),
|
|
|
|
|
"f260ef60 vmin.f32 q15, q0, q8");
|
|
|
|
|
COMPARE(vmax(q15, q0, q8),
|
|
|
|
|
"f240ef60 vmax.f32 q15, q0, q8");
|
|
|
|
|
COMPARE(vmax(NeonS8, q0, q1, q2),
|
|
|
|
|
"f2020644 vmax.s8 q0, q1, q2");
|
|
|
|
|
COMPARE(vmin(NeonU16, q1, q2, q8),
|
|
|
|
|
"f3142670 vmin.u16 q1, q2, q8");
|
|
|
|
|
COMPARE(vmax(NeonS32, q15, q0, q8),
|
|
|
|
|
"f260e660 vmax.s32 q15, q0, q8");
|
2017-04-24 18:53:16 +00:00
|
|
|
COMPARE(vpadd(d0, d1, d2),
|
|
|
|
|
"f3010d02 vpadd.f32 d0, d1, d2");
|
|
|
|
|
COMPARE(vpadd(Neon8, d0, d1, d2),
|
|
|
|
|
"f2010b12 vpadd.i8 d0, d1, d2");
|
|
|
|
|
COMPARE(vpadd(Neon16, d0, d1, d2),
|
|
|
|
|
"f2110b12 vpadd.i16 d0, d1, d2");
|
|
|
|
|
COMPARE(vpadd(Neon32, d0, d1, d2),
|
|
|
|
|
"f2210b12 vpadd.i32 d0, d1, d2");
|
2017-03-02 19:50:33 +00:00
|
|
|
COMPARE(vpmax(NeonS8, d0, d1, d2),
|
|
|
|
|
"f2010a02 vpmax.s8 d0, d1, d2");
|
|
|
|
|
COMPARE(vpmin(NeonU16, d1, d2, d8),
|
|
|
|
|
"f3121a18 vpmin.u16 d1, d2, d8");
|
|
|
|
|
COMPARE(vpmax(NeonS32, d15, d0, d8),
|
|
|
|
|
"f220fa08 vpmax.s32 d15, d0, d8");
|
2016-12-15 18:15:23 +00:00
|
|
|
COMPARE(vadd(q15, q0, q8),
|
|
|
|
|
"f240ed60 vadd.f32 q15, q0, q8");
|
|
|
|
|
COMPARE(vadd(Neon8, q0, q1, q2),
|
|
|
|
|
"f2020844 vadd.i8 q0, q1, q2");
|
|
|
|
|
COMPARE(vadd(Neon16, q1, q2, q8),
|
|
|
|
|
"f2142860 vadd.i16 q1, q2, q8");
|
|
|
|
|
COMPARE(vadd(Neon32, q15, q0, q8),
|
|
|
|
|
"f260e860 vadd.i32 q15, q0, q8");
|
2017-02-01 18:56:28 +00:00
|
|
|
COMPARE(vqadd(NeonU8, q0, q1, q2),
|
|
|
|
|
"f3020054 vqadd.u8 q0, q1, q2");
|
|
|
|
|
COMPARE(vqadd(NeonS16, q1, q2, q8),
|
|
|
|
|
"f2142070 vqadd.s16 q1, q2, q8");
|
|
|
|
|
COMPARE(vqadd(NeonU32, q15, q0, q8),
|
|
|
|
|
"f360e070 vqadd.u32 q15, q0, q8");
|
2016-12-15 18:15:23 +00:00
|
|
|
COMPARE(vsub(q15, q0, q8),
|
|
|
|
|
"f260ed60 vsub.f32 q15, q0, q8");
|
|
|
|
|
COMPARE(vsub(Neon8, q0, q1, q2),
|
|
|
|
|
"f3020844 vsub.i8 q0, q1, q2");
|
|
|
|
|
COMPARE(vsub(Neon16, q1, q2, q8),
|
|
|
|
|
"f3142860 vsub.i16 q1, q2, q8");
|
|
|
|
|
COMPARE(vsub(Neon32, q15, q0, q8),
|
|
|
|
|
"f360e860 vsub.i32 q15, q0, q8");
|
2017-02-01 18:56:28 +00:00
|
|
|
COMPARE(vqsub(NeonU8, q0, q1, q2),
|
|
|
|
|
"f3020254 vqsub.u8 q0, q1, q2");
|
|
|
|
|
COMPARE(vqsub(NeonS16, q1, q2, q8),
|
|
|
|
|
"f2142270 vqsub.s16 q1, q2, q8");
|
|
|
|
|
COMPARE(vqsub(NeonU32, q15, q0, q8),
|
|
|
|
|
"f360e270 vqsub.u32 q15, q0, q8");
|
2016-12-17 21:56:26 +00:00
|
|
|
COMPARE(vmul(q0, q1, q2),
|
|
|
|
|
"f3020d54 vmul.f32 q0, q1, q2");
|
|
|
|
|
COMPARE(vmul(Neon8, q0, q1, q2),
|
|
|
|
|
"f2020954 vmul.i8 q0, q1, q2");
|
|
|
|
|
COMPARE(vmul(Neon16, q1, q2, q8),
|
|
|
|
|
"f2142970 vmul.i16 q1, q2, q8");
|
|
|
|
|
COMPARE(vmul(Neon32, q15, q0, q8),
|
|
|
|
|
"f260e970 vmul.i32 q15, q0, q8");
|
2020-01-17 17:13:06 +00:00
|
|
|
|
|
|
|
|
COMPARE(vmull(NeonU32, q15, d0, d8),
|
|
|
|
|
"f3e0ec08 vmull.u32 q15, d0, d8");
|
|
|
|
|
COMPARE(vmlal(NeonU32, q15, d0, d8),
|
|
|
|
|
"f3e0e808 vmlal.u32 q15, d0, d8");
|
|
|
|
|
|
2017-01-23 18:24:27 +00:00
|
|
|
COMPARE(vshl(NeonS8, q15, q0, 6),
|
|
|
|
|
"f2cee550 vshl.i8 q15, q0, #6");
|
|
|
|
|
COMPARE(vshl(NeonU16, q15, q0, 10),
|
|
|
|
|
"f2dae550 vshl.i16 q15, q0, #10");
|
|
|
|
|
COMPARE(vshl(NeonS32, q15, q0, 17),
|
|
|
|
|
"f2f1e550 vshl.i32 q15, q0, #17");
|
2020-01-10 17:46:51 +00:00
|
|
|
COMPARE(vshl(NeonS64, q15, q0, 40),
|
|
|
|
|
"f2e8e5d0 vshl.i64 q15, q0, #40");
|
2019-09-17 22:05:14 +00:00
|
|
|
COMPARE(vshl(NeonS8, q15, q0, q1),
|
|
|
|
|
"f242e440 vshl.s8 q15, q0, q1");
|
|
|
|
|
COMPARE(vshl(NeonU16, q15, q2, q3),
|
|
|
|
|
"f356e444 vshl.u16 q15, q2, q3");
|
|
|
|
|
COMPARE(vshl(NeonS32, q15, q4, q5),
|
|
|
|
|
"f26ae448 vshl.s32 q15, q4, q5");
|
2017-01-23 18:24:27 +00:00
|
|
|
COMPARE(vshr(NeonS8, q15, q0, 6),
|
|
|
|
|
"f2cae050 vshr.s8 q15, q0, #6");
|
|
|
|
|
COMPARE(vshr(NeonU16, q15, q0, 10),
|
|
|
|
|
"f3d6e050 vshr.u16 q15, q0, #10");
|
|
|
|
|
COMPARE(vshr(NeonS32, q15, q0, 17),
|
|
|
|
|
"f2efe050 vshr.s32 q15, q0, #17");
|
2020-01-10 17:46:51 +00:00
|
|
|
COMPARE(vshr(NeonS64, q15, q0, 40),
|
|
|
|
|
"f2d8e0d0 vshr.s64 q15, q0, #40");
|
|
|
|
|
COMPARE(vshr(NeonU64, q15, q0, 40),
|
|
|
|
|
"f3d8e0d0 vshr.u64 q15, q0, #40");
|
2017-05-16 20:37:16 +00:00
|
|
|
COMPARE(vsli(Neon64, d2, d0, 32),
|
|
|
|
|
"f3a02590 vsli.64 d2, d0, #32");
|
|
|
|
|
COMPARE(vsli(Neon32, d7, d8, 17),
|
|
|
|
|
"f3b17518 vsli.32 d7, d8, #17");
|
|
|
|
|
COMPARE(vsri(Neon64, d2, d0, 32),
|
|
|
|
|
"f3a02490 vsri.64 d2, d0, #32");
|
|
|
|
|
COMPARE(vsri(Neon16, d7, d8, 8),
|
|
|
|
|
"f3987418 vsri.16 d7, d8, #8");
|
2017-01-10 12:36:59 +00:00
|
|
|
COMPARE(vrecpe(q15, q0),
|
|
|
|
|
"f3fbe540 vrecpe.f32 q15, q0");
|
|
|
|
|
COMPARE(vrecps(q15, q0, q8),
|
|
|
|
|
"f240ef70 vrecps.f32 q15, q0, q8");
|
|
|
|
|
COMPARE(vrsqrte(q15, q0),
|
|
|
|
|
"f3fbe5c0 vrsqrte.f32 q15, q0");
|
|
|
|
|
COMPARE(vrsqrts(q15, q0, q8),
|
|
|
|
|
"f260ef70 vrsqrts.f32 q15, q0, q8");
|
2016-12-15 18:15:23 +00:00
|
|
|
COMPARE(vtst(Neon8, q0, q1, q2),
|
|
|
|
|
"f2020854 vtst.i8 q0, q1, q2");
|
|
|
|
|
COMPARE(vtst(Neon16, q1, q2, q8),
|
|
|
|
|
"f2142870 vtst.i16 q1, q2, q8");
|
|
|
|
|
COMPARE(vtst(Neon32, q15, q0, q8),
|
|
|
|
|
"f260e870 vtst.i32 q15, q0, q8");
|
2016-12-20 13:06:58 +00:00
|
|
|
COMPARE(vceq(q0, q1, q2),
|
|
|
|
|
"f2020e44 vceq.f32 q0, q1, q2");
|
2017-01-12 11:20:08 +00:00
|
|
|
COMPARE(vcge(q0, q1, q2),
|
|
|
|
|
"f3020e44 vcge.f32 q0, q1, q2");
|
|
|
|
|
COMPARE(vcgt(q0, q1, q2),
|
|
|
|
|
"f3220e44 vcgt.f32 q0, q1, q2");
|
2016-12-15 18:15:23 +00:00
|
|
|
COMPARE(vceq(Neon8, q0, q1, q2),
|
|
|
|
|
"f3020854 vceq.i8 q0, q1, q2");
|
|
|
|
|
COMPARE(vceq(Neon16, q1, q2, q8),
|
|
|
|
|
"f3142870 vceq.i16 q1, q2, q8");
|
|
|
|
|
COMPARE(vceq(Neon32, q15, q0, q8),
|
|
|
|
|
"f360e870 vceq.i32 q15, q0, q8");
|
2017-01-12 11:20:08 +00:00
|
|
|
COMPARE(vcge(NeonS8, q0, q1, q2),
|
|
|
|
|
"f2020354 vcge.s8 q0, q1, q2");
|
|
|
|
|
COMPARE(vcge(NeonU16, q1, q2, q8),
|
|
|
|
|
"f3142370 vcge.u16 q1, q2, q8");
|
|
|
|
|
COMPARE(vcge(NeonS32, q15, q0, q8),
|
|
|
|
|
"f260e370 vcge.s32 q15, q0, q8");
|
|
|
|
|
COMPARE(vcgt(NeonS8, q0, q1, q2),
|
|
|
|
|
"f2020344 vcgt.s8 q0, q1, q2");
|
|
|
|
|
COMPARE(vcgt(NeonU16, q1, q2, q8),
|
|
|
|
|
"f3142360 vcgt.u16 q1, q2, q8");
|
|
|
|
|
COMPARE(vcgt(NeonS32, q15, q0, q8),
|
|
|
|
|
"f260e360 vcgt.s32 q15, q0, q8");
|
2020-01-02 17:33:34 +00:00
|
|
|
COMPARE(vrhadd(NeonU8, q0, q1, q2),
|
|
|
|
|
"f3020144 vrhadd.u8 q0, q1, q2");
|
|
|
|
|
COMPARE(vrhadd(NeonU16, q1, q2, q8),
|
|
|
|
|
"f3142160 vrhadd.u16 q1, q2, q8");
|
|
|
|
|
COMPARE(vrhadd(NeonU32, q15, q0, q8),
|
|
|
|
|
"f360e160 vrhadd.u32 q15, q0, q8");
|
2016-12-15 18:15:23 +00:00
|
|
|
COMPARE(vbsl(q0, q1, q2),
|
|
|
|
|
"f3120154 vbsl q0, q1, q2");
|
|
|
|
|
COMPARE(vbsl(q15, q0, q8),
|
|
|
|
|
"f350e170 vbsl q15, q0, q8");
|
2016-12-17 21:56:26 +00:00
|
|
|
COMPARE(vext(q15, q0, q8, 3),
|
|
|
|
|
"f2f0e360 vext.8 q15, q0, q8, #3");
|
2017-04-10 21:41:02 +00:00
|
|
|
COMPARE(vzip(Neon16, d15, d0),
|
|
|
|
|
"f3b6f180 vzip.16 d15, d0");
|
2016-12-17 21:56:26 +00:00
|
|
|
COMPARE(vzip(Neon16, q15, q0),
|
|
|
|
|
"f3f6e1c0 vzip.16 q15, q0");
|
2017-04-10 21:41:02 +00:00
|
|
|
COMPARE(vuzp(Neon16, d15, d0),
|
|
|
|
|
"f3b6f100 vuzp.16 d15, d0");
|
2017-03-14 16:28:45 +00:00
|
|
|
COMPARE(vuzp(Neon16, q15, q0),
|
|
|
|
|
"f3f6e140 vuzp.16 q15, q0");
|
2016-12-17 21:56:26 +00:00
|
|
|
COMPARE(vrev64(Neon8, q15, q0),
|
|
|
|
|
"f3f0e040 vrev64.8 q15, q0");
|
2017-04-10 21:41:02 +00:00
|
|
|
COMPARE(vtrn(Neon16, d15, d0),
|
|
|
|
|
"f3b6f080 vtrn.16 d15, d0");
|
2017-03-14 16:28:45 +00:00
|
|
|
COMPARE(vtrn(Neon16, q15, q0),
|
|
|
|
|
"f3f6e0c0 vtrn.16 q15, q0");
|
2016-12-15 18:15:23 +00:00
|
|
|
COMPARE(vtbl(d0, NeonListOperand(d1, 1), d2),
|
|
|
|
|
"f3b10802 vtbl.8 d0, {d1}, d2");
|
|
|
|
|
COMPARE(vtbl(d31, NeonListOperand(d0, 2), d4),
|
|
|
|
|
"f3f0f904 vtbl.8 d31, {d0, d1}, d4");
|
|
|
|
|
COMPARE(vtbl(d15, NeonListOperand(d1, 3), d5),
|
|
|
|
|
"f3b1fa05 vtbl.8 d15, {d1, d2, d3}, d5");
|
|
|
|
|
COMPARE(vtbl(d15, NeonListOperand(d1, 4), d5),
|
|
|
|
|
"f3b1fb05 vtbl.8 d15, {d1, d2, d3, d4}, d5");
|
|
|
|
|
COMPARE(vtbx(d0, NeonListOperand(d1, 1), d2),
|
|
|
|
|
"f3b10842 vtbx.8 d0, {d1}, d2");
|
|
|
|
|
COMPARE(vtbx(d31, NeonListOperand(d0, 2), d4),
|
|
|
|
|
"f3f0f944 vtbx.8 d31, {d0, d1}, d4");
|
|
|
|
|
COMPARE(vtbx(d15, NeonListOperand(d1, 3), d5),
|
|
|
|
|
"f3b1fa45 vtbx.8 d15, {d1, d2, d3}, d5");
|
|
|
|
|
COMPARE(vtbx(d15, NeonListOperand(d1, 4), d5),
|
|
|
|
|
"f3b1fb45 vtbx.8 d15, {d1, d2, d3, d4}, d5");
|
2013-07-10 15:32:39 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
VERIFY_RUN();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2011-05-12 14:44:49 +00:00
|
|
|
TEST(LoadStore) {
|
2012-01-13 13:09:52 +00:00
|
|
|
SET_UP();
|
2011-05-12 14:44:49 +00:00
|
|
|
|
|
|
|
|
COMPARE(ldrb(r0, MemOperand(r1)),
|
|
|
|
|
"e5d10000 ldrb r0, [r1, #+0]");
|
|
|
|
|
COMPARE(ldrb(r2, MemOperand(r3, 42)),
|
|
|
|
|
"e5d3202a ldrb r2, [r3, #+42]");
|
|
|
|
|
COMPARE(ldrb(r4, MemOperand(r5, -42)),
|
|
|
|
|
"e555402a ldrb r4, [r5, #-42]");
|
|
|
|
|
COMPARE(ldrb(r6, MemOperand(r7, 42, PostIndex)),
|
|
|
|
|
"e4d7602a ldrb r6, [r7], #+42");
|
|
|
|
|
COMPARE(ldrb(r8, MemOperand(r9, -42, PostIndex)),
|
|
|
|
|
"e459802a ldrb r8, [r9], #-42");
|
|
|
|
|
COMPARE(ldrb(r10, MemOperand(fp, 42, PreIndex)),
|
|
|
|
|
"e5fba02a ldrb r10, [fp, #+42]!");
|
|
|
|
|
COMPARE(ldrb(ip, MemOperand(sp, -42, PreIndex)),
|
|
|
|
|
"e57dc02a ldrb ip, [sp, #-42]!");
|
|
|
|
|
COMPARE(ldrb(r0, MemOperand(r1, r2)),
|
|
|
|
|
"e7d10002 ldrb r0, [r1, +r2]");
|
|
|
|
|
COMPARE(ldrb(r0, MemOperand(r1, r2, NegOffset)),
|
|
|
|
|
"e7510002 ldrb r0, [r1, -r2]");
|
|
|
|
|
COMPARE(ldrb(r0, MemOperand(r1, r2, PostIndex)),
|
|
|
|
|
"e6d10002 ldrb r0, [r1], +r2");
|
|
|
|
|
COMPARE(ldrb(r0, MemOperand(r1, r2, NegPostIndex)),
|
|
|
|
|
"e6510002 ldrb r0, [r1], -r2");
|
|
|
|
|
COMPARE(ldrb(r0, MemOperand(r1, r2, PreIndex)),
|
|
|
|
|
"e7f10002 ldrb r0, [r1, +r2]!");
|
|
|
|
|
COMPARE(ldrb(r0, MemOperand(r1, r2, NegPreIndex)),
|
|
|
|
|
"e7710002 ldrb r0, [r1, -r2]!");
|
|
|
|
|
|
|
|
|
|
COMPARE(strb(r0, MemOperand(r1)),
|
|
|
|
|
"e5c10000 strb r0, [r1, #+0]");
|
|
|
|
|
COMPARE(strb(r2, MemOperand(r3, 42)),
|
|
|
|
|
"e5c3202a strb r2, [r3, #+42]");
|
|
|
|
|
COMPARE(strb(r4, MemOperand(r5, -42)),
|
|
|
|
|
"e545402a strb r4, [r5, #-42]");
|
|
|
|
|
COMPARE(strb(r6, MemOperand(r7, 42, PostIndex)),
|
|
|
|
|
"e4c7602a strb r6, [r7], #+42");
|
|
|
|
|
COMPARE(strb(r8, MemOperand(r9, -42, PostIndex)),
|
|
|
|
|
"e449802a strb r8, [r9], #-42");
|
|
|
|
|
COMPARE(strb(r10, MemOperand(fp, 42, PreIndex)),
|
|
|
|
|
"e5eba02a strb r10, [fp, #+42]!");
|
|
|
|
|
COMPARE(strb(ip, MemOperand(sp, -42, PreIndex)),
|
|
|
|
|
"e56dc02a strb ip, [sp, #-42]!");
|
|
|
|
|
COMPARE(strb(r0, MemOperand(r1, r2)),
|
|
|
|
|
"e7c10002 strb r0, [r1, +r2]");
|
|
|
|
|
COMPARE(strb(r0, MemOperand(r1, r2, NegOffset)),
|
|
|
|
|
"e7410002 strb r0, [r1, -r2]");
|
|
|
|
|
COMPARE(strb(r0, MemOperand(r1, r2, PostIndex)),
|
|
|
|
|
"e6c10002 strb r0, [r1], +r2");
|
|
|
|
|
COMPARE(strb(r0, MemOperand(r1, r2, NegPostIndex)),
|
|
|
|
|
"e6410002 strb r0, [r1], -r2");
|
|
|
|
|
COMPARE(strb(r0, MemOperand(r1, r2, PreIndex)),
|
|
|
|
|
"e7e10002 strb r0, [r1, +r2]!");
|
|
|
|
|
COMPARE(strb(r0, MemOperand(r1, r2, NegPreIndex)),
|
|
|
|
|
"e7610002 strb r0, [r1, -r2]!");
|
|
|
|
|
|
|
|
|
|
COMPARE(ldrh(r0, MemOperand(r1)),
|
|
|
|
|
"e1d100b0 ldrh r0, [r1, #+0]");
|
|
|
|
|
COMPARE(ldrh(r2, MemOperand(r3, 42)),
|
|
|
|
|
"e1d322ba ldrh r2, [r3, #+42]");
|
|
|
|
|
COMPARE(ldrh(r4, MemOperand(r5, -42)),
|
|
|
|
|
"e15542ba ldrh r4, [r5, #-42]");
|
|
|
|
|
COMPARE(ldrh(r6, MemOperand(r7, 42, PostIndex)),
|
|
|
|
|
"e0d762ba ldrh r6, [r7], #+42");
|
|
|
|
|
COMPARE(ldrh(r8, MemOperand(r9, -42, PostIndex)),
|
|
|
|
|
"e05982ba ldrh r8, [r9], #-42");
|
|
|
|
|
COMPARE(ldrh(r10, MemOperand(fp, 42, PreIndex)),
|
|
|
|
|
"e1fba2ba ldrh r10, [fp, #+42]!");
|
|
|
|
|
COMPARE(ldrh(ip, MemOperand(sp, -42, PreIndex)),
|
|
|
|
|
"e17dc2ba ldrh ip, [sp, #-42]!");
|
|
|
|
|
COMPARE(ldrh(r0, MemOperand(r1, r2)),
|
|
|
|
|
"e19100b2 ldrh r0, [r1, +r2]");
|
|
|
|
|
COMPARE(ldrh(r0, MemOperand(r1, r2, NegOffset)),
|
|
|
|
|
"e11100b2 ldrh r0, [r1, -r2]");
|
|
|
|
|
COMPARE(ldrh(r0, MemOperand(r1, r2, PostIndex)),
|
|
|
|
|
"e09100b2 ldrh r0, [r1], +r2");
|
|
|
|
|
COMPARE(ldrh(r0, MemOperand(r1, r2, NegPostIndex)),
|
|
|
|
|
"e01100b2 ldrh r0, [r1], -r2");
|
|
|
|
|
COMPARE(ldrh(r0, MemOperand(r1, r2, PreIndex)),
|
|
|
|
|
"e1b100b2 ldrh r0, [r1, +r2]!");
|
|
|
|
|
COMPARE(ldrh(r0, MemOperand(r1, r2, NegPreIndex)),
|
|
|
|
|
"e13100b2 ldrh r0, [r1, -r2]!");
|
|
|
|
|
|
|
|
|
|
COMPARE(strh(r0, MemOperand(r1)),
|
|
|
|
|
"e1c100b0 strh r0, [r1, #+0]");
|
|
|
|
|
COMPARE(strh(r2, MemOperand(r3, 42)),
|
|
|
|
|
"e1c322ba strh r2, [r3, #+42]");
|
|
|
|
|
COMPARE(strh(r4, MemOperand(r5, -42)),
|
|
|
|
|
"e14542ba strh r4, [r5, #-42]");
|
|
|
|
|
COMPARE(strh(r6, MemOperand(r7, 42, PostIndex)),
|
|
|
|
|
"e0c762ba strh r6, [r7], #+42");
|
|
|
|
|
COMPARE(strh(r8, MemOperand(r9, -42, PostIndex)),
|
|
|
|
|
"e04982ba strh r8, [r9], #-42");
|
|
|
|
|
COMPARE(strh(r10, MemOperand(fp, 42, PreIndex)),
|
|
|
|
|
"e1eba2ba strh r10, [fp, #+42]!");
|
|
|
|
|
COMPARE(strh(ip, MemOperand(sp, -42, PreIndex)),
|
|
|
|
|
"e16dc2ba strh ip, [sp, #-42]!");
|
|
|
|
|
COMPARE(strh(r0, MemOperand(r1, r2)),
|
|
|
|
|
"e18100b2 strh r0, [r1, +r2]");
|
|
|
|
|
COMPARE(strh(r0, MemOperand(r1, r2, NegOffset)),
|
|
|
|
|
"e10100b2 strh r0, [r1, -r2]");
|
|
|
|
|
COMPARE(strh(r0, MemOperand(r1, r2, PostIndex)),
|
|
|
|
|
"e08100b2 strh r0, [r1], +r2");
|
|
|
|
|
COMPARE(strh(r0, MemOperand(r1, r2, NegPostIndex)),
|
|
|
|
|
"e00100b2 strh r0, [r1], -r2");
|
|
|
|
|
COMPARE(strh(r0, MemOperand(r1, r2, PreIndex)),
|
|
|
|
|
"e1a100b2 strh r0, [r1, +r2]!");
|
|
|
|
|
COMPARE(strh(r0, MemOperand(r1, r2, NegPreIndex)),
|
|
|
|
|
"e12100b2 strh r0, [r1, -r2]!");
|
|
|
|
|
|
|
|
|
|
COMPARE(ldr(r0, MemOperand(r1)),
|
|
|
|
|
"e5910000 ldr r0, [r1, #+0]");
|
|
|
|
|
COMPARE(ldr(r2, MemOperand(r3, 42)),
|
|
|
|
|
"e593202a ldr r2, [r3, #+42]");
|
|
|
|
|
COMPARE(ldr(r4, MemOperand(r5, -42)),
|
|
|
|
|
"e515402a ldr r4, [r5, #-42]");
|
|
|
|
|
COMPARE(ldr(r6, MemOperand(r7, 42, PostIndex)),
|
|
|
|
|
"e497602a ldr r6, [r7], #+42");
|
|
|
|
|
COMPARE(ldr(r8, MemOperand(r9, -42, PostIndex)),
|
|
|
|
|
"e419802a ldr r8, [r9], #-42");
|
|
|
|
|
COMPARE(ldr(r10, MemOperand(fp, 42, PreIndex)),
|
|
|
|
|
"e5bba02a ldr r10, [fp, #+42]!");
|
|
|
|
|
COMPARE(ldr(ip, MemOperand(sp, -42, PreIndex)),
|
|
|
|
|
"e53dc02a ldr ip, [sp, #-42]!");
|
|
|
|
|
COMPARE(ldr(r0, MemOperand(r1, r2)),
|
|
|
|
|
"e7910002 ldr r0, [r1, +r2]");
|
|
|
|
|
COMPARE(ldr(r0, MemOperand(r1, r2, NegOffset)),
|
|
|
|
|
"e7110002 ldr r0, [r1, -r2]");
|
|
|
|
|
COMPARE(ldr(r0, MemOperand(r1, r2, PostIndex)),
|
|
|
|
|
"e6910002 ldr r0, [r1], +r2");
|
|
|
|
|
COMPARE(ldr(r0, MemOperand(r1, r2, NegPostIndex)),
|
|
|
|
|
"e6110002 ldr r0, [r1], -r2");
|
|
|
|
|
COMPARE(ldr(r0, MemOperand(r1, r2, PreIndex)),
|
|
|
|
|
"e7b10002 ldr r0, [r1, +r2]!");
|
|
|
|
|
COMPARE(ldr(r0, MemOperand(r1, r2, NegPreIndex)),
|
|
|
|
|
"e7310002 ldr r0, [r1, -r2]!");
|
|
|
|
|
|
|
|
|
|
COMPARE(str(r0, MemOperand(r1)),
|
|
|
|
|
"e5810000 str r0, [r1, #+0]");
|
|
|
|
|
COMPARE(str(r2, MemOperand(r3, 42)),
|
|
|
|
|
"e583202a str r2, [r3, #+42]");
|
|
|
|
|
COMPARE(str(r4, MemOperand(r5, -42)),
|
|
|
|
|
"e505402a str r4, [r5, #-42]");
|
|
|
|
|
COMPARE(str(r6, MemOperand(r7, 42, PostIndex)),
|
|
|
|
|
"e487602a str r6, [r7], #+42");
|
|
|
|
|
COMPARE(str(r8, MemOperand(r9, -42, PostIndex)),
|
|
|
|
|
"e409802a str r8, [r9], #-42");
|
|
|
|
|
COMPARE(str(r10, MemOperand(fp, 42, PreIndex)),
|
|
|
|
|
"e5aba02a str r10, [fp, #+42]!");
|
|
|
|
|
COMPARE(str(ip, MemOperand(sp, -42, PreIndex)),
|
|
|
|
|
"e52dc02a str ip, [sp, #-42]!");
|
|
|
|
|
COMPARE(str(r0, MemOperand(r1, r2)),
|
|
|
|
|
"e7810002 str r0, [r1, +r2]");
|
|
|
|
|
COMPARE(str(r0, MemOperand(r1, r2, NegOffset)),
|
|
|
|
|
"e7010002 str r0, [r1, -r2]");
|
|
|
|
|
COMPARE(str(r0, MemOperand(r1, r2, PostIndex)),
|
|
|
|
|
"e6810002 str r0, [r1], +r2");
|
|
|
|
|
COMPARE(str(r0, MemOperand(r1, r2, NegPostIndex)),
|
|
|
|
|
"e6010002 str r0, [r1], -r2");
|
|
|
|
|
COMPARE(str(r0, MemOperand(r1, r2, PreIndex)),
|
|
|
|
|
"e7a10002 str r0, [r1, +r2]!");
|
|
|
|
|
COMPARE(str(r0, MemOperand(r1, r2, NegPreIndex)),
|
|
|
|
|
"e7210002 str r0, [r1, -r2]!");
|
|
|
|
|
|
|
|
|
|
if (CpuFeatures::IsSupported(ARMv7)) {
|
2013-03-05 10:48:16 +00:00
|
|
|
CpuFeatureScope scope(&assm, ARMv7);
|
2011-05-12 14:44:49 +00:00
|
|
|
COMPARE(ldrd(r0, r1, MemOperand(r1)),
|
|
|
|
|
"e1c100d0 ldrd r0, [r1, #+0]");
|
|
|
|
|
COMPARE(ldrd(r2, r3, MemOperand(r3, 127)),
|
|
|
|
|
"e1c327df ldrd r2, [r3, #+127]");
|
|
|
|
|
COMPARE(ldrd(r4, r5, MemOperand(r5, -127)),
|
|
|
|
|
"e14547df ldrd r4, [r5, #-127]");
|
|
|
|
|
COMPARE(ldrd(r6, r7, MemOperand(r7, 127, PostIndex)),
|
|
|
|
|
"e0c767df ldrd r6, [r7], #+127");
|
|
|
|
|
COMPARE(ldrd(r8, r9, MemOperand(r9, -127, PostIndex)),
|
|
|
|
|
"e04987df ldrd r8, [r9], #-127");
|
|
|
|
|
COMPARE(ldrd(r10, fp, MemOperand(fp, 127, PreIndex)),
|
|
|
|
|
"e1eba7df ldrd r10, [fp, #+127]!");
|
|
|
|
|
COMPARE(ldrd(ip, sp, MemOperand(sp, -127, PreIndex)),
|
|
|
|
|
"e16dc7df ldrd ip, [sp, #-127]!");
|
|
|
|
|
|
|
|
|
|
COMPARE(strd(r0, r1, MemOperand(r1)),
|
|
|
|
|
"e1c100f0 strd r0, [r1, #+0]");
|
|
|
|
|
COMPARE(strd(r2, r3, MemOperand(r3, 127)),
|
|
|
|
|
"e1c327ff strd r2, [r3, #+127]");
|
|
|
|
|
COMPARE(strd(r4, r5, MemOperand(r5, -127)),
|
|
|
|
|
"e14547ff strd r4, [r5, #-127]");
|
|
|
|
|
COMPARE(strd(r6, r7, MemOperand(r7, 127, PostIndex)),
|
|
|
|
|
"e0c767ff strd r6, [r7], #+127");
|
|
|
|
|
COMPARE(strd(r8, r9, MemOperand(r9, -127, PostIndex)),
|
|
|
|
|
"e04987ff strd r8, [r9], #-127");
|
|
|
|
|
COMPARE(strd(r10, fp, MemOperand(fp, 127, PreIndex)),
|
|
|
|
|
"e1eba7ff strd r10, [fp, #+127]!");
|
|
|
|
|
COMPARE(strd(ip, sp, MemOperand(sp, -127, PreIndex)),
|
|
|
|
|
"e16dc7ff strd ip, [sp, #-127]!");
|
2013-07-10 15:32:39 +00:00
|
|
|
|
|
|
|
|
COMPARE(pld(MemOperand(r1, 0)),
|
|
|
|
|
"f5d1f000 pld [r1]");
|
2017-07-13 10:07:46 +00:00
|
|
|
COMPARE(pld(MemOperand(ip, 64)),
|
|
|
|
|
"f5dcf040 pld [ip, #+64]");
|
2013-07-10 15:32:39 +00:00
|
|
|
COMPARE(pld(MemOperand(r2, 128)),
|
|
|
|
|
"f5d2f080 pld [r2, #+128]");
|
2011-05-12 14:44:49 +00:00
|
|
|
}
|
|
|
|
|
|
2017-06-22 10:00:56 +00:00
|
|
|
// Test out-of-bound immediates.
|
|
|
|
|
COMPARE(ldrb(r6, MemOperand(r7, 42 << 12)),
|
|
|
|
|
"e3a06a2a mov r6, #172032",
|
|
|
|
|
"e7d76006 ldrb r6, [r7, +r6]");
|
|
|
|
|
COMPARE(ldrh(r6, MemOperand(r7, 42 << 8, PostIndex)),
|
|
|
|
|
"e3a06c2a mov r6, #10752",
|
|
|
|
|
"e09760b6 ldrh r6, [r7], +r6");
|
|
|
|
|
// Make sure ip is used if the destination is the same as the base.
|
|
|
|
|
COMPARE(ldr(r8, MemOperand(r8, 42 << 12, PreIndex)),
|
|
|
|
|
"e3a0ca2a mov ip, #172032",
|
|
|
|
|
"e7b8800c ldr r8, [r8, +ip]!");
|
|
|
|
|
COMPARE(strb(r6, MemOperand(r7, 42 << 12)),
|
|
|
|
|
"e3a0ca2a mov ip, #172032",
|
|
|
|
|
"e7c7600c strb r6, [r7, +ip]");
|
|
|
|
|
COMPARE(strh(r6, MemOperand(r7, 42 << 8, PostIndex)),
|
|
|
|
|
"e3a0cc2a mov ip, #10752",
|
|
|
|
|
"e08760bc strh r6, [r7], +ip");
|
|
|
|
|
COMPARE(str(r6, MemOperand(r7, 42 << 12, PreIndex)),
|
|
|
|
|
"e3a0ca2a mov ip, #172032",
|
|
|
|
|
"e7a7600c str r6, [r7, +ip]!");
|
|
|
|
|
|
|
|
|
|
// Test scaled operands for instructions that do not support it natively.
|
|
|
|
|
COMPARE(ldrh(r0, MemOperand(r1, r2, LSL, 2)),
|
|
|
|
|
"e1a00102 mov r0, r2, lsl #2",
|
|
|
|
|
"e19100b0 ldrh r0, [r1, +r0]");
|
|
|
|
|
COMPARE(strh(r3, MemOperand(r4, r5, LSR, 3)),
|
|
|
|
|
"e1a0c1a5 mov ip, r5, lsr #3",
|
|
|
|
|
"e18430bc strh r3, [r4, +ip]");
|
|
|
|
|
// Make sure ip is used if the destination is the same as the base.
|
|
|
|
|
COMPARE(ldrsb(r6, MemOperand(r6, r8, ASR, 4)),
|
|
|
|
|
"e1a0c248 mov ip, r8, asr #4",
|
|
|
|
|
"e19660dc ldrsb r6, [r6, +ip]");
|
|
|
|
|
COMPARE(ldrsh(r9, MemOperand(sp, r10, ROR, 5)),
|
|
|
|
|
"e1a092ea mov r9, r10, ror #5",
|
|
|
|
|
"e19d90f9 ldrsh r9, [sp, +r9]");
|
|
|
|
|
|
2011-05-12 14:44:49 +00:00
|
|
|
VERIFY_RUN();
|
|
|
|
|
}
|
2016-02-17 19:57:18 +00:00
|
|
|
|
|
|
|
|
|
2017-05-15 11:00:16 +00:00
|
|
|
static void TestLoadLiteral(byte* buffer, Assembler* assm, bool* failure,
|
|
|
|
|
int offset) {
|
|
|
|
|
int pc_offset = assm->pc_offset();
|
|
|
|
|
byte *progcounter = &buffer[pc_offset];
|
[arm] Restrict usage of pc-relative LDR.
Disallow using the PC as a base in LDR and instead provide a dedicated assembler
method for pc-relative loads. The reason for this is that the generic
`Assembler::ldr` method may decide to generate more instructions if the offset
is out of range, and if the PC was the base, we would get surprising
results. For example:
~~~
ldr r0, [pc, #0xcabba9e]
~~~
is not equivalent to:
~~~
movw ip, #0xba9e
movt ip, #0xcab
ldr r0, [pc, ip]
~~~
since the reference to the PC has moved down two instructions!
We could teach the assembler to handle those cases correctly, but pc-relative
loads are used in specific cases only so that's not necessary.
As a drive-by, remove a reference to code aging.
Bug:
Change-Id: I586d83a418db52cf28d3b524f889bf40f077998a
Reviewed-on: https://chromium-review.googlesource.com/847008
Reviewed-by: Jaroslav Sevcik <jarin@chromium.org>
Commit-Queue: Pierre Langlois <pierre.langlois@arm.com>
Cr-Commit-Position: refs/heads/master@{#50475}
2018-01-02 18:56:22 +00:00
|
|
|
assm->ldr_pcrel(r0, offset);
|
2017-05-15 11:00:16 +00:00
|
|
|
|
|
|
|
|
const char *expected_string_template =
|
|
|
|
|
(offset >= 0) ?
|
2018-11-08 10:30:30 +00:00
|
|
|
"e59f0%03x ldr r0, [pc, #+%d] (addr 0x%08" PRIxPTR ")" :
|
|
|
|
|
"e51f0%03x ldr r0, [pc, #%d] (addr 0x%08" PRIxPTR ")";
|
2017-05-15 11:00:16 +00:00
|
|
|
char expected_string[80];
|
|
|
|
|
snprintf(expected_string, sizeof(expected_string), expected_string_template,
|
2018-11-08 10:30:30 +00:00
|
|
|
abs(offset), offset,
|
|
|
|
|
reinterpret_cast<uintptr_t>(
|
|
|
|
|
progcounter + Instruction::kPcLoadDelta + offset));
|
2018-04-23 15:44:01 +00:00
|
|
|
if (!DisassembleAndCompare(progcounter, kRawString, expected_string)) {
|
|
|
|
|
*failure = true;
|
|
|
|
|
}
|
2017-05-15 11:00:16 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TEST(LoadLiteral) {
|
|
|
|
|
SET_UP();
|
|
|
|
|
|
|
|
|
|
TestLoadLiteral(buffer, &assm, &failure, 0);
|
|
|
|
|
TestLoadLiteral(buffer, &assm, &failure, 1);
|
|
|
|
|
TestLoadLiteral(buffer, &assm, &failure, 4);
|
|
|
|
|
TestLoadLiteral(buffer, &assm, &failure, 4095);
|
|
|
|
|
TestLoadLiteral(buffer, &assm, &failure, -1);
|
|
|
|
|
TestLoadLiteral(buffer, &assm, &failure, -4);
|
|
|
|
|
TestLoadLiteral(buffer, &assm, &failure, -4095);
|
|
|
|
|
|
|
|
|
|
VERIFY_RUN();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2016-02-17 19:57:18 +00:00
|
|
|
TEST(Barrier) {
|
|
|
|
|
SET_UP();
|
|
|
|
|
|
|
|
|
|
if (CpuFeatures::IsSupported(ARMv7)) {
|
|
|
|
|
CpuFeatureScope scope(&assm, ARMv7);
|
|
|
|
|
|
|
|
|
|
COMPARE(dmb(OSHLD),
|
|
|
|
|
"f57ff051 dmb oshld");
|
|
|
|
|
COMPARE(dmb(OSHST),
|
|
|
|
|
"f57ff052 dmb oshst");
|
|
|
|
|
COMPARE(dmb(OSH),
|
|
|
|
|
"f57ff053 dmb osh");
|
|
|
|
|
COMPARE(dmb(NSHLD),
|
|
|
|
|
"f57ff055 dmb nshld");
|
|
|
|
|
COMPARE(dmb(NSHST),
|
|
|
|
|
"f57ff056 dmb nshst");
|
|
|
|
|
COMPARE(dmb(NSH),
|
|
|
|
|
"f57ff057 dmb nsh");
|
|
|
|
|
COMPARE(dmb(ISHLD),
|
|
|
|
|
"f57ff059 dmb ishld");
|
|
|
|
|
COMPARE(dmb(ISHST),
|
|
|
|
|
"f57ff05a dmb ishst");
|
|
|
|
|
COMPARE(dmb(ISH),
|
|
|
|
|
"f57ff05b dmb ish");
|
|
|
|
|
COMPARE(dmb(LD),
|
|
|
|
|
"f57ff05d dmb ld");
|
|
|
|
|
COMPARE(dmb(ST),
|
|
|
|
|
"f57ff05e dmb st");
|
|
|
|
|
COMPARE(dmb(SY),
|
|
|
|
|
"f57ff05f dmb sy");
|
|
|
|
|
|
|
|
|
|
COMPARE(dsb(ISH),
|
|
|
|
|
"f57ff04b dsb ish");
|
|
|
|
|
|
2016-09-06 11:29:57 +00:00
|
|
|
COMPARE(isb(SY),
|
|
|
|
|
"f57ff06f isb sy");
|
|
|
|
|
} else {
|
|
|
|
|
// ARMv6 uses CP15 to implement barriers. The BarrierOption argument is
|
|
|
|
|
// ignored.
|
|
|
|
|
COMPARE(dmb(ISH),
|
|
|
|
|
"ee070fba mcr (CP15DMB)");
|
|
|
|
|
COMPARE(dsb(OSH),
|
|
|
|
|
"ee070f9a mcr (CP15DSB)");
|
|
|
|
|
COMPARE(isb(SY),
|
|
|
|
|
"ee070f95 mcr (CP15ISB)");
|
2016-02-17 19:57:18 +00:00
|
|
|
}
|
|
|
|
|
|
2016-09-06 11:29:57 +00:00
|
|
|
// ARMv6 barriers.
|
|
|
|
|
// Details available in ARM DDI 0406C.b, B3-1750.
|
|
|
|
|
COMPARE(mcr(p15, 0, r0, cr7, cr10, 5), "ee070fba mcr (CP15DMB)");
|
|
|
|
|
COMPARE(mcr(p15, 0, r0, cr7, cr10, 4), "ee070f9a mcr (CP15DSB)");
|
|
|
|
|
COMPARE(mcr(p15, 0, r0, cr7, cr5, 4), "ee070f95 mcr (CP15ISB)");
|
|
|
|
|
// Rt is ignored.
|
|
|
|
|
COMPARE(mcr(p15, 0, lr, cr7, cr10, 5), "ee07efba mcr (CP15DMB)");
|
|
|
|
|
COMPARE(mcr(p15, 0, lr, cr7, cr10, 4), "ee07ef9a mcr (CP15DSB)");
|
|
|
|
|
COMPARE(mcr(p15, 0, lr, cr7, cr5, 4), "ee07ef95 mcr (CP15ISB)");
|
|
|
|
|
// The mcr instruction can be conditional.
|
|
|
|
|
COMPARE(mcr(p15, 0, r0, cr7, cr10, 5, eq), "0e070fba mcreq (CP15DMB)");
|
|
|
|
|
COMPARE(mcr(p15, 0, r0, cr7, cr10, 4, ne), "1e070f9a mcrne (CP15DSB)");
|
|
|
|
|
COMPARE(mcr(p15, 0, r0, cr7, cr5, 4, mi), "4e070f95 mcrmi (CP15ISB)");
|
|
|
|
|
|
2018-02-21 11:03:02 +00:00
|
|
|
// Conditional speculation barrier.
|
|
|
|
|
COMPARE(csdb(), "e320f014 csdb");
|
|
|
|
|
|
2016-02-17 19:57:18 +00:00
|
|
|
VERIFY_RUN();
|
|
|
|
|
}
|
2016-05-19 19:11:09 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
TEST(LoadStoreExclusive) {
|
|
|
|
|
SET_UP();
|
|
|
|
|
|
|
|
|
|
COMPARE(ldrexb(r0, r1), "e1d10f9f ldrexb r0, [r1]");
|
|
|
|
|
COMPARE(strexb(r0, r1, r2), "e1c20f91 strexb r0, r1, [r2]");
|
|
|
|
|
COMPARE(ldrexh(r0, r1), "e1f10f9f ldrexh r0, [r1]");
|
|
|
|
|
COMPARE(strexh(r0, r1, r2), "e1e20f91 strexh r0, r1, [r2]");
|
|
|
|
|
COMPARE(ldrex(r0, r1), "e1910f9f ldrex r0, [r1]");
|
|
|
|
|
COMPARE(strex(r0, r1, r2), "e1820f91 strex r0, r1, [r2]");
|
2018-08-25 01:32:25 +00:00
|
|
|
COMPARE(ldrexd(r0, r1, r2), "e1b20f9f ldrexd r0, [r2]");
|
|
|
|
|
COMPARE(strexd(r0, r2, r3, r4),
|
2018-08-20 17:01:34 +00:00
|
|
|
"e1a40f92 strexd r0, r2, [r4]");
|
2016-05-19 19:11:09 +00:00
|
|
|
|
|
|
|
|
VERIFY_RUN();
|
|
|
|
|
}
|
2017-08-31 12:34:55 +00:00
|
|
|
|
[arm] Support splitting add with immediate instructions
When an immediate does not fit an add instruction we use a temporary register to
hold the value, using movw/movt to encode it. However, in order to remove a use
of r9 in TurboFan's code generator, we need to cope with no scratch registers
being available. That is to say that the destination and source registers are
the same, and `ip` is not available to use.
In this case, we can split an add instruction into a sequence of additions:
```
UseScratchRegisterScope temps(...);
Register my_scratch = temps.Acquire();
__ add(r0, r0, Operand(0xabcd); // add r0, r0, #0xcd
// add r0, r0, #0xab00
```
As a drive-by fix, make the disassembler test fail if we expected a different
number of instructions generated.
Bug: v8:6553
Change-Id: Ib7fcc765d28bccafe39257f47cd73f922c5873bf
Reviewed-on: https://chromium-review.googlesource.com/685014
Reviewed-by: Benedikt Meurer <bmeurer@chromium.org>
Commit-Queue: Pierre Langlois <pierre.langlois@arm.com>
Cr-Commit-Position: refs/heads/master@{#48491}
2017-10-11 12:00:21 +00:00
|
|
|
TEST(SplitAddImmediate) {
|
|
|
|
|
SET_UP();
|
|
|
|
|
|
2018-04-23 15:44:01 +00:00
|
|
|
if (CpuFeatures::IsSupported(ARMv7)) {
|
|
|
|
|
// Re-use the destination as a scratch.
|
|
|
|
|
COMPARE(add(r0, r1, Operand(0x12345678)),
|
|
|
|
|
"e3050678 movw r0, #22136",
|
|
|
|
|
"e3410234 movt r0, #4660",
|
|
|
|
|
"e0810000 add r0, r1, r0");
|
|
|
|
|
|
|
|
|
|
// Use ip as a scratch.
|
|
|
|
|
COMPARE(add(r0, r0, Operand(0x12345678)),
|
|
|
|
|
"e305c678 movw ip, #22136",
|
|
|
|
|
"e341c234 movt ip, #4660",
|
|
|
|
|
"e080000c add r0, r0, ip");
|
|
|
|
|
} else {
|
|
|
|
|
// Re-use the destination as a scratch.
|
|
|
|
|
COMPARE_REGEX(add(r0, r1, Operand(0x12345678)),
|
|
|
|
|
"e59f0[0-9a-f]{3} "
|
|
|
|
|
"ldr r0, \\[pc, #\\+[0-9]+\\] \\(addr 0x[0-9a-f]{8}\\)",
|
|
|
|
|
"e0810000 add r0, r1, r0");
|
|
|
|
|
|
|
|
|
|
// Use ip as a scratch.
|
|
|
|
|
COMPARE_REGEX(add(r0, r0, Operand(0x12345678)),
|
|
|
|
|
"e59fc[0-9a-f]{3} "
|
|
|
|
|
"ldr ip, \\[pc, #\\+[0-9]+\\] \\(addr 0x[0-9a-f]{8}\\)",
|
|
|
|
|
"e080000c add r0, r0, ip");
|
|
|
|
|
}
|
[arm] Support splitting add with immediate instructions
When an immediate does not fit an add instruction we use a temporary register to
hold the value, using movw/movt to encode it. However, in order to remove a use
of r9 in TurboFan's code generator, we need to cope with no scratch registers
being available. That is to say that the destination and source registers are
the same, and `ip` is not available to use.
In this case, we can split an add instruction into a sequence of additions:
```
UseScratchRegisterScope temps(...);
Register my_scratch = temps.Acquire();
__ add(r0, r0, Operand(0xabcd); // add r0, r0, #0xcd
// add r0, r0, #0xab00
```
As a drive-by fix, make the disassembler test fail if we expected a different
number of instructions generated.
Bug: v8:6553
Change-Id: Ib7fcc765d28bccafe39257f47cd73f922c5873bf
Reviewed-on: https://chromium-review.googlesource.com/685014
Reviewed-by: Benedikt Meurer <bmeurer@chromium.org>
Commit-Queue: Pierre Langlois <pierre.langlois@arm.com>
Cr-Commit-Position: refs/heads/master@{#48491}
2017-10-11 12:00:21 +00:00
|
|
|
|
|
|
|
|
// If ip is not available, split the operation into multiple additions.
|
|
|
|
|
{
|
|
|
|
|
UseScratchRegisterScope temps(&assm);
|
|
|
|
|
Register reserved = temps.Acquire();
|
|
|
|
|
USE(reserved);
|
|
|
|
|
COMPARE(add(r2, r2, Operand(0x12345678)),
|
|
|
|
|
"e2822f9e add r2, r2, #632",
|
|
|
|
|
"e2822b15 add r2, r2, #21504",
|
|
|
|
|
"e282278d add r2, r2, #36962304",
|
|
|
|
|
"e2822201 add r2, r2, #268435456");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
VERIFY_RUN();
|
|
|
|
|
}
|
|
|
|
|
|
2017-08-31 12:34:55 +00:00
|
|
|
} // namespace internal
|
|
|
|
|
} // namespace v8
|
