2009-05-06 12:08:50 +00:00
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// Copyright (c) 1994-2006 Sun Microsystems Inc.
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// All Rights Reserved.
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//
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2009-05-04 07:16:10 +00:00
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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2009-05-06 12:08:50 +00:00
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// - Redistribution in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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2009-05-04 07:16:10 +00:00
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//
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2009-05-06 12:08:50 +00:00
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// - Neither the name of Sun Microsystems or the names of contributors may
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// be used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// The original source code covered by the above license above has been
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// modified significantly by Google Inc.
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// Copyright 2006-2009 the V8 project authors. All rights reserved.
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// A lightweight X64 Assembler.
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2009-05-04 07:16:10 +00:00
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2009-05-05 14:39:05 +00:00
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#ifndef V8_X64_ASSEMBLER_X64_H_
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#define V8_X64_ASSEMBLER_X64_H_
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2009-05-25 10:05:56 +00:00
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namespace v8 {
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namespace internal {
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2009-05-05 14:39:05 +00:00
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2009-05-06 12:08:50 +00:00
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// CPU Registers.
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//
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// 1) We would prefer to use an enum, but enum values are assignment-
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// compatible with int, which has caused code-generation bugs.
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//
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// 2) We would prefer to use a class instead of a struct but we don't like
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// the register initialization to depend on the particular initialization
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// order (which appears to be different on OS X, Linux, and Windows for the
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// installed versions of C++ we tried). Using a struct permits C-style
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// "initialization". Also, the Register objects cannot be const as this
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// forces initialization stubs in MSVC, making us dependent on initialization
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// order.
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//
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// 3) By not using an enum, we are possibly preventing the compiler from
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// doing certain constant folds, which may significantly reduce the
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// code generated for some assembly instructions (because they boil down
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// to a few constants). If this is a problem, we could change the code
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// such that we use an enum in optimized mode, and the struct in debug
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// mode. This way we get the compile-time error checking in debug mode
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// and best performance in optimized code.
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//
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2009-05-05 14:39:05 +00:00
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struct Register {
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2009-05-28 09:18:17 +00:00
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static Register toRegister(int code) {
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Register r = {code};
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return r;
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}
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2009-05-27 07:53:47 +00:00
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bool is_valid() const { return 0 <= code_ && code_ < 16; }
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2009-05-05 14:39:05 +00:00
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bool is(Register reg) const { return code_ == reg.code_; }
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2009-05-06 12:08:50 +00:00
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// The byte-register distinction of ai32 has dissapeared.
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bool is_byte_register() const { return false; }
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2009-05-05 14:39:05 +00:00
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int code() const {
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ASSERT(is_valid());
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return code_;
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}
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int bit() const {
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2009-05-06 12:08:50 +00:00
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UNIMPLEMENTED();
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return 0;
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2009-05-05 14:39:05 +00:00
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}
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// (unfortunately we can't make this private in a struct)
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int code_;
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};
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2009-05-06 12:08:50 +00:00
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extern Register rax;
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extern Register rcx;
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extern Register rdx;
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extern Register rbx;
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extern Register rsp;
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extern Register rbp;
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extern Register rsi;
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extern Register rdi;
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extern Register r8;
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extern Register r9;
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extern Register r10;
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extern Register r11;
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extern Register r12;
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extern Register r13;
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extern Register r14;
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extern Register r15;
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2009-05-05 14:39:05 +00:00
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extern Register no_reg;
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2009-05-06 12:08:50 +00:00
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struct XMMRegister {
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bool is_valid() const { return 0 <= code_ && code_ < 2; }
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int code() const {
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ASSERT(is_valid());
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return code_;
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}
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int code_;
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};
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extern XMMRegister xmm0;
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extern XMMRegister xmm1;
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extern XMMRegister xmm2;
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extern XMMRegister xmm3;
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extern XMMRegister xmm4;
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extern XMMRegister xmm5;
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extern XMMRegister xmm6;
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extern XMMRegister xmm7;
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2009-05-26 07:58:36 +00:00
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extern XMMRegister xmm8;
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extern XMMRegister xmm9;
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extern XMMRegister xmm10;
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extern XMMRegister xmm11;
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extern XMMRegister xmm12;
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extern XMMRegister xmm13;
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extern XMMRegister xmm14;
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extern XMMRegister xmm15;
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2009-05-06 12:08:50 +00:00
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2009-05-05 14:39:05 +00:00
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enum Condition {
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// any value < 0 is considered no_condition
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no_condition = -1,
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overflow = 0,
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no_overflow = 1,
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below = 2,
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above_equal = 3,
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equal = 4,
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not_equal = 5,
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below_equal = 6,
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above = 7,
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negative = 8,
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positive = 9,
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parity_even = 10,
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parity_odd = 11,
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less = 12,
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greater_equal = 13,
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less_equal = 14,
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greater = 15,
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// aliases
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carry = below,
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not_carry = above_equal,
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zero = equal,
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not_zero = not_equal,
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sign = negative,
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not_sign = positive
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};
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2009-05-06 12:08:50 +00:00
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// Returns the equivalent of !cc.
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// Negation of the default no_condition (-1) results in a non-default
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// no_condition value (-2). As long as tests for no_condition check
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// for condition < 0, this will work as expected.
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inline Condition NegateCondition(Condition cc);
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// Corresponds to transposing the operands of a comparison.
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inline Condition ReverseCondition(Condition cc) {
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switch (cc) {
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case below:
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return above;
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case above:
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return below;
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case above_equal:
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return below_equal;
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case below_equal:
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return above_equal;
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case less:
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return greater;
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case greater:
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return less;
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case greater_equal:
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return less_equal;
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case less_equal:
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return greater_equal;
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default:
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return cc;
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};
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}
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2009-05-05 14:39:05 +00:00
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enum Hint {
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no_hint = 0,
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not_taken = 0x2e,
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taken = 0x3e
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};
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2009-05-06 12:08:50 +00:00
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// The result of negating a hint is as if the corresponding condition
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// were negated by NegateCondition. That is, no_hint is mapped to
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// itself and not_taken and taken are mapped to each other.
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inline Hint NegateHint(Hint hint) {
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return (hint == no_hint)
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? no_hint
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: ((hint == not_taken) ? taken : not_taken);
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}
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// -----------------------------------------------------------------------------
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// Machine instruction Immediates
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class Immediate BASE_EMBEDDED {
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public:
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2009-05-28 09:18:17 +00:00
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explicit Immediate(int32_t value) : value_(value) {}
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2009-05-06 12:08:50 +00:00
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inline explicit Immediate(Smi* value);
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private:
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2009-05-28 09:18:17 +00:00
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int32_t value_;
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2009-05-06 12:08:50 +00:00
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friend class Assembler;
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};
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// -----------------------------------------------------------------------------
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// Machine instruction Operands
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enum ScaleFactor {
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times_1 = 0,
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times_2 = 1,
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times_4 = 2,
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times_8 = 3
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};
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class Operand BASE_EMBEDDED {
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public:
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// [base + disp/r]
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2009-05-27 08:15:31 +00:00
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INLINE(Operand(Register base, int32_t disp));
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2009-05-06 12:08:50 +00:00
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// [base + index*scale + disp/r]
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2009-05-27 08:15:31 +00:00
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Operand(Register base,
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Register index,
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ScaleFactor scale,
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int32_t disp);
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2009-05-06 12:08:50 +00:00
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// [index*scale + disp/r]
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2009-05-27 08:15:31 +00:00
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Operand(Register index,
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ScaleFactor scale,
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int32_t disp);
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2009-05-06 12:08:50 +00:00
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private:
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byte rex_;
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byte buf_[10];
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// The number of bytes in buf_.
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unsigned int len_;
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RelocInfo::Mode rmode_;
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// Set the ModRM byte without an encoded 'reg' register. The
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// register is encoded later as part of the emit_operand operation.
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2009-05-27 08:15:31 +00:00
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// set_modrm can be called before or after set_sib and set_disp*.
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2009-05-06 12:08:50 +00:00
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inline void set_modrm(int mod, Register rm);
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2009-05-27 08:15:31 +00:00
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// Set the SIB byte if one is needed. Sets the length to 2 rather than 1.
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2009-05-06 12:08:50 +00:00
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inline void set_sib(ScaleFactor scale, Register index, Register base);
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2009-05-27 08:15:31 +00:00
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// Adds operand displacement fields (offsets added to the memory address).
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// Needs to be called after set_sib, not before it.
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inline void set_disp8(int disp);
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inline void set_disp32(int disp);
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2009-05-06 12:08:50 +00:00
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2009-05-27 08:15:31 +00:00
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friend class Assembler;
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2009-05-06 12:08:50 +00:00
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};
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// CpuFeatures keeps track of which features are supported by the target CPU.
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// Supported features must be enabled by a Scope before use.
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// Example:
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// if (CpuFeatures::IsSupported(SSE2)) {
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// CpuFeatures::Scope fscope(SSE2);
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// // Generate SSE2 floating point code.
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// } else {
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// // Generate standard x87 floating point code.
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// }
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class CpuFeatures : public AllStatic {
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public:
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// Feature flags bit positions. They are mostly based on the CPUID spec.
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// (We assign CPUID itself to one of the currently reserved bits --
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// feel free to change this if needed.)
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enum Feature { SSE3 = 32, SSE2 = 26, CMOV = 15, RDTSC = 4, CPUID = 10 };
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// Detect features of the target CPU. Set safe defaults if the serializer
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// is enabled (snapshots must be portable).
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static void Probe();
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// Check whether a feature is supported by the target CPU.
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static bool IsSupported(Feature f) {
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return (supported_ & (static_cast<uint64_t>(1) << f)) != 0;
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}
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// Check whether a feature is currently enabled.
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static bool IsEnabled(Feature f) {
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return (enabled_ & (static_cast<uint64_t>(1) << f)) != 0;
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}
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// Enable a specified feature within a scope.
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class Scope BASE_EMBEDDED {
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#ifdef DEBUG
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public:
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explicit Scope(Feature f) {
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ASSERT(CpuFeatures::IsSupported(f));
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old_enabled_ = CpuFeatures::enabled_;
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CpuFeatures::enabled_ |= (static_cast<uint64_t>(1) << f);
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}
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~Scope() { CpuFeatures::enabled_ = old_enabled_; }
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private:
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uint64_t old_enabled_;
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#else
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public:
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explicit Scope(Feature f) {}
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#endif
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};
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private:
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static uint64_t supported_;
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static uint64_t enabled_;
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};
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class Assembler : public Malloced {
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private:
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// The relocation writer's position is kGap bytes below the end of
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// the generated instructions. This leaves enough space for the
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2009-05-25 14:00:30 +00:00
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// longest possible x64 instruction (There is a 15 byte limit on
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// instruction length, ruling out some otherwise valid instructions) and
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2009-05-06 12:08:50 +00:00
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// allows for a single, fast space check per instruction.
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static const int kGap = 32;
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public:
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// Create an assembler. Instructions and relocation information are emitted
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// into a buffer, with the instructions starting from the beginning and the
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// relocation information starting from the end of the buffer. See CodeDesc
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// for a detailed comment on the layout (globals.h).
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//
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// If the provided buffer is NULL, the assembler allocates and grows its own
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// buffer, and buffer_size determines the initial buffer size. The buffer is
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// owned by the assembler and deallocated upon destruction of the assembler.
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//
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// If the provided buffer is not NULL, the assembler uses the provided buffer
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// for code generation and assumes its size to be buffer_size. If the buffer
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// is too small, a fatal error occurs. No deallocation of the buffer is done
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// upon destruction of the assembler.
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Assembler(void* buffer, int buffer_size);
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~Assembler();
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// GetCode emits any pending (non-emitted) code and fills the descriptor
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// desc. GetCode() is idempotent; it returns the same result if no other
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// Assembler functions are invoked in between GetCode() calls.
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void GetCode(CodeDesc* desc);
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|
|
// Read/Modify the code target in the branch/call instruction at pc.
|
|
|
|
inline static Address target_address_at(Address pc);
|
|
|
|
inline static void set_target_address_at(Address pc, Address target);
|
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|
|
// Distance between the address of the code target in the call instruction
|
|
|
|
// and the return address
|
|
|
|
static const int kTargetAddrToReturnAddrDist = kPointerSize;
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|
|
// ---------------------------------------------------------------------------
|
|
|
|
// Code generation
|
|
|
|
//
|
2009-05-25 14:00:30 +00:00
|
|
|
// Function names correspond one-to-one to x64 instruction mnemonics.
|
|
|
|
// Unless specified otherwise, instructions operate on 64-bit operands.
|
|
|
|
//
|
|
|
|
// If we need versions of an assembly instruction that operate on different
|
|
|
|
// width arguments, we add a single-letter suffix specifying the width.
|
|
|
|
// This is done for the following instructions: mov, cmp.
|
|
|
|
// There are no versions of these instructions without the suffix.
|
|
|
|
// - Instructions on 8-bit (byte) operands/registers have a trailing 'b'.
|
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|
|
// - Instructions on 16-bit (word) operands/registers have a trailing 'w'.
|
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|
|
// - Instructions on 32-bit (doubleword) operands/registers use 'l'.
|
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|
|
// - Instructions on 64-bit (quadword) operands/registers use 'q'.
|
|
|
|
//
|
|
|
|
// Some mnemonics, such as "and", are the same as C++ keywords.
|
|
|
|
// Naming conflicts with C++ keywords are resolved by adding a trailing '_'.
|
2009-05-06 12:08:50 +00:00
|
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|
|
|
|
|
// Insert the smallest number of nop instructions
|
|
|
|
// possible to align the pc offset to a multiple
|
|
|
|
// of m. m must be a power of 2.
|
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|
|
void Align(int m);
|
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|
|
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|
|
|
// Stack
|
|
|
|
void pushad();
|
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|
|
void popad();
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|
|
void pushfd();
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|
|
void popfd();
|
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|
|
void push(const Immediate& x);
|
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|
|
void push(Register src);
|
|
|
|
void push(const Operand& src);
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|
|
void push(Label* label, RelocInfo::Mode relocation_mode);
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|
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|
|
void pop(Register dst);
|
|
|
|
void pop(const Operand& dst);
|
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|
|
|
|
|
|
void enter(const Immediate& size);
|
|
|
|
void leave();
|
|
|
|
|
|
|
|
// Moves
|
2009-05-28 09:18:17 +00:00
|
|
|
void movb(Register dst, const Operand& src);
|
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|
|
void movb(const Operand& dst, int8_t imm8);
|
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|
|
void movb(const Operand& dst, Register src);
|
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|
|
void movq(Register dst, int32_t imm32);
|
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|
|
void movq(Register dst, Immediate x);
|
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|
|
void movq(Register dst, const Operand& src);
|
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|
|
void movq(Register dst, Register src);
|
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|
|
void movq(const Operand& dst, const Immediate& x);
|
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|
|
void movq(const Operand& dst, Register src);
|
|
|
|
|
|
|
|
// New x64 instructions to load a 64-bit immediate into a register.
|
|
|
|
// All 64-bit immediates must have a relocation mode.
|
|
|
|
void movq(Register dst, void* ptr, RelocInfo::Mode rmode);
|
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|
|
void movq(Register dst, int64_t value, RelocInfo::Mode rmode);
|
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|
|
void movq(Register dst, const char* s, RelocInfo::Mode rmode);
|
|
|
|
void movq(Register dst, const ExternalReference& ext, RelocInfo::Mode rmode);
|
|
|
|
void movq(Register dst, Handle<Object> handle, RelocInfo::Mode rmode);
|
|
|
|
|
|
|
|
// New x64 instruction to load from an immediate 64-bit pointer into RAX.
|
|
|
|
void load_rax(void* ptr, RelocInfo::Mode rmode);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
void movsx_b(Register dst, const Operand& src);
|
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|
|
|
|
|
|
void movsx_w(Register dst, const Operand& src);
|
|
|
|
|
|
|
|
void movzx_b(Register dst, const Operand& src);
|
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|
|
void movzx_w(Register dst, const Operand& src);
|
|
|
|
|
|
|
|
// Conditional moves
|
|
|
|
void cmov(Condition cc, Register dst, int32_t imm32);
|
|
|
|
void cmov(Condition cc, Register dst, Handle<Object> handle);
|
|
|
|
void cmov(Condition cc, Register dst, const Operand& src);
|
|
|
|
|
|
|
|
// Exchange two registers
|
|
|
|
void xchg(Register dst, Register src);
|
|
|
|
|
|
|
|
// Arithmetics
|
2009-05-28 09:18:17 +00:00
|
|
|
void add(Register dst, Register src) {
|
|
|
|
arithmetic_op(0x03, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void add(Register dst, const Operand& src) {
|
|
|
|
arithmetic_op(0x03, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-05-28 10:06:48 +00:00
|
|
|
|
2009-05-28 09:18:17 +00:00
|
|
|
void add(const Operand& dst, Register src) {
|
|
|
|
arithmetic_op(0x01, src, dst);
|
|
|
|
}
|
|
|
|
|
|
|
|
void add(Register dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op(0x0, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void add(const Operand& dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op(0x0, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cmp(Register dst, Register src) {
|
|
|
|
arithmetic_op(0x3B, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cmp(Register dst, const Operand& src) {
|
|
|
|
arithmetic_op(0x3B, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cmp(const Operand& dst, Register src) {
|
|
|
|
arithmetic_op(0x39, src, dst);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cmp(Register dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op(0x7, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cmp(const Operand& dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op(0x7, dst, src);
|
|
|
|
}
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-05-28 10:06:48 +00:00
|
|
|
void and_(Register dst, Register src) {
|
|
|
|
arithmetic_op(0x23, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void and_(Register dst, const Operand& src) {
|
|
|
|
arithmetic_op(0x23, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void and_(const Operand& dst, Register src) {
|
|
|
|
arithmetic_op(0x21, src, dst);
|
|
|
|
}
|
|
|
|
|
|
|
|
void and_(Register dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op(0x4, dst, src);
|
|
|
|
}
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-05-28 10:06:48 +00:00
|
|
|
void and_(const Operand& dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op(0x4, dst, src);
|
|
|
|
}
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
void cmpb(const Operand& op, int8_t imm8);
|
|
|
|
void cmpb_al(const Operand& op);
|
|
|
|
void cmpw_ax(const Operand& op);
|
|
|
|
void cmpw(const Operand& op, Immediate imm16);
|
|
|
|
|
|
|
|
void dec_b(Register dst);
|
|
|
|
|
|
|
|
void dec(Register dst);
|
|
|
|
void dec(const Operand& dst);
|
|
|
|
|
|
|
|
void cdq();
|
|
|
|
|
|
|
|
void idiv(Register src);
|
|
|
|
|
|
|
|
void imul(Register dst, const Operand& src);
|
|
|
|
void imul(Register dst, Register src, int32_t imm32);
|
|
|
|
|
|
|
|
void inc(Register dst);
|
|
|
|
void inc(const Operand& dst);
|
|
|
|
|
|
|
|
void lea(Register dst, const Operand& src);
|
|
|
|
|
|
|
|
void mul(Register src);
|
|
|
|
|
|
|
|
void neg(Register dst);
|
|
|
|
|
|
|
|
void not_(Register dst);
|
|
|
|
|
2009-05-28 10:06:48 +00:00
|
|
|
void or_(Register dst, Register src) {
|
|
|
|
arithmetic_op(0x0B, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void or_(Register dst, const Operand& src) {
|
|
|
|
arithmetic_op(0x0B, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void or_(const Operand& dst, Register src) {
|
|
|
|
arithmetic_op(0x09, src, dst);
|
|
|
|
}
|
|
|
|
|
|
|
|
void or_(Register dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op(0x1, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void or_(const Operand& dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op(0x1, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
void rcl(Register dst, uint8_t imm8);
|
|
|
|
|
|
|
|
void sar(Register dst, uint8_t imm8);
|
|
|
|
void sar(Register dst);
|
|
|
|
|
|
|
|
void sbb(Register dst, const Operand& src);
|
|
|
|
|
|
|
|
void shld(Register dst, const Operand& src);
|
|
|
|
|
|
|
|
void shl(Register dst, uint8_t imm8);
|
|
|
|
void shl(Register dst);
|
|
|
|
|
|
|
|
void shrd(Register dst, const Operand& src);
|
|
|
|
|
|
|
|
void shr(Register dst, uint8_t imm8);
|
|
|
|
void shr(Register dst);
|
|
|
|
void shr_cl(Register dst);
|
|
|
|
|
2009-05-28 10:06:48 +00:00
|
|
|
void sub(Register dst, Register src) {
|
|
|
|
arithmetic_op(0x2B, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void sub(Register dst, const Operand& src) {
|
|
|
|
arithmetic_op(0x2B, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void sub(const Operand& dst, Register src) {
|
|
|
|
arithmetic_op(0x29, src, dst);
|
|
|
|
}
|
|
|
|
|
|
|
|
void sub(Register dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op(0x5, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void sub(const Operand& dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op(0x5, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
void test(Register reg, const Immediate& imm);
|
|
|
|
void test(Register reg, const Operand& op);
|
|
|
|
void test(const Operand& op, const Immediate& imm);
|
|
|
|
|
2009-05-28 10:06:48 +00:00
|
|
|
void xor_(Register dst, Register src) {
|
|
|
|
arithmetic_op(0x33, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void xor_(Register dst, const Operand& src) {
|
|
|
|
arithmetic_op(0x33, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void xor_(const Operand& dst, Register src) {
|
|
|
|
arithmetic_op(0x31, src, dst);
|
|
|
|
}
|
|
|
|
|
|
|
|
void xor_(Register dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op(0x6, dst, src);
|
|
|
|
}
|
|
|
|
|
|
|
|
void xor_(const Operand& dst, Immediate src) {
|
|
|
|
immediate_arithmetic_op(0x6, dst, src);
|
|
|
|
}
|
|
|
|
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
// Bit operations.
|
|
|
|
void bt(const Operand& dst, Register src);
|
|
|
|
void bts(const Operand& dst, Register src);
|
|
|
|
|
|
|
|
// Miscellaneous
|
|
|
|
void hlt();
|
|
|
|
void int3();
|
|
|
|
void nop();
|
|
|
|
void rdtsc();
|
|
|
|
void ret(int imm16);
|
|
|
|
|
|
|
|
// Label operations & relative jumps (PPUM Appendix D)
|
|
|
|
//
|
|
|
|
// Takes a branch opcode (cc) and a label (L) and generates
|
|
|
|
// either a backward branch or a forward branch and links it
|
|
|
|
// to the label fixup chain. Usage:
|
|
|
|
//
|
|
|
|
// Label L; // unbound label
|
|
|
|
// j(cc, &L); // forward branch to unbound label
|
|
|
|
// bind(&L); // bind label to the current pc
|
|
|
|
// j(cc, &L); // backward branch to bound label
|
|
|
|
// bind(&L); // illegal: a label may be bound only once
|
|
|
|
//
|
|
|
|
// Note: The same Label can be used for forward and backward branches
|
|
|
|
// but it may be bound only once.
|
|
|
|
|
|
|
|
void bind(Label* L); // binds an unbound label L to the current code position
|
|
|
|
|
|
|
|
// Calls
|
|
|
|
void call(Label* L);
|
|
|
|
void call(byte* entry, RelocInfo::Mode rmode);
|
|
|
|
void call(const Operand& adr);
|
|
|
|
void call(Handle<Code> code, RelocInfo::Mode rmode);
|
|
|
|
|
|
|
|
// Jumps
|
|
|
|
void jmp(Label* L); // unconditional jump to L
|
|
|
|
void jmp(byte* entry, RelocInfo::Mode rmode);
|
|
|
|
void jmp(const Operand& adr);
|
|
|
|
void jmp(Handle<Code> code, RelocInfo::Mode rmode);
|
|
|
|
|
|
|
|
// Conditional jumps
|
2009-05-26 12:32:09 +00:00
|
|
|
void j(Condition cc, Label* L);
|
|
|
|
void j(Condition cc, byte* entry, RelocInfo::Mode rmode);
|
|
|
|
void j(Condition cc, Handle<Code> code);
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
// Floating-point operations
|
|
|
|
void fld(int i);
|
|
|
|
|
|
|
|
void fld1();
|
|
|
|
void fldz();
|
|
|
|
|
|
|
|
void fld_s(const Operand& adr);
|
|
|
|
void fld_d(const Operand& adr);
|
|
|
|
|
|
|
|
void fstp_s(const Operand& adr);
|
|
|
|
void fstp_d(const Operand& adr);
|
|
|
|
|
|
|
|
void fild_s(const Operand& adr);
|
|
|
|
void fild_d(const Operand& adr);
|
|
|
|
|
|
|
|
void fist_s(const Operand& adr);
|
|
|
|
|
|
|
|
void fistp_s(const Operand& adr);
|
|
|
|
void fistp_d(const Operand& adr);
|
|
|
|
|
|
|
|
void fisttp_s(const Operand& adr);
|
|
|
|
|
|
|
|
void fabs();
|
|
|
|
void fchs();
|
|
|
|
|
|
|
|
void fadd(int i);
|
|
|
|
void fsub(int i);
|
|
|
|
void fmul(int i);
|
|
|
|
void fdiv(int i);
|
|
|
|
|
|
|
|
void fisub_s(const Operand& adr);
|
|
|
|
|
|
|
|
void faddp(int i = 1);
|
|
|
|
void fsubp(int i = 1);
|
|
|
|
void fsubrp(int i = 1);
|
|
|
|
void fmulp(int i = 1);
|
|
|
|
void fdivp(int i = 1);
|
|
|
|
void fprem();
|
|
|
|
void fprem1();
|
|
|
|
|
|
|
|
void fxch(int i = 1);
|
|
|
|
void fincstp();
|
|
|
|
void ffree(int i = 0);
|
|
|
|
|
|
|
|
void ftst();
|
|
|
|
void fucomp(int i);
|
|
|
|
void fucompp();
|
|
|
|
void fcompp();
|
|
|
|
void fnstsw_ax();
|
|
|
|
void fwait();
|
|
|
|
void fnclex();
|
|
|
|
|
|
|
|
void frndint();
|
|
|
|
|
|
|
|
void sahf();
|
|
|
|
void setcc(Condition cc, Register reg);
|
|
|
|
|
|
|
|
void cpuid();
|
|
|
|
|
|
|
|
// SSE2 instructions
|
|
|
|
void cvttss2si(Register dst, const Operand& src);
|
|
|
|
void cvttsd2si(Register dst, const Operand& src);
|
|
|
|
|
|
|
|
void cvtsi2sd(XMMRegister dst, const Operand& src);
|
|
|
|
|
|
|
|
void addsd(XMMRegister dst, XMMRegister src);
|
|
|
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void subsd(XMMRegister dst, XMMRegister src);
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|
void mulsd(XMMRegister dst, XMMRegister src);
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void divsd(XMMRegister dst, XMMRegister src);
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// Use either movsd or movlpd.
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void movdbl(XMMRegister dst, const Operand& src);
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void movdbl(const Operand& dst, XMMRegister src);
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|
// Debugging
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void Print();
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// Check the code size generated from label to here.
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int SizeOfCodeGeneratedSince(Label* l) { return pc_offset() - l->pos(); }
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// Mark address of the ExitJSFrame code.
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void RecordJSReturn();
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// Record a comment relocation entry that can be used by a disassembler.
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// Use --debug_code to enable.
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void RecordComment(const char* msg);
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void RecordPosition(int pos);
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void RecordStatementPosition(int pos);
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void WriteRecordedPositions();
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// Writes a single word of data in the code stream.
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// Used for inline tables, e.g., jump-tables.
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void dd(uint32_t data, RelocInfo::Mode reloc_info);
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// Writes the absolute address of a bound label at the given position in
|
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// the generated code. That positions should have the relocation mode
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// internal_reference!
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void WriteInternalReference(int position, const Label& bound_label);
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int pc_offset() const { return pc_ - buffer_; }
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int current_statement_position() const { return current_statement_position_; }
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int current_position() const { return current_position_; }
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|
// Check if there is less than kGap bytes available in the buffer.
|
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|
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// If this is the case, we need to grow the buffer before emitting
|
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|
// an instruction or relocation information.
|
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|
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inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; }
|
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// Get the number of bytes available in the buffer.
|
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|
|
inline int available_space() const { return reloc_info_writer.pos() - pc_; }
|
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|
// Avoid overflows for displacements etc.
|
|
|
|
static const int kMaximalBufferSize = 512*MB;
|
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|
|
static const int kMinimalBufferSize = 4*KB;
|
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|
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|
|
protected:
|
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|
void movsd(XMMRegister dst, const Operand& src);
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|
void movsd(const Operand& dst, XMMRegister src);
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|
|
void emit_sse_operand(XMMRegister reg, const Operand& adr);
|
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|
|
void emit_sse_operand(XMMRegister dst, XMMRegister src);
|
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|
|
private:
|
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|
|
byte* addr_at(int pos) { return buffer_ + pos; }
|
|
|
|
byte byte_at(int pos) { return buffer_[pos]; }
|
|
|
|
uint32_t long_at(int pos) {
|
|
|
|
return *reinterpret_cast<uint32_t*>(addr_at(pos));
|
|
|
|
}
|
|
|
|
void long_at_put(int pos, uint32_t x) {
|
|
|
|
*reinterpret_cast<uint32_t*>(addr_at(pos)) = x;
|
|
|
|
}
|
|
|
|
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|
|
// code emission
|
|
|
|
void GrowBuffer();
|
2009-05-28 10:06:48 +00:00
|
|
|
|
|
|
|
void emit(byte x) { *pc_++ = x; }
|
2009-05-28 09:18:17 +00:00
|
|
|
inline void emitl(uint32_t x);
|
2009-05-06 12:08:50 +00:00
|
|
|
inline void emit(Handle<Object> handle);
|
2009-05-28 09:18:17 +00:00
|
|
|
inline void emitq(uint64_t x, RelocInfo::Mode rmode);
|
|
|
|
void emit(Immediate x) { emitl(x.value_); }
|
2009-05-06 12:08:50 +00:00
|
|
|
|
2009-05-22 07:53:28 +00:00
|
|
|
// Emits a REX prefix that encodes a 64-bit operand size and
|
|
|
|
// the top bit of both register codes.
|
2009-05-28 09:18:17 +00:00
|
|
|
// High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
|
|
|
|
// REX.W is set.
|
2009-05-22 07:53:28 +00:00
|
|
|
inline void emit_rex_64(Register reg, Register rm_reg);
|
|
|
|
|
|
|
|
// Emits a REX prefix that encodes a 64-bit operand size and
|
|
|
|
// the top bit of the destination, index, and base register codes.
|
2009-05-28 09:18:17 +00:00
|
|
|
// The high bit of reg is used for REX.R, the high bit of op's base
|
|
|
|
// register is used for REX.B, and the high bit of op's index register
|
|
|
|
// is used for REX.X. REX.W is set.
|
2009-05-22 07:53:28 +00:00
|
|
|
inline void emit_rex_64(Register reg, const Operand& op);
|
|
|
|
|
2009-05-28 10:06:48 +00:00
|
|
|
// Emit the Mod/RM byte, and optionally the SIB byte and
|
|
|
|
// 1- or 4-byte offset for a memory operand. Also encodes
|
|
|
|
// the second operand of the operation, a register, into the Mod/RM byte.
|
|
|
|
void emit_operand(Register reg, const Operand& adr);
|
|
|
|
|
2009-05-06 12:08:50 +00:00
|
|
|
// Emit the code-object-relative offset of the label's position
|
|
|
|
inline void emit_code_relative_offset(Label* label);
|
|
|
|
|
2009-05-28 10:06:48 +00:00
|
|
|
// Emit machine code for one of the operations ADD, ADC, SUB, SBC,
|
|
|
|
// AND, OR, XOR, or CMP. The encodings of these operations are all
|
|
|
|
// similar, differing just in the opcode or in the reg field of the
|
|
|
|
// Mod/RM byte.
|
2009-05-28 09:18:17 +00:00
|
|
|
void arithmetic_op(byte opcode, Register dst, Register src);
|
|
|
|
void arithmetic_op(byte opcode, Register reg, const Operand& op);
|
|
|
|
void immediate_arithmetic_op(byte subcode, Register dst, Immediate src);
|
|
|
|
void immediate_arithmetic_op(byte subcode, const Operand& dst, Immediate src);
|
|
|
|
|
2009-05-06 12:08:50 +00:00
|
|
|
void emit_farith(int b1, int b2, int i);
|
|
|
|
|
|
|
|
// labels
|
|
|
|
void print(Label* L);
|
|
|
|
void bind_to(Label* L, int pos);
|
|
|
|
void link_to(Label* L, Label* appendix);
|
|
|
|
|
|
|
|
// record reloc info for current pc_
|
2009-05-28 09:18:17 +00:00
|
|
|
void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0) {
|
|
|
|
UNIMPLEMENTED();
|
|
|
|
}
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
friend class CodePatcher;
|
|
|
|
friend class EnsureSpace;
|
|
|
|
|
|
|
|
// Code buffer:
|
|
|
|
// The buffer into which code and relocation info are generated.
|
|
|
|
byte* buffer_;
|
|
|
|
int buffer_size_;
|
|
|
|
// True if the assembler owns the buffer, false if buffer is external.
|
|
|
|
bool own_buffer_;
|
2009-05-20 12:17:23 +00:00
|
|
|
// A previously allocated buffer of kMinimalBufferSize bytes, or NULL.
|
|
|
|
static byte* spare_buffer_;
|
2009-05-06 12:08:50 +00:00
|
|
|
|
|
|
|
// code generation
|
|
|
|
byte* pc_; // the program counter; moves forward
|
|
|
|
RelocInfoWriter reloc_info_writer;
|
|
|
|
|
|
|
|
// push-pop elimination
|
|
|
|
byte* last_pc_;
|
|
|
|
|
|
|
|
// source position information
|
|
|
|
int current_statement_position_;
|
|
|
|
int current_position_;
|
|
|
|
int written_statement_position_;
|
|
|
|
int written_position_;
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
// Helper class that ensures that there is enough space for generating
|
|
|
|
// instructions and relocation information. The constructor makes
|
|
|
|
// sure that there is enough space and (in debug mode) the destructor
|
|
|
|
// checks that we did not generate too much.
|
|
|
|
class EnsureSpace BASE_EMBEDDED {
|
|
|
|
public:
|
|
|
|
explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) {
|
|
|
|
if (assembler_->overflow()) assembler_->GrowBuffer();
|
|
|
|
#ifdef DEBUG
|
|
|
|
space_before_ = assembler_->available_space();
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef DEBUG
|
|
|
|
~EnsureSpace() {
|
|
|
|
int bytes_generated = space_before_ - assembler_->available_space();
|
|
|
|
ASSERT(bytes_generated < assembler_->kGap);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
private:
|
|
|
|
Assembler* assembler_;
|
|
|
|
#ifdef DEBUG
|
|
|
|
int space_before_;
|
|
|
|
#endif
|
|
|
|
};
|
|
|
|
|
2009-05-05 14:39:05 +00:00
|
|
|
} } // namespace v8::internal
|
|
|
|
|
|
|
|
#endif // V8_X64_ASSEMBLER_X64_H_
|