Commit Graph

30 Commits

Author SHA1 Message Date
erik.corry@gmail.com
66d13be5f9 Fix incorrect encoding of single and double precision registers for some VFP instructions. Also fix incorrect disassembling of vldr/vstr. This is a commit of http://codereview.chromium.org/3107027 for Rodolph Perfetta.
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5352 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-08-26 08:53:00 +00:00
sgjesse@chromium.org
e61bd7bd26 ARM: backend opt for ToBoolean: JIT code generation for ToBool
Upgraded the CodeGenerator::ToBoolean() function in the ARM backend to use complete JIT code generation and not make runtime calls to ToBool (when VFP is enabled). 

This change also includes the vcmp VFP instruction that supports a constant 0.0 as the second operand. 

Patch by Subrato K De <subratokde@codeaurora.org>



git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5267 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-08-16 07:52:49 +00:00
ager@chromium.org
74f9789f61 Landing for Rodolph Perfetta.
Add support for saturation instruction (ARMv6 or above).
The byte array clamping code has been updated accordingly.

Review URL: http://codereview.chromium.org/3036008/show

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5106 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-07-21 07:42:51 +00:00
erik.corry@gmail.com
8c767e02f9 ARM: Add support for the VFP mov literal instruction and mov
between single VFP registers.  Math.pow implementation has
been updated with the new instructions.  This is a commit
of http://codereview.chromium.org/2813046/show for Rodolph
Perfetta.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5037 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-07-08 12:38:02 +00:00
sgjesse@chromium.org
ff6c4fe680 ARM: Special code for raising to the power of an integer
When calculating Math.pow where the exponent is a smi use a simple loop to calculate the result.

Added support for the vmov instruction moving from one doubleword extension register to another.

Added some Math.pow tests which partially covers what is in the Sputnik tests.
Review URL: http://codereview.chromium.org/2804033

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4990 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-30 12:22:15 +00:00
sgjesse@chromium.org
65018d9123 ARM: Use the vsqrt instruction when available
vsqrt is used to calculate Math.sqrt(x), Math.pow(x, 0.5) and Math.pow(x, -0.5). Code size doesn't matter, as %_MathSqrt and %_MathPow are only called in one place each.
Review URL: http://codereview.chromium.org/2885002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4974 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-29 09:40:36 +00:00
erik.corry@gmail.com
53340b2624 Add movw and movt support for ARMv7. This includes some code from
Zhang Kun.  For now we only emit movw and movt in places where no
relocation is needed.  Small performance boost (around 0.5%).
Also adds support for turning ALU operations (eor etc.) with
large immediates into mvn or movw followed by a register-based
ALU operation.
Review URL: http://codereview.chromium.org/2821014

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4913 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-22 08:38:32 +00:00
erik.corry@gmail.com
67c0ec6f17 Update and improve support for ARMv7 bitfield instructions.
This is a commit of http://codereview.chromium.org/2124022
for Rodolph Perfetta.  I changed the test in
test-assembler-arm.cc so it only runs if ARMv7 is supported.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4744 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-05-27 13:46:18 +00:00
mark@chromium.org
e9b5d7855b Allow build-time selection between ia32 and x86_64 in the GYP/Xcode Mac
Chromium build.

v8.gyp no longer sets any V8_TARGET_ARCH_* macro on the Mac. Instead, the
proper V8_TARGET_ARCH_* macro will be set by src/globals.h in the same way as
the V8_HOST_ARCH_* macro when it detects that no target macro is currently
defined. The Mac build will attempt to compile all ia32 and x86_64 .cc files.
#ifdef guards in each of these target-specific source files prevent their
compilation when the associated target is not selected. For completeness,
these #ifdef guards are also provided for the arm and mips .cc files.

BUG=706
TEST=x86_64 Mac GYP/Xcode-based Chromium build (still depends on other changes)
Review URL: http://codereview.chromium.org/2133003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4666 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-05-17 15:41:35 +00:00
erik.corry@gmail.com
d5738c0e6d Add ldrd and strd instructions to the ARM port. This is a
commit for zhangk@codeaurora.org.  See
http://codereview.chromium.org/568029 and
http://codereview.chromium.org/2019003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4618 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-05-07 20:02:57 +00:00
sgjesse@chromium.org
8ced007f5a Update comment to provide the correct usage of the Disassembler class.
TBR=erik.corry@gmail.com
Review URL: http://codereview.chromium.org/1755001

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4457 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-04-21 09:45:06 +00:00
sgjesse@chromium.org
de69f5beba Add support for bkpt instruction
The bkpt instruction is now supported by both the disassembler and the simulator. In the simulator it breaks to the native debugger if any like int3 on Intel.

Moved the handling of the miscellaneous instructions to a separate part.

Review URL: http://codereview.chromium.org/1576026


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4360 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-04-08 13:30:48 +00:00
vegorov@chromium.org
b7833cb5f1 Port of optimized ICs for external and pixel arrays from ia32 to ARM.
Review URL: http://codereview.chromium.org/993002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4228 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-03-23 13:38:04 +00:00
sgjesse@chromium.org
2618422ed5 ARMv7 ubfx support
Patch from Kun Zhang <zhangk@codeaurora.org>, see http://codereview.chromium.org/569015.
Review URL: http://codereview.chromium.org/573027

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3804 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-02-05 08:46:41 +00:00
whesse@chromium.org
f88e7e82b7 Add vstr and vldr floating point load and store to ARM assembler, disassembler, and simulator.
Review URL: http://codereview.chromium.org/545155

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3687 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-01-25 11:54:10 +00:00
erik.corry@gmail.com
593c388b39 Fix for bug 512 from Subrato De, CodeAurora.
Review URL: http://codereview.chromium.org/464016

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3435 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-12-09 11:14:45 +00:00
erik.corry@gmail.com
407816af39 Fix some style issues in the ARM code.
Also move a function into the macro assembler.
Fix some *& placement errors that had accumulated.
Review URL: http://codereview.chromium.org/385069

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3293 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-11-12 13:55:21 +00:00
erik.corry@gmail.com
0d94d7c785 Add vfp support on ARM. Patch from John Jozwiak.
Review URL: http://codereview.chromium.org/348019

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3292 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-11-12 13:04:02 +00:00
sgjesse@chromium.org
3546e91bbc Refactor the register to name mapping in the ARM simulator.
Review URL: http://codereview.chromium.org/195024

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2847 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-09-09 07:01:20 +00:00
lrn@chromium.org
9230ad29eb ARM native regexps.
Review URL: http://codereview.chromium.org/173567


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2785 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-08-31 12:40:37 +00:00
erik.corry@gmail.com
038f9074bc Reapply ARM root array change to reduce const pool size
by using r10 to point to a list of common root objects.
This time we also disable a debugger test on ARM that
has never worked, but with this change sometimes
crashes.
Review URL: http://codereview.chromium.org/174317

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2744 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-08-24 11:57:57 +00:00
feng@chromium.org
33fb11c12f Revert commit 2701 per Erik Corry's request.
Original CL:

http://codereview.chromium.org/171041
Review URL: http://codereview.chromium.org/171089

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2702 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-08-18 00:12:26 +00:00
whesse@chromium.org
349dc04a5d Use root array to load roots in generated ARM code.
This cuts down on code size and reloc work.
Review URL: http://codereview.chromium.org/171041

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2701 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-08-17 14:31:49 +00:00
iposva@chromium.org
05b7b265cb - Update comments and fix a small glitch in the ARM disassembler.
- Fix the use of OS::ActivationFrameAlignment() when running with
  the simulator.
Review URL: http://codereview.chromium.org/155109

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2401 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-07-08 22:13:42 +00:00
erik.corry@gmail.com
9dd35ee2f9 ARM improvements to constant div, mod and mul.
* Fast runtime calls for div and mod.
* Fix assembly and disassembly of multiply instructions.
* Strength reduce and inline multiplications to shift-add.
* Strength reduce and inline mod by power of 2.
* Strength reduce mod by other small integers to mul.
* Strength reduce div by 2 and 3.
Review URL: http://codereview.chromium.org/155047

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2355 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-07-03 12:44:31 +00:00
erik.corry@gmail.com
cea9476cf0 More changes to make the simulator run code that is for the ARM5 snapshot.
Review URL: http://codereview.chromium.org/150100

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2307 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-06-30 13:38:40 +00:00
erik.corry@gmail.com
4a30e3f58e * Add missing imul instruction on Intel.
* Fix incorrect signedness in disassembly of umull/mull on ARM.
* Fix incorrect register order in disassembly of umull/mull.
* Fix incorrect assembly of umull on ARM.
* Remove retroactively obsoleted restriction on choice of
  registers in mul instructions on ARM.
Review URL: http://codereview.chromium.org/150002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2292 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-06-29 09:32:06 +00:00
erik.corry@gmail.com
6b2a49ff83 * Modify simulator and ARM code generator to avoid swi
instructions.  The intention is that the snapshots generated
by the simulator should be usable on the hardware.  Instead of
swi instructions we generate a branch to a swi instruction that
is not part of the snapshot.  The call/jump is patched up in
the same way as other external references when the snapshot
is deserialized.  This only works for EABI targets: on old ABI
targets we still emit some instructions not supported by the
simulator (fp coprocessor instructions).
Review URL: http://codereview.chromium.org/119036

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2127 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-06-09 09:26:53 +00:00
mikhail.naganov@gmail.com
30a0a7de43 Split nested namespaces declaration in two lines in accordance with C++ Style Guide.
This issue was raised by Brett Wilson while reviewing my changelist for readability. Craig Silverstein (one of C++ SG maintainers) confirmed that we should declare one namespace per line. Our way of namespaces closing seems not violating style guides (there is no clear agreement on it), so I left it intact.

Review URL: http://codereview.chromium.org/115756


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2038 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-05-25 10:05:56 +00:00
lrn@chromium.org
a4d756a1c8 Move backend specific files to separate directories.
Move ia32 and arm specific files to subdirectories to make it easier to add more backends.

Review URL: http://codereview.chromium.org/92068


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@1782 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-04-23 12:06:38 +00:00