Commit Graph

113 Commits

Author SHA1 Message Date
Clemens Hammacher
30fabc4cdf Replace CALL_GENERATED_CODE by GeneratedCode wrapper
This ensures that there is only one entrance point from C++ to
generated code, hence only one method has to be excluded from CFI.
It also introduces type safety by only allowing the code to be called
with the right arguments.
This CL includes minor drive-by fixes in the tests, like removing
unused dummy variables.

R=mstarzinger@chromium.org

Bug: v8:7182
Change-Id: Ied9164a2497db9e7c032324c5e082094fdffc72d
Reviewed-on: https://chromium-review.googlesource.com/852213
Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Reviewed-by: Michael Starzinger <mstarzinger@chromium.org>
Commit-Queue: Clemens Hammacher <clemensh@chromium.org>
Cr-Commit-Position: refs/heads/master@{#50426}
2018-01-09 10:33:36 +00:00
Michael Starzinger
542aa4b2f0 [simulator] De-dupe {CALL_GENERATED_CODE} macro definition.
R=clemensh@chromium.org

Change-Id: Ib7e625763f0e017fe4490fb87c4e90e8d57489fd
Reviewed-on: https://chromium-review.googlesource.com/817442
Reviewed-by: Clemens Hammacher <clemensh@chromium.org>
Commit-Queue: Michael Starzinger <mstarzinger@chromium.org>
Cr-Commit-Position: refs/heads/master@{#50001}
2017-12-11 17:07:44 +00:00
Mathias Bynens
822be9b238 Normalize casing of hexadecimal digits
This patch normalizes the casing of hexadecimal digits in escape
sequences of the form `\xNN` and integer literals of the form
`0xNNNN`.

Previously, the V8 code base used an inconsistent mixture of uppercase
and lowercase.

Google’s C++ style guide uses uppercase in its examples:
https://google.github.io/styleguide/cppguide.html#Non-ASCII_Characters

Moreover, uppercase letters more clearly stand out from the lowercase
`x` (or `u`) characters at the start, as well as lowercase letters
elsewhere in strings.

BUG=v8:7109
TBR=marja@chromium.org,titzer@chromium.org,mtrofin@chromium.org,mstarzinger@chromium.org,rossberg@chromium.org,yangguo@chromium.org,mlippautz@chromium.org
NOPRESUBMIT=true

Cq-Include-Trybots: master.tryserver.blink:linux_trusty_blink_rel;master.tryserver.chromium.linux:linux_chromium_rel_ng
Change-Id: I790e21c25d96ad5d95c8229724eb45d2aa9e22d6
Reviewed-on: https://chromium-review.googlesource.com/804294
Commit-Queue: Mathias Bynens <mathias@chromium.org>
Reviewed-by: Jakob Kummerow <jkummerow@chromium.org>
Cr-Commit-Position: refs/heads/master@{#49810}
2017-12-02 01:24:40 +00:00
Predrag Rudic
25d4f93740 Reland "MIPS[64] Implementation of MSA instructions on builtin simulator"
This is reland of 3e0bf580e8
Original change's description:
> This commit is a step toward enabling test-run-wasm-simd tests for MIPS.
> 36 of those were failing in V8 builtin simulator because some instructions
> were not implemented.  Also there are minor fixes to some of the already
> implemented instructions.
>
> This commit has only 32-bit implementation. After review I will add
> 64-bit version.
>
> Bug:
> Change-Id: I25b0cac352db3efb56b922ace64ab2aaef82472d
> Reviewed-on: https://chromium-review.googlesource.com/744008
> Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
> Reviewed-by: Jakob Kummerow <jkummerow@chromium.org>
> Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
> Cr-Commit-Position: refs/heads/master@{#49439}

Bug: 
Change-Id: I3a904caf675d314186c02c1c843d1e6a91a21a14
Reviewed-on: https://chromium-review.googlesource.com/776813
Reviewed-by: Jakob Kummerow <jkummerow@chromium.org>
Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
Reviewed-by: Benedikt Meurer <bmeurer@chromium.org>
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
Cr-Commit-Position: refs/heads/master@{#49666}
2017-11-28 13:43:23 +00:00
Clemens Hammacher
4c420258d3 Revert "MIPS[64] Implementation of MSA instructions in builtin simulator"
This reverts commit 3e0bf580e8.

Reason for revert: MSVC does not compile any more, see https://build.chromium.org/p/client.v8/builders/V8%20Win64%20-%20msvc/builds/172

Original change's description:
> MIPS[64] Implementation of MSA instructions in builtin simulator
> 
> This commit is a step toward enabling test-run-wasm-simd tests for MIPS.
> 36 of those were failing in V8 builtin simulator because some instructions
> were not implemented.  Also there are minor fixes to some of the already
> implemented instructions.
> 
> This commit has only 32-bit implementation. After review I will add
> 64-bit version.
> 
> Bug: 
> Change-Id: I25b0cac352db3efb56b922ace64ab2aaef82472d
> Reviewed-on: https://chromium-review.googlesource.com/744008
> Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
> Reviewed-by: Jakob Kummerow <jkummerow@chromium.org>
> Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
> Cr-Commit-Position: refs/heads/master@{#49439}

TBR=jkummerow@chromium.org,mstarzinger@chromium.org,mlippautz@chromium.org,bmeurer@chromium.org,predrag.rudic@mips.com,ivica.bogosavljevic@mips.com,Ilija.Pavlovic@mips.com,sreten.kovacevic@mips.com,Miran.Karic@imgtec.com

Change-Id: Ic0c6339473481fa75908e942bc86de2b5c6349d8
No-Presubmit: true
No-Tree-Checks: true
No-Try: true
Reviewed-on: https://chromium-review.googlesource.com/776655
Reviewed-by: Clemens Hammacher <clemensh@chromium.org>
Commit-Queue: Clemens Hammacher <clemensh@chromium.org>
Cr-Commit-Position: refs/heads/master@{#49441}
2017-11-17 11:02:48 +00:00
Predrag Rudic
3e0bf580e8 MIPS[64] Implementation of MSA instructions in builtin simulator
This commit is a step toward enabling test-run-wasm-simd tests for MIPS.
36 of those were failing in V8 builtin simulator because some instructions
were not implemented.  Also there are minor fixes to some of the already
implemented instructions.

This commit has only 32-bit implementation. After review I will add
64-bit version.

Bug: 
Change-Id: I25b0cac352db3efb56b922ace64ab2aaef82472d
Reviewed-on: https://chromium-review.googlesource.com/744008
Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
Reviewed-by: Jakob Kummerow <jkummerow@chromium.org>
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
Cr-Commit-Position: refs/heads/master@{#49439}
2017-11-17 10:24:15 +00:00
Clemens Hammacher
5f6510825a [cleanup] Fix remaining (D)CHECK macro usages
This CL fixes all occurences that don't require special OWNER reviews,
or can be reviewed by Michi.

After this one, we should be able to reenable the readability/check
cpplint check.

R=mstarzinger@chromium.org

Bug: v8:6837, v8:6921
Cq-Include-Trybots: master.tryserver.chromium.linux:linux_chromium_rel_ng;master.tryserver.v8:v8_linux_noi18n_rel_ng
Change-Id: Ic81d68d5534eaa795b7197fed5c41ed158361d62
Reviewed-on: https://chromium-review.googlesource.com/721120
Commit-Queue: Clemens Hammacher <clemensh@chromium.org>
Reviewed-by: Michael Starzinger <mstarzinger@chromium.org>
Cr-Commit-Position: refs/heads/master@{#48670}
2017-10-18 10:12:31 +00:00
Mathias Bynens
62f929ff4c Use nullptr instead of NULL where possible
New code should use nullptr instead of NULL.

This patch updates existing use of NULL to nullptr where applicable,
making the code base more consistent.

BUG=v8:6928,v8:6921

Cq-Include-Trybots: master.tryserver.chromium.linux:linux_chromium_rel_ng;master.tryserver.v8:v8_linux_noi18n_rel_ng
Change-Id: I4687f5b96fcfd88b41fa970a2b937b4f6538777c
Reviewed-on: https://chromium-review.googlesource.com/718338
Commit-Queue: Mathias Bynens <mathias@chromium.org>
Reviewed-by: Andreas Haas <ahaas@chromium.org>
Reviewed-by: Benedikt Meurer <bmeurer@chromium.org>
Reviewed-by: Ulan Degenbaev <ulan@chromium.org>
Reviewed-by: Toon Verwaest <verwaest@chromium.org>
Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Reviewed-by: Yang Guo <yangguo@chromium.org>
Cr-Commit-Position: refs/heads/master@{#48557}
2017-10-13 17:21:49 +00:00
Predrag Rudic
31fa640d06 MIPS[64]:Implement MSA 3RF instructions for V8 builtin simulator
Bug: 
Change-Id: Icc4fd48ba1313cb94102ac794b06927d24151671
Reviewed-on: https://chromium-review.googlesource.com/708270
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Cr-Commit-Position: refs/heads/master@{#48551}
2017-10-13 14:08:01 +00:00
Toon Verwaest
1067026ff1 Remove ComputeFlags, simply pass in Code::Kind instead of Code::Flags
TBR: ofrobots@google.com, yangguo@chromium.org
Bug: 
Change-Id: I6cb0704acabf9a7f2334de539a6600db8607baef
Reviewed-on: https://chromium-review.googlesource.com/691720
Commit-Queue: Toon Verwaest <verwaest@chromium.org>
Reviewed-by: Michael Starzinger <mstarzinger@chromium.org>
Cr-Commit-Position: refs/heads/master@{#48237}
2017-09-29 15:37:27 +00:00
Predrag Rudic
d2e22dbf6d MIPS[64]: Implement MSA 2RF instructions for V8 builtin simulator
Change-Id: Id2eef89f0eba3c59bcdb490e7d986b4b3af0ff9b
Reviewed-on: https://chromium-review.googlesource.com/657677
Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Cr-Commit-Position: refs/heads/master@{#48230}
2017-09-29 13:22:42 +00:00
Ivica Bogosavljevic
01e3be5046 MIPS[64]: Implement 3R MSA instructions in simulator
Bug: 
Change-Id: Ia7bbbb2aba28ec36b470a1b23ebe38fc3a09e600
Reviewed-on: https://chromium-review.googlesource.com/657757
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Reviewed-by: Miran Karić <Miran.Karic@imgtec.com>
Reviewed-by: Jakob Kummerow <jkummerow@chromium.org>
Cr-Commit-Position: refs/heads/master@{#48108}
2017-09-21 13:27:44 +00:00
Michael Starzinger
bc69f3450b [iwyu] Remove illegal inline include from "macro-assembler.h"
R=clemensh@chromium.org

Cq-Include-Trybots: master.tryserver.v8:v8_linux_noi18n_rel_ng
Change-Id: I3df5d50f81909188ee0cb31d0f479aadeeabe20f
Reviewed-on: https://chromium-review.googlesource.com/662780
Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Reviewed-by: Igor Sheludko <ishell@chromium.org>
Reviewed-by: Clemens Hammacher <clemensh@chromium.org>
Commit-Queue: Michael Starzinger <mstarzinger@chromium.org>
Cr-Commit-Position: refs/heads/master@{#47991}
2017-09-13 11:44:07 +00:00
Michael Starzinger
dac0ed5654 [cctest] Avoid disallowed "using namespace" directive.
R=jkummerow@chromium.org

Change-Id: I8937933e9ec5b4bd150f5a044700716db458f365
Reviewed-on: https://chromium-review.googlesource.com/645691
Reviewed-by: Jakob Kummerow <jkummerow@chromium.org>
Commit-Queue: Michael Starzinger <mstarzinger@chromium.org>
Cr-Commit-Position: refs/heads/master@{#47758}
2017-09-01 08:28:36 +00:00
Ivica Bogosavljevic
c0a632b3b1 MIPS[64]: Add simulation support for MIPS SIMD MI10 instruction group
Add support for the simulation of MIPS SIMD MI10 instruction group,
which included Load Vector and Store Vector instructions. Add
corresponding test for these instructions.

Bug: 
Change-Id: I7cbc9d8dff2a779d9a716f539cd9a2bbb8ac694a
Reviewed-on: https://chromium-review.googlesource.com/595567
Reviewed-by: Miran Karić <Miran.Karic@imgtec.com>
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Cr-Commit-Position: refs/heads/master@{#47226}
2017-08-08 14:32:27 +00:00
Dusan Simicic
1084d20978 Reland "MIPS[64]: Implement MSA I10 instructions in simulator"
This is reland of 34ed247071.
Fixed build error:

https: //build.chromium.org/p/client.v8.ports/builders/V8%20Mips%20-%20builder/builds/10881
Bug: 
Change-Id: Ie49ac7097b12780ab1f2f3a8559a4a5f25bc73ab
Reviewed-on: https://chromium-review.googlesource.com/579433
Reviewed-by: Miran Karić <Miran.Karic@imgtec.com>
Commit-Queue: Miran Karić <Miran.Karic@imgtec.com>
Cr-Commit-Position: refs/heads/master@{#46794}
2017-07-20 13:18:22 +00:00
Michael Achenbach
b23b8c088c Revert "MIPS[64]: Implement MSA I10 instructions in simulator"
This reverts commit 34ed247071.

Reason for revert: Compile on mips builder:
https://build.chromium.org/p/client.v8.ports/builders/V8%20Mips%20-%20builder/builds/10881

Original change's description:
> MIPS[64]: Implement MSA I10 instructions in simulator
> 
> Bug: 
> Change-Id: Ib252b157977fe97f6f4ceb6e7f696f14ca12680e
> Reviewed-on: https://chromium-review.googlesource.com/574595
> Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
> Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
> Cr-Commit-Position: refs/heads/master@{#46783}

TBR=ivica.bogosavljevic@imgtec.com,Ilija.Pavlovic@imgtec.com,dusan.simicic@imgtec.com,Miran.Karic@imgtec.com

Change-Id: Ic855904b3f93e5ef941a27bcc67c61c15303422a
No-Presubmit: true
No-Tree-Checks: true
No-Try: true
Reviewed-on: https://chromium-review.googlesource.com/579048
Reviewed-by: Michael Achenbach <machenbach@chromium.org>
Commit-Queue: Michael Achenbach <machenbach@chromium.org>
Cr-Commit-Position: refs/heads/master@{#46784}
2017-07-20 09:15:34 +00:00
Dusan Simicic
34ed247071 MIPS[64]: Implement MSA I10 instructions in simulator
Bug: 
Change-Id: Ib252b157977fe97f6f4ceb6e7f696f14ca12680e
Reviewed-on: https://chromium-review.googlesource.com/574595
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Cr-Commit-Position: refs/heads/master@{#46783}
2017-07-20 09:11:20 +00:00
Dusan Simicic
6d9025ef57 MIPS[64]: Implement MSA Bit instructions in simulator
Add support for slli, srai, srli, bclri, bseti, bnegi, binsli, binsri,
sat_s, sat_u, srari, srlri MSA instructions in mips32 and mips64
simulators.

Bug: 
Change-Id: I1a351a23c733f0bfbc829f25874df26295327afc
Reviewed-on: https://chromium-review.googlesource.com/568020
Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Cr-Commit-Position: refs/heads/master@{#46764}
2017-07-19 13:42:02 +00:00
Dusan Simicic
c16a39f23e MIPS[64]: Implement vector MSA instructions in simulator
Add support for and.v, or.v, nor.v, xor.v, bmnz.v, bmz.v, bsel.v MSA
instructions in mips32 and mips64 simulator.

Bug: 
Change-Id: Idf092a1c211959a096694485268fff379b612b77
Reviewed-on: https://chromium-review.googlesource.com/533075
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Cr-Commit-Position: refs/heads/master@{#46474}
2017-07-07 12:10:51 +00:00
Ilija Pavlovic
fe37d91345 MIPS[64]: Add tests for INS and EXT instructions.
This CL contains new created tests for instructions INS and EXT.

TEST=cctest/test-assembler-mips[64]/Ins,
     cctest/test-assembler-mips[64]/Ext
BUG=

Change-Id: Ie62037ee425a5cba3700c5025608fdada144add5
Reviewed-on: https://chromium-review.googlesource.com/561319
Commit-Queue: Miran Karić <Miran.Karic@imgtec.com>
Reviewed-by: Miran Karić <Miran.Karic@imgtec.com>
Cr-Commit-Position: refs/heads/master@{#46468}
2017-07-07 08:37:57 +00:00
Dusan Simicic
6886f2ceed MIPS[64]: Implement MSA 2R instructions in simulator
Add support for pcnt.df, nlzc.df, nloc.df MSA instructions in mips32 and
mips64 simulator.

Bug: 
Change-Id: I15c2e832c317ff81ce3615b7bd269e039c978e93
Reviewed-on: https://chromium-review.googlesource.com/538654
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Cr-Commit-Position: refs/heads/master@{#46410}
2017-07-05 11:58:57 +00:00
Miran.Karic
eaf850e2e0 MIPS: Fix ins and ext instructions in simulator.
Instructions ins and ext didn't work properly when size = 32 because of
incorrect mask initialization, this CL fixes this. A test for Ins is
also added.

BUG=

Change-Id: I95cc8e13aaa2341b34ae59dae1eefb64c551b8b4
Reviewed-on: https://chromium-review.googlesource.com/558872
Commit-Queue: Miran Karić <Miran.Karic@imgtec.com>
Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Cr-Commit-Position: refs/heads/master@{#46378}
2017-07-03 09:44:23 +00:00
Dusan Simicic
5f0d82881c MIPS[64]: Implement MSA I5 instructions in simulator
Add support for MSA I5 instructions in mips32 and mips64 simulators.

Bug: 
Change-Id: Ie1be499a1b3c686603348d895456b8f39d5c1002
Reviewed-on: https://chromium-review.googlesource.com/552554
Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Cr-Commit-Position: refs/heads/master@{#46359}
2017-06-30 13:23:44 +00:00
neis
659e8f7b5c [compiler] Delay allocation of code-embedded heap numbers.
Instead of allocating and embedding certain heap numbers into the code
during code assembly, emit dummies but record the allocation requests.
Later then, in Assembler::GetCode, allocate the heap numbers and patch
the code by replacing the dummies with the actual objects. The
RelocInfos for the embedded objects are already recorded correctly when
emitting the dummies.

R=jarin@chromium.org
BUG=v8:6048

Review-Url: https://codereview.chromium.org/2900683002
Cr-Commit-Position: refs/heads/master@{#45635}
2017-05-31 14:00:11 +00:00
dusan.simicic
f87271ccd0 MIPS[64]: Implement insert.df and I8 instructions in simulator
Add support for insert.df, andi.b, ori.b, nori.b, xori.b,
bmnzi.b, bmzi.b, bseli.b, shf.df MSA instructions in mips32
and mips64 simulator.

BUG=

Review-Url: https://codereview.chromium.org/2908753002
Cr-Commit-Position: refs/heads/master@{#45620}
2017-05-31 09:34:46 +00:00
dusan.simicic
1f06818739 MIPS[64]: Implement fill.df, copy_u.df, copy_s.df instructions in simulator
- Increase FPUregisters_[] element size to 128b in order to support MSA regs
- Add skeleton for MSA instr. decoding in mips32 and mips64 simulator
- Add support for fill.df, copy_u.df and copy_s.df MSA instructions
- Assembler test for fill.df, copy_u.df and copy_s.df

BUG=

Review-Url: https://codereview.chromium.org/2799923002
Cr-Commit-Position: refs/heads/master@{#45529}
2017-05-25 14:51:07 +00:00
Miran.Karic
cc1aae2812 MIPS64: Add optimizations to li macro.
A number of improvements in mips64 load immediate macro is added per
suggestions from MIPS ART team. Also fix Subu and Dsubu macro, add a
test for Subu and Dsubu and make minor code adjustments.

BUG=
TEST=cctest/test-assembler-mips/li_macro
     cctest/test-assembler-mips/Subu
     cctest/test-assembler-mips/Dsubu

Review-Url: https://codereview.chromium.org/2892163002
Cr-Commit-Position: refs/heads/master@{#45493}
2017-05-23 16:01:41 +00:00
Miran.Karic
de14ba9fd2 MIPS: Fix Subu and add optimization
For int16 imm values Subu would emit addiu with -imm value, but doing
this with min_int16 would overflow and produce incorrect result. This is
fixed by checking if -imm is int16. A test for this case is created.

An optimization is also added for values imm where we cannot just emit
addiu and loading -imm to a register takes one instruction using ori.
Then instead of loading imm with lui;ori and subtracting with subu, we
can load -imm with ori and add with addu.

BUG=
TEST=cctest/test-assembler-mips/Subu

Review-Url: https://codereview.chromium.org/2845043002
Cr-Commit-Position: refs/heads/master@{#44932}
2017-04-27 12:56:50 +00:00
Ilija.Pavlovic
47da8de250 MIPS: Move ldc1/sdc1 to macro-assembler.
For MIPS32, instructions ldc1 and sdc1 are moved into macro-assembler
and renamed as Ldc1 and Sdc1. The reason for placing them into
macro-assembler is that they emmit two or three instructions.

TEST=test/cctest/test-assembler-mips,
     test/cctest/test-code-stubs-mips,
     test/cctest/test-macro-assembler-mips
BUG=

Review-Url: https://codereview.chromium.org/2751973002
Cr-Commit-Position: refs/heads/master@{#43977}
2017-03-21 11:35:40 +00:00
franzih
3df821c24e [test] Make CHECK_EQ calls in cctest consistent.
Cleanup CHECK_EQ order and simplify CHECK_EQ(true/false).
Cleanup callorder for negative numbers
Cleanup callorder order for capital letter constants.
Cleanup callorder for test.x checks.

BUG=

Review-Url: https://codereview.chromium.org/2677183002
Cr-Commit-Position: refs/heads/master@{#42997}
2017-02-07 14:20:02 +00:00
predrag.rudic
11f0a0e819 Fix MIPS maddf and msubf instructions in simulator and tests.
Tests were falling in qemu because of inexact computation in tests.
After correcting tests, simulator also had to be fixed.

Review-Url: https://codereview.chromium.org/2539133002
Cr-Commit-Position: refs/heads/master@{#41447}
2016-12-02 09:12:04 +00:00
ivica.bogosavljevic
7d48278119 MIPS: Fix compilation failures due to warnings on mips32r1
BUG=

Review-Url: https://codereview.chromium.org/2359923003
Cr-Commit-Position: refs/heads/master@{#39664}
2016-09-23 13:23:52 +00:00
Ilija.Pavlovic
65fd5e1165 MIPS: Implement MADD.S, MSUB, MADDF and MSUBF.
Implementation MADD.S. MSUB.fmt, MADDF.fmt, MSUBF.fmt and corresponding
tests for assembler and disassembler.

TEST=cctest/test-assembler-mips[64], cctest/test-disasm-mips[64]
BUG=

Review-Url: https://codereview.chromium.org/2313623002
Cr-Commit-Position: refs/heads/master@{#39415}
2016-09-14 11:37:13 +00:00
balazs.kilvady
5345727935 MIPS: Fix unbounded label counter.
TEST=mjsunit/asm/embenchen/zlib
BUG=

Review-Url: https://codereview.chromium.org/1925543003
Cr-Commit-Position: refs/heads/master@{#35854}
2016-04-28 11:01:12 +00:00
Ilija.Pavlovic
0b479e4e81 MIPS: Enable big endian testing.
Enabled big endian testing for MIPS32 and MIPS64. The tests are also
adapted for big endian variant.

TEST=cctest/test-assembler-mips[64]
BUG=

Review URL: https://codereview.chromium.org/1867503002

Cr-Commit-Position: refs/heads/master@{#35369}
2016-04-11 06:36:42 +00:00
balazs.kilvady
d4a391bb7a MIPS: Support r6 min, max floating point instructions.
Use macro instructions for min, max ops to get the same functionality on
pre-r6 and r6 targets.

BUG=
TEST=mjsunit/math-min-max, cctest/test-macro-assembler-mips64/min_max_nan, cctest/test-macro-assembler-mips/min_max_nan, cctest/test-assembler-mips64/min_max, cctest/test-assembler-mips/min_max

Review URL: https://codereview.chromium.org/1694833002

Cr-Commit-Position: refs/heads/master@{#35073}
2016-03-25 16:51:23 +00:00
balazs.kilvady
04a735c7e7 MIPS: Improve Lsa/Dlsa implementations.
Make the low level assembler implementation exact and protected to disallow explicit usage.

BUG=

Review URL: https://codereview.chromium.org/1749263002

Cr-Commit-Position: refs/heads/master@{#34673}
2016-03-10 13:41:34 +00:00
ivica.bogosavljevic
b23d5389e0 Reland of MIPS: Add FPXX support to MIPS32R2
Fix failures on MIPS simulator because incomplete
handling of MTHC1 and MFHC1 in Fp32 mode
Fix failures on older kernels that have problems with
MTHC1 and MFHC1 in kernel FPU emulation

Original issue's description:
> Revert of MIPS: Add FPXX support to MIPS32R2 (patchset #3
> id:40001 of https://codereview.chromium.org/1586223004/ )
>
> Reason for revert:
> Revert patch due to a number of failures appearing on the > MIPS v8 simulator
>
> Original issue's description:
>> MIPS: Add FPXX support to MIPS32R2
>>
>> The JIT code generated by V8 is FPXX compliant
>> when v8 compiled with FPXX flag. This allows the code to
>> run in both FP=1 and FP=0 mode. It also alows v8 to be used
>> as a library by both FP32 and FP64 binaries.
>>
>> BUG=
>>
>> Committed: https://crrev.com/95110dde666158a230a823fd50a68558ad772320
>> Cr-Commit-Position: refs/heads/master@{#33576}

BUG=

Review URL: https://codereview.chromium.org/1659883002

Cr-Commit-Position: refs/heads/master@{#33808}
2016-02-08 09:44:19 +00:00
balazs.kilvady
a58c750ccc MIPS: Fix FPU min, max, mina, maxa in simulator.
BUG=
TEST=cctest/test-assembler-mips/min_max, cctest/test-assembler-mips/mina_maxa, cctest/test-assembler-mips64/min_max, cctest/test-assembler-mips64/mina_maxa

Review URL: https://codereview.chromium.org/1668143002

Cr-Commit-Position: refs/heads/master@{#33790}
2016-02-05 17:59:05 +00:00
balazs.kilvady
ebac85c0a4 MIPS: Use PC relative instructions on r6.
BUG=

Review URL: https://codereview.chromium.org/1628453002

Cr-Commit-Position: refs/heads/master@{#33703}
2016-02-03 13:31:30 +00:00
ivica.bogosavljevic
ca404f3c15 Revert of MIPS: Add FPXX support to MIPS32R2 (patchset #3 id:40001 of https://codereview.chromium.org/1586223004/ )
Reason for revert:
Revert patch due to a number of failures appearing on the MIPS v8 simulator

Original issue's description:
> MIPS: Add FPXX support to MIPS32R2
>
> The JIT code generated by V8 is FPXX compliant
> when v8 compiled with FPXX flag. This allows the code to
> run in both FP=1 and FP=0 mode. It also alows v8 to be used
> as a library by both FP32 and FP64 binaries.
>
> BUG=
>
> Committed: https://crrev.com/95110dde666158a230a823fd50a68558ad772320
> Cr-Commit-Position: refs/heads/master@{#33576}

TBR=paul.lind@imgtec.com,gergely.kis@imgtec.com,akos.palfi@imgtec.com,ilija.pavlovic@imgtec.com,marija.antic@imgtec.com,miran.karic@imgtec.com,balazs.kilvady@imgtec.com
# Skipping CQ checks because original CL landed less than 1 days ago.
NOPRESUBMIT=true
NOTREECHECKS=true
NOTRY=true
BUG=

Review URL: https://codereview.chromium.org/1646813003

Cr-Commit-Position: refs/heads/master@{#33583}
2016-01-28 13:09:39 +00:00
ivica.bogosavljevic
95110dde66 MIPS: Add FPXX support to MIPS32R2
The JIT code generated by V8 is FPXX compliant
when v8 compiled with FPXX flag. This allows the code to
run in both FP=1 and FP=0 mode. It also alows v8 to be used
as a library by both FP32 and FP64 binaries.

BUG=

Review URL: https://codereview.chromium.org/1586223004

Cr-Commit-Position: refs/heads/master@{#33576}
2016-01-28 09:34:01 +00:00
balazs.kilvady
5091e8f2f5 MIPS: Fix dd() implementations for compact branches.
BUG=

Review URL: https://codereview.chromium.org/1573953002

Cr-Commit-Position: refs/heads/master@{#33249}
2016-01-12 19:49:18 +00:00
balazs.kilvady
8d6899c827 MIPS: Add lsa and dlsa r6 instructions.
BUG=

Review URL: https://codereview.chromium.org/1545013002

Cr-Commit-Position: refs/heads/master@{#33127}
2016-01-05 19:46:15 +00:00
paul.lind
ac33eaba10 MIPS: Remove clang-format-off from assembler tests.
Per request in https://codereview.chromium.org/1047213002/

These files will continue to have a lot of churn in next two months
as we finish support for MIPS r6 instruction set. When things settle
down, we will do a clang-format --full to clean them up. For now,
we'd prefer to be able to do easy diffs, and will do incremental
re-formats as we make changes.

BUG=

Review URL: https://codereview.chromium.org/1546973003

Cr-Commit-Position: refs/heads/master@{#33038}
2015-12-24 14:17:57 +00:00
ivica.bogosavljevic
108d52645a MIPS: Fix uninitialized upper word bits for Cvt_d_uw macro.
After Cvt_d_uw macro, upper 32 bits of the output remain
unitnitialized which caused flaky failures on some tests on
MIPS32R6

TEST=cctest/test-assembler-mips/MIPS13,mjsunit/asm/int32-umod
BUG=

Review URL: https://codereview.chromium.org/1537973002

Cr-Commit-Position: refs/heads/master@{#32983}
2015-12-21 10:49:35 +00:00
jochen
6f472db65a Disable soon to be deprecated APIs per default for v8
Embedders still can use those APIs by default

test-api.cc still has an exception to use the old APIs...

BUG=v8:4143
R=vogelheim@chromium.org
LOG=n

Review URL: https://codereview.chromium.org/1505803004

Cr-Commit-Position: refs/heads/master@{#32701}
2015-12-09 10:35:04 +00:00
bmeurer
fc0a1a709c [test] Test expectations in cctest should use CHECK and not DCHECK.
The test expectations should fail consistently in both release and debug
builds. DCHECK is only meant for debug-only checks in production code.

R=yangguo@chromium.org

Review URL: https://codereview.chromium.org/1506753002

Cr-Commit-Position: refs/heads/master@{#32639}
2015-12-07 05:37:15 +00:00
ivica.bogosavljevic
60d77c8a43 MIPS: Correct handling of Nan values on MIPS R6
MIPS R6 introduced new behavior for handling of NaN values
for TRUNC, FLOOR, CEIL and CVT instructions. Adding support for
the new behavior in MIPS and MIPS64 simulators. Fixing tests
for MIPS and MIPS64 to align them with the new behavior.

BUG=

Review URL: https://codereview.chromium.org/1488613007

Cr-Commit-Position: refs/heads/master@{#32499}
2015-12-02 10:55:23 +00:00