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127 Commits

Author SHA1 Message Date
ager@chromium.org
5ec91a4279 x64: Fix safepoint register index calculation. 
We leave room for all registers on the stack so we have to add a bit.

This is not nicely factored and I need to do that. This will fix the breakage and I
will fix the rest on Monday.

TBR=lrn@chromium.org

Review URL: http://codereview.chromium.org/6544017

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6857 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-18 16:16:17 +00:00
ager@chromium.org
b8f0b88b54 x64: Implement regexp literals and string CharCodeAt in lithium backend. 
Review URL: http://codereview.chromium.org/6469052

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6853 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-18 14:00:46 +00:00
ager@chromium.org
d5851dcde0 x64: Enable inline smi code patching to reenable the inlined code in 
the code generated by the full code generator after my previous
change.

The generated code is the same as on ia32 and so is the patching.

Review URL: http://codereview.chromium.org/6456023

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6703 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-09 14:51:38 +00:00
ricow@chromium.org
f64966085e x64: Add MulI and DivI to lithium instructions. 
Review URL: http://codereview.chromium.org/6448001

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6681 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-08 14:37:50 +00:00
ager@chromium.org
52cfd6ab16 Fixed a number of issues on x64 crankshaft port: 
- Don't use SmiSub when overflow can occur. It asserts that overflow
  does not happen.

- Actually use CompareICs and signal to crankshaft whether or not smi
  code was inlined.

- Fix bug in CmpI where 64 bits were compared instead of 32 bits.

- Implement Throw, DeferredStackCheck, StoreKeyedFastElement in
  lithium backend.

BUG=
TEST=

Review URL: http://codereview.chromium.org/6312193

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6669 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-08 07:49:59 +00:00
lrn@chromium.org
19b734fd82 Fix potential overwriting of debug jumps of following code. 
Add JSArrayLength, CallKnownFunction, and InstanceType operations.
Remove LadGlobal and StoreGlobal again (they fail).

Review URL: http://codereview.chromium.org/6347067

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6645 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-04 14:09:03 +00:00
whesse@chromium.org
f1acd1299d X64 Crankshaft: Port TaggedToI to X64. 
Review URL: http://codereview.chromium.org/6368097

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6637 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-04 13:16:51 +00:00
whesse@chromium.org
c5de2c95fa X64 Crankshaft: Add bit operations and shifts to x64 crankshaft. 
Review URL: http://codereview.chromium.org/6246099

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6632 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-02-04 11:10:39 +00:00
whesse@chromium.org
cd935a417b X64 Crankshaft: Remove relative jump to deoptimization code. Fixes logical error, and compilation error on Windows. 
Review URL: http://codereview.chromium.org/6310018

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6489 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-26 13:24:19 +00:00
lrn@chromium.org
43d7951677 X64 Crankshaft: Added a bunch of operations. 
Review URL: http://codereview.chromium.org/6366010

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6455 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-25 11:30:47 +00:00
ricow@chromium.org
d5cab38a33 Add support for deoptimization on x64. 
I did not take out the code relating to osr from the generate method
since this makes it easier to compare to ia32 (we will abort anyway when we hit the osr code so there should be no issues with having this in)
 

Review URL: http://codereview.chromium.org/6390001

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6449 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-25 07:57:56 +00:00
kbr@chromium.org
cbc1c0fca6 Truncate rather than round to nearest when performing float-to-integer 
conversions for external array types, which implement the Typed Array
spec. (Revision of http://codereview.chromium.org/6315004 .)

Prefer SSE2 code path on x86 processors. Non-SSE2 processors now make
a slow runtime call for float-to-int conversions. Use SSE3 for 32-bit
signed and unsigned int array types where possible.

The movement of code from ic-arm.cc to stub-cache-arm.cc caused the
VFP3 code path to be tested for the first time. Fixed bugs in the
register usage and in the constant value stored into integer arrays
for NaN and +/-Infinity.

Added new truncation test to test-api.cc. Storage of NaN and +/-Inf
was already covered. Ran unit tests on x86, x64 and ARM simulator.
Tested ia32 and x64 code in Chromium on Mac and Linux respectively
with Typed Array unit tests and WebGL content.

BUG=http://code.google.com/p/chromium/issues/detail?id=50972
TEST=test-api/ExternalArrays

Review URL: http://codereview.chromium.org/6303012

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6431 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-21 23:58:00 +00:00
lrn@chromium.org
e66ceb9079 X64 Crank: Implemented DoBranch and all *AndBranch comparisons. 
Review URL: http://codereview.chromium.org/6374002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6385 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-19 10:17:18 +00:00
ager@chromium.org
6b4d29766c Revert r6376 and r6373 which changes external array support. The ARM 
version did not work.

TBR=kbr@chromium.org
Review URL: http://codereview.chromium.org/6295013

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6381 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-19 08:20:42 +00:00
kbr@chromium.org
27f0ae7aad Truncate rather than round to nearest when performing float-to-integer 
conversions for external array types, which implement the Typed Array
spec. The new code paths are for SSE3 and SSE2 capable processors.
The code for non-SSE2 processors is unchanged for now. The ARM port
appears to already be correct.

Moved the generation of the external array load and store intrinsics
to the stub cache (on all platforms) so that they are generated at run
time and can take advantage of CPU features.

This functionality is covered by the array-unit-tests.html test in the
WebGL conformance test suite:
http://khronos.org/webgl/wiki/Testing/Conformance
https://cvs.khronos.org/svn/repos/registry/trunk/public/webgl/sdk/tests/conformance/array-unit-tests.html

Manually verified all of the SSE3/SSE2/non-SSE2 code paths by enabling
each in turn. Tested in Chromium on 32-bit Mac OS X and 64-bit Linux.

BUG=http://code.google.com/p/chromium/issues/detail?id=50972
TEST=none (see above)

Review URL: http://codereview.chromium.org/6315004

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6373 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-18 21:51:50 +00:00
ricow@chromium.org
3d245133a3 Enable compilation of very simple functions in x64 crankshaft. 
This change includes support for safepointtables and adding deoptimization info (but not for deoptimizing).

Implemented crankshaft functions:
CallCode
GenerateSafepointTable
RegisterEnvironmentForDeoptimization
EmitGoto


This change allows us to compile very simple functions with crankshaft:
An empty function
A function returning a constant.
A function returning a parameter.

There is 6 disabled tests that require us to be able to deoptimize
which is currently not supported.


Review URL: http://codereview.chromium.org/6310009

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6350 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-17 13:11:39 +00:00
lrn@chromium.org
2b4767b584 X64: Fix allocated register name table. 
BUG=
TEST=

Review URL: http://codereview.chromium.org/6247006

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6325 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-14 14:03:05 +00:00
ricow@chromium.org
5e557d3624 Add implementations of some more x64 lithium methods. 
This puts us very close to being able to compile the empty function.

This changes only has a small number of 64 bit specific assembler instructions.

The remaining changes are much more platform specific and will go in another change.

Review URL: http://codereview.chromium.org/6247005

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6306 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-14 10:27:25 +00:00
lrn@chromium.org
ba023c5405 X64 Crankshaft: Ported lots of boilerplate code. 
Small tweaks to make X64 compliant.
A few UNIMPLEMENTED left, but most empty functions call Abort to bail out.

Review URL: http://codereview.chromium.org/6201006

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6297 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-13 10:04:02 +00:00
whesse@chromium.org
7fa57552fa Cleanup of x64 code. Rearrange functions in ic-x64.cc to match order in ic-ia32.cc. Remove unused declarations, and move a constant to assembler-x64.h. 
Review URL: http://codereview.chromium.org/6020012

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@6143 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2011-01-04 09:50:35 +00:00
kasperl@chromium.org
90b3370374 Update V8 to version 3.0 (re-land r5920). 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5922 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-12-07 11:31:57 +00:00
kasperl@chromium.org
51b494d096 Revert r5920. Will re-land shortly. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5921 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-12-07 11:01:02 +00:00
kasperl@chromium.org
e5860bd6a8 Update V8 to version 3.0. 
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5920 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-12-07 09:11:56 +00:00
whesse@chromium.org
66836efbba Add generated code to calculate Math.log and to search Transcendental cache for logs. Implemented on all platforms. 
Review URL: http://codereview.chromium.org/5437002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5912 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-12-02 11:20:44 +00:00
vegorov@chromium.org
746d72420c Improve positions recording for calls. 
Review URL: http://codereview.chromium.org/4469002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5768 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-11-04 15:12:03 +00:00
kmillikin@chromium.org
9c503a8330 Fix some inconsistent formatting. 
I noticed we sometimes had extra spaces before and after the "const"
keyword.  Probably the result of a search and replace gone wrong.

This is a whitespace only change.

Review URL: http://codereview.chromium.org/3427021

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5519 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-09-24 08:25:31 +00:00
ricow@chromium.org
240cee91e4 Add support for near labels. 
This change introduces near labels in the assembler, allowing us to
uptimize forward jumps (conditional and unconditional) if we can
guarantee that the jump is witin range -128 to +127.

I changed a large fractions of the existing Labels to NearLabels, and
left out cases where it was not immediately clear if it could be used
or not (not immediately clear means labels covering a large code
block, or used in function calls which we could potentially change to
accept near labels). 

Review URL: http://codereview.chromium.org/3388004

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5460 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-09-15 11:43:12 +00:00
antonm@chromium.org
9d6fd08276 Port faster callbacks invocation to x64. 
It's a port of http://code.google.com/p/v8/source/detail?r=3209 to x64 platform.
That allows invocation of callbacks without going into runtime.

Review URL: http://codereview.chromium.org/2801008

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5141 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-07-28 09:36:53 +00:00
lrn@chromium.org
40d86c616c X64: Remove more fpu code. Unroll more local initialization loops. 
Review URL: http://codereview.chromium.org/2815028

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4934 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-24 09:03:49 +00:00
lrn@chromium.org
0dee9a7942 X64: Change some fpu operations to use XMM registers. 
Review URL: http://codereview.chromium.org/2827022

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4930 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-23 14:05:18 +00:00
lrn@chromium.org
a2fc244de2 X64: A bunch of small fixes. 
Make push/pop use emit_optional_rex32.
Fix bug in disassembler (swapped name of comisd/ucomisd).
Use fstp in FCmp macro.

Review URL: http://codereview.chromium.org/2818026

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4928 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-23 11:48:30 +00:00
lrn@chromium.org
2bd8d3323b X64: Change strategy for spilling to match ia32. It's just better. 
Align deferred code blocks to 16-byte address boundaries.

Review URL: http://codereview.chromium.org/2855018

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4914 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-22 10:07:57 +00:00
lrn@chromium.org
26e692af2f X64: Change some smi operations to work on untagged integers instead. 
Use direct reading and writing of integers from Smi fields.
Change RecordWrite with 0 offset to take untagged index instead of
smi tagged index.

Review URL: http://codereview.chromium.org/2872005

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4893 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-17 15:48:43 +00:00
ager@chromium.org
6702ace935 Move definition of NegateConditon from assembler*-inl.h files to 
assembler*.h files to make clang happy. There was no reason for having
the definition in the -inl.h files in the first place.

Review URL: http://codereview.chromium.org/2825008

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4888 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-17 08:41:48 +00:00
ager@chromium.org
2043956c54 Remove the comisd instruction from the ia32 and x64 assemblers. We 
should always use ucomisd.

Add missing pop from floating-point stack in case of allocation failure.
Review URL: http://codereview.chromium.org/2831009

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4878 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-16 12:32:34 +00:00
sgjesse@chromium.org
634fb9152c More precise break points and stepping when debugging 
Added support for more precise break points when debugging and stepping. To achieve that additional nop instructions are inserted where breaking would otherwise be impossible. The number of nop instructions inserted are sufficient to make place for patching with a call to a debug break code stub. On Intel that is 5 nop's for 32-bit and 13 for 64-bit. Om ARM 3 nop instructions (12 bytes) are required.

In order to avoid inserting nop's in to many places a simple ast checker have been added to check whether there are breakable code in a statement or expression. If it is possible to break in an expression no additional break enabeling code is inserted.

Added break locations to the true and false part of a conditional expression.

Added stepping tests to cover more constructs.

These changes are only in the full compiler.

Changed the default value for the option --debugger in teh d8 shell from true to false. The reason for this is that with --debugger turned on the full compiler will be used for all code in when running d8, which can be unexpeceted.

Review URL: http://codereview.chromium.org/2693002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4820 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-06-08 12:04:49 +00:00
lrn@chromium.org
7bfe569088 X64: Many small tweaks and more usages of "load smi as int32". 
Review URL: http://codereview.chromium.org/2266003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4739 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-05-27 10:25:33 +00:00
lrn@chromium.org
4afc3d3c4f X64: Make smi memory operations work directly on the embedded value. 
Adds Operand-relative Operand constructor.

Review URL: http://codereview.chromium.org/2242002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4725 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-05-26 10:02:07 +00:00
lrn@chromium.org
7410865adb X64: Make all arithmetic ops, and a few other, try to avoid rsp and r12 as base register. 
Using rsp or r12 as the "base" register of the ModR/M byte forces a SIB byte,
even with no index register. Some operations can avoid this by using another,
equivalent, encoding that swaps the meaning of the base and register parts.

Review URL: http://codereview.chromium.org/2075010

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4678 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-05-19 08:16:52 +00:00
lrn@chromium.org
44fb6cc8d3 X64: Made bit-fiddling fallback for double-to-int32 conversion. 
Review URL: http://codereview.chromium.org/2048007

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4648 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-05-12 11:16:35 +00:00
lrn@chromium.org
9f859fef26 Make X64 double-to-int32 conversion use the 64-bit version of cvttsd2si. 
Use type info to allow ia32 to use the 32-bit versions in some cases.
Remove sse3-specific code from X64 GenericBinaryOpStub.

Review URL: http://codereview.chromium.org/1992011

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4632 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-05-10 11:38:58 +00:00
lrn@chromium.org
1790c3534a X64: Port inline transcendental cache to X64. 
Review URL: http://codereview.chromium.org/1860001

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4567 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-05-03 10:43:49 +00:00
ager@chromium.org
62e8d5a789 Port inline version of Math.sqrt and Math.pow from ia32 to x64. 
Review URL: http://codereview.chromium.org/1774010

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4541 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-04-28 14:43:51 +00:00
whesse@chromium.org
a8e817161a Optimize the assembly code generated for Math.random() 
Review URL: http://codereview.chromium.org/1631008

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4384 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-04-12 10:07:50 +00:00
ager@chromium.org
a8a7a74bb3 Fix presubmit errors. 
I will lint my code, I will lint my code, I will lint my code. :)

TBR=sgjesse@chromium.org
Review URL: http://codereview.chromium.org/1115007

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4193 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-03-19 12:53:55 +00:00
ager@chromium.org
1bf60267e7 Port number-dictionary probing in generated code to x64. 
BUG=640
Review URL: http://codereview.chromium.org/1113001

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4192 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-03-19 12:26:45 +00:00
whesse@chromium.org
df9544d598 Declare register names as constants in assembler-x64.h. Fix for issue 615. 
Review URL: http://codereview.chromium.org/650136

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3924 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-02-22 11:41:52 +00:00
sgjesse@chromium.org
f937e7daa5 Fix array allocation in generated code on x64 
The porting of array allocation in generated code from ia32 to x64 wrongly assumed that a smi contained the actual number times 2. Removed the constant times_half_pointer_size, as it will probably not be needed.
Review URL: http://codereview.chromium.org/596084

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3845 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-02-12 13:49:57 +00:00
lrn@chromium.org
96127b68e5 Ported ia32 optimization of revision 3487 to x64. 
Review URL: http://codereview.chromium.org/597005

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3821 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-02-09 13:10:32 +00:00
sgjesse@chromium.org
9b4312fd76 Fixed random style violations. 
Review URL: http://codereview.chromium.org/574009

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3801 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
 2010-02-04 21:32:02 +00:00