Commit Graph

20 Commits

Author SHA1 Message Date
erik.corry@gmail.com
66d13be5f9 Fix incorrect encoding of single and double precision registers for some VFP instructions. Also fix incorrect disassembling of vldr/vstr. This is a commit of http://codereview.chromium.org/3107027 for Rodolph Perfetta.
git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5352 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-08-26 08:53:00 +00:00
erik.corry@gmail.com
8c767e02f9 ARM: Add support for the VFP mov literal instruction and mov
between single VFP registers.  Math.pow implementation has
been updated with the new instructions.  This is a commit
of http://codereview.chromium.org/2813046/show for Rodolph
Perfetta.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@5037 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-07-08 12:38:02 +00:00
erik.corry@gmail.com
53340b2624 Add movw and movt support for ARMv7. This includes some code from
Zhang Kun.  For now we only emit movw and movt in places where no
relocation is needed.  Small performance boost (around 0.5%).
Also adds support for turning ALU operations (eor etc.) with
large immediates into mvn or movw followed by a register-based
ALU operation.
Review URL: http://codereview.chromium.org/2821014

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4913 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-06-22 08:38:32 +00:00
sgjesse@chromium.org
58ea4c20cd ARM: Default to use unaligned accesses in the simulator
Support building with or without unaligned accesses by using scons flag simulatorunalignedaccesses.

$ scons simulator=arm simulatorunalignedaccesses=off
$ scons simulator=arm simulatorunalignedaccesses=on

If simulatorunalignedaccesses is not specified (or specified as default) the default is to use unaligned accesses.
Review URL: http://codereview.chromium.org/2218003

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4737 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-05-27 07:31:10 +00:00
erik.corry@gmail.com
6a03e12123 Allow unaligned memory accesses on ARM targets that support it.
The build process must add -DCAN_USE_UNALIGNED_ACCESSES=1 to the
C++ flags to activate the support.  This is a commit for
Subrato of CodeAurora.  See http://codereview.chromium.org/1731013
Small edits by Erik Corry to activate unaligned accesses by
default on the simulator and testing Android builds.


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4604 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-05-06 12:49:12 +00:00
sgjesse@chromium.org
de69f5beba Add support for bkpt instruction
The bkpt instruction is now supported by both the disassembler and the simulator. In the simulator it breaks to the native debugger if any like int3 on Intel.

Moved the handling of the miscellaneous instructions to a separate part.

Review URL: http://codereview.chromium.org/1576026


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4360 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-04-08 13:30:48 +00:00
vegorov@chromium.org
b7833cb5f1 Port of optimized ICs for external and pixel arrays from ia32 to ARM.
Review URL: http://codereview.chromium.org/993002

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4228 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-03-23 13:38:04 +00:00
erik.corry@gmail.com
1b7df23f7c Implement function calls on ARM using the blx instruction when
available. Using blx will allow the CPU to predict the return address
fo the function, resulting in better overall performamce.
This is a copy of http://codereview.chromium.org/1113002 by
rodolph.perfetta@googlemail.com

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4198 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-03-19 14:05:11 +00:00
whesse@chromium.org
f88e7e82b7 Add vstr and vldr floating point load and store to ARM assembler, disassembler, and simulator.
Review URL: http://codereview.chromium.org/545155

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3687 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2010-01-25 11:54:10 +00:00
erik.corry@gmail.com
059b9bbc5e Update with a hopefully complete list of macros
used by gcc to indicate ARM architectures.
Review URL: http://codereview.chromium.org/440017

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3359 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-11-25 11:23:48 +00:00
erik.corry@gmail.com
b0b5dbadbd Fix bug 516 by recognizing yet another gcc macro that
indicates ARMv6.
Review URL: http://codereview.chromium.org/437056

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3356 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-11-25 09:55:49 +00:00
erik.corry@gmail.com
407816af39 Fix some style issues in the ARM code.
Also move a function into the macro assembler.
Fix some *& placement errors that had accumulated.
Review URL: http://codereview.chromium.org/385069

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3293 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-11-12 13:55:21 +00:00
erik.corry@gmail.com
0d94d7c785 Add vfp support on ARM. Patch from John Jozwiak.
Review URL: http://codereview.chromium.org/348019

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@3292 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-11-12 13:04:02 +00:00
erik.corry@gmail.com
fb2897bcf9 Clean up the ifdefs on ARM.
Ensure that we use ARMv5 instructions on ARMv6 and ARMv7 CPUs.
Review URL: http://codereview.chromium.org/206012

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2898 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-09-16 08:48:17 +00:00
sgjesse@chromium.org
3546e91bbc Refactor the register to name mapping in the ARM simulator.
Review URL: http://codereview.chromium.org/195024

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2847 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-09-09 07:01:20 +00:00
erik.corry@gmail.com
cea9476cf0 More changes to make the simulator run code that is for the ARM5 snapshot.
Review URL: http://codereview.chromium.org/150100

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2307 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-06-30 13:38:40 +00:00
erik.corry@gmail.com
6b2a49ff83 * Modify simulator and ARM code generator to avoid swi
instructions.  The intention is that the snapshots generated
by the simulator should be usable on the hardware.  Instead of
swi instructions we generate a branch to a swi instruction that
is not part of the snapshot.  The call/jump is patched up in
the same way as other external references when the snapshot
is deserialized.  This only works for EABI targets: on old ABI
targets we still emit some instructions not supported by the
simulator (fp coprocessor instructions).
Review URL: http://codereview.chromium.org/119036

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2127 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-06-09 09:26:53 +00:00
mikhail.naganov@gmail.com
30a0a7de43 Split nested namespaces declaration in two lines in accordance with C++ Style Guide.
This issue was raised by Brett Wilson while reviewing my changelist for readability. Craig Silverstein (one of C++ SG maintainers) confirmed that we should declare one namespace per line. Our way of namespaces closing seems not violating style guides (there is no clear agreement on it), so I left it intact.

Review URL: http://codereview.chromium.org/115756


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@2038 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-05-25 10:05:56 +00:00
deanm@chromium.org
eb906555fc Cleanup include guards:
- Fix some typos / guards that didn't match the filename.
- Fix some style inconsistencies.
- Add guards to files that were missing them.
- Add the directory name to the guard.

Review URL: http://codereview.chromium.org/99343


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@1845 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-05-04 13:36:43 +00:00
lrn@chromium.org
a4d756a1c8 Move backend specific files to separate directories.
Move ia32 and arm specific files to subdirectories to make it easier to add more backends.

Review URL: http://codereview.chromium.org/92068


git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@1782 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
2009-04-23 12:06:38 +00:00