2011-12-05 08:58:01 +00:00
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// Copyright 2011 the V8 project authors. All rights reserved.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above
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// copyright notice, this list of conditions and the following
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// disclaimer in the documentation and/or other materials provided
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// with the distribution.
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// * Neither the name of Google Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include <stdlib.h>
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2021-09-09 21:03:41 +00:00
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#include "src/base/vector.h"
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2019-05-21 09:30:15 +00:00
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#include "src/codegen/code-factory.h"
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#include "src/codegen/macro-assembler.h"
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2015-07-31 11:07:50 +00:00
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#include "src/debug/debug.h"
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2019-05-20 09:15:06 +00:00
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#include "src/diagnostics/disasm.h"
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#include "src/diagnostics/disassembler.h"
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2019-05-22 07:55:37 +00:00
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#include "src/execution/frames-inl.h"
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2021-09-09 21:03:41 +00:00
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#include "src/init/v8.h"
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2019-05-23 08:51:46 +00:00
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#include "src/objects/objects-inl.h"
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2021-09-09 21:03:41 +00:00
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#include "src/utils/ostreams.h"
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2014-06-03 08:12:43 +00:00
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#include "test/cctest/cctest.h"
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2011-12-05 08:58:01 +00:00
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2017-08-11 11:22:28 +00:00
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namespace v8 {
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namespace internal {
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2011-12-05 08:58:01 +00:00
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#define __ assm.
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TEST(DisasmX64) {
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2014-03-05 09:28:26 +00:00
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Isolate* isolate = CcTest::i_isolate();
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HandleScope scope(isolate);
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2016-09-12 06:24:06 +00:00
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v8::internal::byte buffer[8192];
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2019-01-16 18:29:52 +00:00
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Assembler assm(AssemblerOptions{},
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ExternalAssemblerBuffer(buffer, sizeof buffer));
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2021-09-15 17:44:42 +00:00
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// Some instructions are tested in DisasmX64CheckOutput.
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2011-12-05 08:58:01 +00:00
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// Calls
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Label L1, L2;
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__ bind(&L1);
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__ nop();
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__ call(&L1);
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__ call(&L2);
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__ nop();
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__ bind(&L2);
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2019-11-06 13:39:55 +00:00
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__ call(rcx);
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2011-12-05 08:58:01 +00:00
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__ nop();
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2019-11-04 10:01:19 +00:00
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Handle<Code> ic = BUILTIN_CODE(isolate, ArrayFrom);
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2011-12-05 08:58:01 +00:00
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__ call(ic, RelocInfo::CODE_TARGET);
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__ nop();
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__ jmp(&L1);
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2019-01-28 13:01:36 +00:00
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__ jmp(Operand(rbx, rcx, times_4, 10000));
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2011-12-05 08:58:01 +00:00
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__ jmp(ic, RelocInfo::CODE_TARGET);
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__ nop();
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Label Ljcc;
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__ nop();
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// long jumps
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__ j(overflow, &Ljcc);
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__ j(no_overflow, &Ljcc);
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__ j(below, &Ljcc);
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__ j(above_equal, &Ljcc);
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__ j(equal, &Ljcc);
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__ j(not_equal, &Ljcc);
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__ j(below_equal, &Ljcc);
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__ j(above, &Ljcc);
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__ j(sign, &Ljcc);
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__ j(not_sign, &Ljcc);
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__ j(parity_even, &Ljcc);
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__ j(parity_odd, &Ljcc);
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__ j(less, &Ljcc);
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__ j(greater_equal, &Ljcc);
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__ j(less_equal, &Ljcc);
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__ j(greater, &Ljcc);
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__ nop();
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__ bind(&Ljcc);
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// short jumps
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__ j(overflow, &Ljcc);
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__ j(no_overflow, &Ljcc);
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__ j(below, &Ljcc);
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__ j(above_equal, &Ljcc);
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__ j(equal, &Ljcc);
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__ j(not_equal, &Ljcc);
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__ j(below_equal, &Ljcc);
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__ j(above, &Ljcc);
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__ j(sign, &Ljcc);
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__ j(not_sign, &Ljcc);
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__ j(parity_even, &Ljcc);
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__ j(parity_odd, &Ljcc);
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__ j(less, &Ljcc);
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__ j(greater_equal, &Ljcc);
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__ j(less_equal, &Ljcc);
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__ j(greater, &Ljcc);
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2016-09-12 06:24:06 +00:00
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#define EMIT_SSE34_INSTR(instruction, notUsed1, notUsed2, notUsed3, notUsed4) \
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__ instruction(xmm5, xmm1); \
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__ instruction(xmm5, Operand(rdx, 4));
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2019-10-30 04:38:36 +00:00
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#define EMIT_SSE34_IMM_INSTR(instruction, notUsed1, notUsed2, notUsed3, \
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notUsed4) \
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__ instruction(rbx, xmm15, 0); \
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__ instruction(Operand(rax, 10), xmm0, 1);
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2013-10-15 12:51:58 +00:00
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{
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if (CpuFeatures::IsSupported(SSE4_1)) {
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CpuFeatureScope scope(&assm, SSE4_1);
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2016-05-19 19:52:59 +00:00
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__ insertps(xmm5, xmm1, 123);
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[wasm] Implement wasm x64 I16x8 Ops
- Add I16x8 Splat, ExtractLane, ReplaceLane, shift ops, Some BinOps and compare ops
- Add pshufhw, pshuflw in the assembler, disassembler
- Fix incorrect modrm for pextrw, this bug disregards the register allocated and always makes pextrw use rax.
- Fix pextrw disasm to take the 0 - 7 bits of the immediate instead of 0 - 3.
- Pextrw, pinsrw are in the assembler use 128 bit encodings, pextrw, pinsrw in the disassembler use legacy encodings, fix inconsistencies causing weird code gen when --print-code is used.
Review-Url: https://codereview.chromium.org/2767983002
Cr-Commit-Position: refs/heads/master@{#44664}
2017-04-17 18:47:46 +00:00
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__ pinsrw(xmm2, rcx, 1);
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2019-07-01 23:58:02 +00:00
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__ pextrq(r12, xmm0, 1);
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2015-03-05 09:22:26 +00:00
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__ pinsrd(xmm9, r9, 0);
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2016-05-19 19:52:59 +00:00
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__ pinsrd(xmm5, Operand(rax, 4), 1);
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2019-07-01 23:58:02 +00:00
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__ pinsrq(xmm9, r9, 0);
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__ pinsrq(xmm5, Operand(rax, 4), 1);
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2018-08-14 19:38:14 +00:00
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__ pblendw(xmm5, xmm1, 1);
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__ pblendw(xmm9, Operand(rax, 4), 1);
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2016-05-19 19:52:59 +00:00
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__ cmpps(xmm5, xmm1, 1);
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2016-08-03 15:23:57 +00:00
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__ cmpps(xmm5, Operand(rbx, rcx, times_4, 10000), 1);
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2016-05-19 19:52:59 +00:00
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__ cmpeqps(xmm5, xmm1);
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2016-08-03 15:23:57 +00:00
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__ cmpeqps(xmm5, Operand(rbx, rcx, times_4, 10000));
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2016-05-19 19:52:59 +00:00
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__ cmpltps(xmm5, xmm1);
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2016-08-03 15:23:57 +00:00
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__ cmpltps(xmm5, Operand(rbx, rcx, times_4, 10000));
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2016-05-19 19:52:59 +00:00
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__ cmpleps(xmm5, xmm1);
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2016-08-03 15:23:57 +00:00
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__ cmpleps(xmm5, Operand(rbx, rcx, times_4, 10000));
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2021-04-14 23:04:50 +00:00
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__ cmpunordps(xmm5, xmm1);
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__ cmpunordps(xmm5, Operand(rbx, rcx, times_4, 10000));
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2016-05-19 19:52:59 +00:00
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__ cmpneqps(xmm5, xmm1);
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2016-08-03 15:23:57 +00:00
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__ cmpneqps(xmm5, Operand(rbx, rcx, times_4, 10000));
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2016-05-19 19:52:59 +00:00
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__ cmpnltps(xmm5, xmm1);
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2016-08-03 15:23:57 +00:00
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__ cmpnltps(xmm5, Operand(rbx, rcx, times_4, 10000));
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2016-05-19 19:52:59 +00:00
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__ cmpnleps(xmm5, xmm1);
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2016-08-03 15:23:57 +00:00
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__ cmpnleps(xmm5, Operand(rbx, rcx, times_4, 10000));
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__ cmppd(xmm5, xmm1, 1);
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__ cmppd(xmm5, Operand(rbx, rcx, times_4, 10000), 1);
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__ cmpeqpd(xmm5, xmm1);
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__ cmpeqpd(xmm5, Operand(rbx, rcx, times_4, 10000));
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__ cmpltpd(xmm5, xmm1);
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__ cmpltpd(xmm5, Operand(rbx, rcx, times_4, 10000));
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__ cmplepd(xmm5, xmm1);
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__ cmplepd(xmm5, Operand(rbx, rcx, times_4, 10000));
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2021-04-14 23:04:50 +00:00
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__ cmpunordpd(xmm5, xmm1);
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__ cmpunordpd(xmm5, Operand(rbx, rcx, times_4, 10000));
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2016-08-03 15:23:57 +00:00
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__ cmpneqpd(xmm5, xmm1);
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__ cmpneqpd(xmm5, Operand(rbx, rcx, times_4, 10000));
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__ cmpnltpd(xmm5, xmm1);
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__ cmpnltpd(xmm5, Operand(rbx, rcx, times_4, 10000));
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__ cmpnlepd(xmm5, xmm1);
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__ cmpnlepd(xmm5, Operand(rbx, rcx, times_4, 10000));
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2016-05-19 19:52:59 +00:00
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__ movups(xmm5, xmm1);
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__ movups(xmm5, Operand(rdx, 4));
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__ movups(Operand(rdx, 4), xmm5);
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__ pmulld(xmm5, xmm1);
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__ pmulld(xmm5, Operand(rdx, 4));
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2016-09-12 06:24:06 +00:00
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__ pmullw(xmm5, xmm1);
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__ pmullw(xmm5, Operand(rdx, 4));
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2016-05-19 19:52:59 +00:00
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__ pmuludq(xmm5, xmm1);
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__ pmuludq(xmm5, Operand(rdx, 4));
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__ psrldq(xmm5, 123);
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__ pshufd(xmm5, xmm1, 3);
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__ cvtps2dq(xmm5, xmm1);
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__ cvtps2dq(xmm5, Operand(rdx, 4));
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__ cvtdq2ps(xmm5, xmm1);
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__ cvtdq2ps(xmm5, Operand(rdx, 4));
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2020-10-28 02:43:49 +00:00
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__ pblendvb(xmm5, xmm1);
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__ blendvps(xmm5, xmm1);
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__ blendvps(xmm5, Operand(rdx, 4));
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2020-01-10 17:54:44 +00:00
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__ blendvpd(xmm5, xmm1);
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__ blendvpd(xmm5, Operand(rdx, 4));
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2016-09-12 06:24:06 +00:00
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2020-06-02 21:11:49 +00:00
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__ roundps(xmm8, xmm3, kRoundUp);
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2020-06-08 16:45:43 +00:00
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__ roundpd(xmm8, xmm3, kRoundToNearest);
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2020-04-06 16:44:23 +00:00
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__ roundss(xmm8, xmm3, kRoundDown);
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__ roundsd(xmm8, xmm3, kRoundDown);
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2016-09-12 06:24:06 +00:00
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SSE4_INSTRUCTION_LIST(EMIT_SSE34_INSTR)
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2020-02-27 08:45:39 +00:00
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SSE4_UNOP_INSTRUCTION_LIST(EMIT_SSE34_INSTR)
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2019-10-30 04:38:36 +00:00
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SSE4_EXTRACT_INSTRUCTION_LIST(EMIT_SSE34_IMM_INSTR)
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2013-10-15 12:51:58 +00:00
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}
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}
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2019-07-16 08:50:27 +00:00
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{
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if (CpuFeatures::IsSupported(SSE4_2)) {
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CpuFeatureScope scope(&assm, SSE4_2);
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SSE4_2_INSTRUCTION_LIST(EMIT_SSE34_INSTR)
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}
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}
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2016-09-12 06:24:06 +00:00
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#undef EMIT_SSE34_INSTR
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2019-10-30 04:38:36 +00:00
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#undef EMIT_SSE34_IMM_INSTR
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2013-10-15 12:51:58 +00:00
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2014-12-01 10:45:02 +00:00
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// AVX instruction
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{
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if (CpuFeatures::IsSupported(AVX)) {
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CpuFeatureScope scope(&assm, AVX);
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2015-10-20 04:58:07 +00:00
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__ vmovss(xmm6, xmm14, xmm2);
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__ vmovss(xmm9, Operand(rbx, rcx, times_4, 10000));
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__ vmovss(Operand(rbx, rcx, times_4, 10000), xmm0);
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2015-03-30 07:33:46 +00:00
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__ vaddss(xmm0, xmm1, xmm2);
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__ vaddss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
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__ vmulss(xmm0, xmm1, xmm2);
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__ vmulss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
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__ vsubss(xmm0, xmm1, xmm2);
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__ vsubss(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
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__ vdivss(xmm0, xmm1, xmm2);
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__ vdivss(xmm0, xmm1, Operand(rbx, rcx, times_2, 10000));
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__ vminss(xmm8, xmm1, xmm2);
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__ vminss(xmm9, xmm1, Operand(rbx, rcx, times_8, 10000));
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__ vmaxss(xmm8, xmm1, xmm2);
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__ vmaxss(xmm9, xmm1, Operand(rbx, rcx, times_1, 10000));
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2018-03-03 08:53:21 +00:00
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__ vsqrtss(xmm8, xmm1, xmm2);
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__ vsqrtss(xmm9, xmm1, Operand(rbx, rcx, times_1, 10000));
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2015-10-19 20:35:17 +00:00
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__ vmovss(xmm9, Operand(r11, rcx, times_8, -10000));
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__ vmovss(Operand(rbx, r9, times_4, 10000), xmm1);
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2015-03-30 07:33:46 +00:00
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__ vucomiss(xmm9, xmm1);
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__ vucomiss(xmm8, Operand(rbx, rdx, times_2, 10981));
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2015-10-16 05:20:31 +00:00
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__ vmovd(xmm5, rdi);
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__ vmovd(xmm9, Operand(rbx, rcx, times_4, 10000));
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|
|
__ vmovd(r9, xmm6);
|
|
|
|
|
__ vmovq(xmm5, rdi);
|
|
|
|
|
__ vmovq(xmm9, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vmovq(r9, xmm6);
|
|
|
|
|
|
2015-10-20 04:58:07 +00:00
|
|
|
__ vmovsd(xmm6, xmm14, xmm2);
|
2015-10-15 04:14:31 +00:00
|
|
|
__ vmovsd(xmm9, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vmovsd(Operand(rbx, rcx, times_4, 10000), xmm0);
|
|
|
|
|
|
2020-12-29 00:47:14 +00:00
|
|
|
__ vmovdqa(xmm4, xmm5);
|
2021-01-26 01:33:12 +00:00
|
|
|
__ vmovdqa(xmm4, Operand(rbx, rcx, times_4, 10000));
|
2021-09-07 22:14:40 +00:00
|
|
|
__ vmovdqa(ymm4, ymm5);
|
|
|
|
|
__ vmovdqa(xmm4, Operand(rbx, rcx, times_4, 10000));
|
2020-12-29 00:47:14 +00:00
|
|
|
|
2019-10-18 23:58:10 +00:00
|
|
|
__ vmovdqu(xmm9, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vmovdqu(Operand(rbx, rcx, times_4, 10000), xmm0);
|
2020-12-29 00:47:14 +00:00
|
|
|
__ vmovdqu(xmm4, xmm5);
|
2021-09-07 22:14:40 +00:00
|
|
|
__ vmovdqu(ymm9, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vmovdqu(Operand(rbx, rcx, times_4, 10000), ymm0);
|
|
|
|
|
__ vmovdqu(ymm4, ymm5);
|
2019-10-18 23:58:10 +00:00
|
|
|
|
2020-12-14 23:12:42 +00:00
|
|
|
__ vmovhlps(xmm1, xmm3, xmm5);
|
2020-10-14 16:33:41 +00:00
|
|
|
__ vmovlps(xmm8, xmm9, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vmovlps(Operand(rbx, rcx, times_4, 10000), xmm9);
|
2020-12-14 23:12:42 +00:00
|
|
|
__ vmovlhps(xmm1, xmm3, xmm5);
|
2020-10-14 16:33:41 +00:00
|
|
|
__ vmovhps(xmm8, xmm9, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vmovhps(Operand(rbx, rcx, times_4, 10000), xmm12);
|
|
|
|
|
|
2020-06-02 21:11:49 +00:00
|
|
|
__ vroundps(xmm9, xmm2, kRoundUp);
|
2020-06-08 16:45:43 +00:00
|
|
|
__ vroundpd(xmm9, xmm2, kRoundToNearest);
|
2020-01-10 17:55:04 +00:00
|
|
|
__ vroundss(xmm9, xmm1, xmm2, kRoundDown);
|
2015-10-23 07:48:54 +00:00
|
|
|
__ vroundsd(xmm8, xmm3, xmm0, kRoundDown);
|
2015-03-30 07:33:46 +00:00
|
|
|
__ vucomisd(xmm9, xmm1);
|
|
|
|
|
__ vucomisd(xmm8, Operand(rbx, rdx, times_2, 10981));
|
2015-10-18 15:43:07 +00:00
|
|
|
|
2021-01-27 22:01:46 +00:00
|
|
|
__ vcvtdq2pd(xmm9, xmm11);
|
2015-10-18 16:11:11 +00:00
|
|
|
__ vcvtss2sd(xmm4, xmm9, xmm11);
|
|
|
|
|
__ vcvtss2sd(xmm4, xmm9, Operand(rbx, rcx, times_1, 10000));
|
2020-03-03 04:46:45 +00:00
|
|
|
__ vcvttps2dq(xmm4, xmm11);
|
2015-10-15 17:50:03 +00:00
|
|
|
__ vcvtlsi2sd(xmm5, xmm9, rcx);
|
|
|
|
|
__ vcvtlsi2sd(xmm9, xmm3, Operand(rbx, r9, times_4, 10000));
|
2015-10-24 16:49:35 +00:00
|
|
|
__ vcvtqsi2sd(xmm5, xmm9, r11);
|
2015-10-18 15:43:07 +00:00
|
|
|
__ vcvttsd2si(r9, xmm6);
|
|
|
|
|
__ vcvttsd2si(rax, Operand(rbx, r9, times_4, 10000));
|
|
|
|
|
__ vcvttsd2siq(rdi, xmm9);
|
|
|
|
|
__ vcvttsd2siq(r8, Operand(r9, rbx, times_4, 10000));
|
2015-10-24 18:55:27 +00:00
|
|
|
__ vcvtsd2si(rdi, xmm9);
|
2015-04-11 01:02:22 +00:00
|
|
|
|
2015-10-20 04:58:07 +00:00
|
|
|
__ vmovaps(xmm10, xmm11);
|
2021-01-26 01:33:12 +00:00
|
|
|
__ vmovaps(xmm0, Operand(rbx, rcx, times_4, 10000));
|
2015-10-18 16:12:24 +00:00
|
|
|
__ vmovapd(xmm7, xmm0);
|
2016-07-21 11:01:44 +00:00
|
|
|
__ vmovupd(xmm0, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vmovupd(Operand(rbx, rcx, times_4, 10000), xmm0);
|
2015-10-18 16:12:24 +00:00
|
|
|
__ vmovmskpd(r9, xmm4);
|
2020-04-06 16:42:49 +00:00
|
|
|
__ vpmovmskb(r10, xmm9);
|
2015-10-18 16:12:24 +00:00
|
|
|
|
2016-07-11 18:18:17 +00:00
|
|
|
__ vmovups(xmm5, xmm1);
|
|
|
|
|
__ vmovups(xmm5, Operand(rdx, 4));
|
|
|
|
|
__ vmovups(Operand(rdx, 4), xmm5);
|
|
|
|
|
|
2015-04-11 01:02:22 +00:00
|
|
|
__ vandps(xmm0, xmm9, xmm2);
|
|
|
|
|
__ vandps(xmm9, xmm1, Operand(rbx, rcx, times_4, 10000));
|
2019-03-21 20:30:49 +00:00
|
|
|
__ vandnps(xmm0, xmm9, xmm2);
|
|
|
|
|
__ vandnps(xmm9, xmm1, Operand(rbx, rcx, times_4, 10000));
|
2015-04-11 01:02:22 +00:00
|
|
|
__ vxorps(xmm0, xmm1, xmm9);
|
|
|
|
|
__ vxorps(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
|
2018-02-28 06:28:08 +00:00
|
|
|
__ vhaddps(xmm0, xmm1, xmm9);
|
|
|
|
|
__ vhaddps(xmm0, xmm1, Operand(rbx, rcx, times_4, 10000));
|
2021-10-01 20:35:37 +00:00
|
|
|
__ vhaddps(ymm0, ymm1, ymm2);
|
|
|
|
|
__ vhaddps(ymm0, ymm1, Operand(rbx, rcx, times_4, 10000));
|
2015-04-11 01:02:22 +00:00
|
|
|
|
2015-10-22 07:00:57 +00:00
|
|
|
__ vpcmpeqd(xmm0, xmm15, xmm5);
|
|
|
|
|
__ vpcmpeqd(xmm15, xmm0, Operand(rbx, rcx, times_4, 10000));
|
2016-08-03 15:23:57 +00:00
|
|
|
|
|
|
|
|
__ vcmpps(xmm5, xmm4, xmm1, 1);
|
|
|
|
|
__ vcmpps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000), 1);
|
|
|
|
|
__ vcmpeqps(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpeqps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vcmpltps(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpltps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vcmpleps(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpleps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
2021-04-14 23:04:50 +00:00
|
|
|
__ vcmpunordps(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpunordps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
2016-08-03 15:23:57 +00:00
|
|
|
__ vcmpneqps(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpneqps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vcmpnltps(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpnltps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vcmpnleps(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpnleps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
2021-09-07 19:21:09 +00:00
|
|
|
__ vcmpgeps(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpgeps(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
2016-08-03 15:23:57 +00:00
|
|
|
__ vcmppd(xmm5, xmm4, xmm1, 1);
|
|
|
|
|
__ vcmppd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000), 1);
|
|
|
|
|
__ vcmpeqpd(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpeqpd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vcmpltpd(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpltpd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vcmplepd(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmplepd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
2021-04-14 23:04:50 +00:00
|
|
|
__ vcmpunordpd(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpunordpd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
2016-08-03 15:23:57 +00:00
|
|
|
__ vcmpneqpd(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpneqpd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vcmpnltpd(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpnltpd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vcmpnlepd(xmm5, xmm4, xmm1);
|
|
|
|
|
__ vcmpnlepd(xmm5, xmm4, Operand(rbx, rcx, times_4, 10000));
|
2016-09-12 06:24:06 +00:00
|
|
|
|
2019-11-25 19:26:01 +00:00
|
|
|
#define EMIT_SSE_UNOP_AVXINSTR(instruction, notUsed1, notUsed2) \
|
|
|
|
|
__ v##instruction(xmm10, xmm1); \
|
2021-09-07 22:14:40 +00:00
|
|
|
__ v##instruction(xmm10, Operand(rbx, rcx, times_4, 10000)); \
|
|
|
|
|
__ v##instruction(ymm10, ymm1); \
|
|
|
|
|
__ v##instruction(ymm10, Operand(rbx, rcx, times_4, 10000));
|
2019-11-25 19:26:01 +00:00
|
|
|
|
|
|
|
|
SSE_UNOP_INSTRUCTION_LIST(EMIT_SSE_UNOP_AVXINSTR)
|
|
|
|
|
#undef EMIT_SSE_UNOP_AVXINSTR
|
|
|
|
|
|
2021-09-07 22:14:40 +00:00
|
|
|
#define EMIT_SSE_BINOP_AVXINSTR(instruction, notUsed1, notUsed2) \
|
|
|
|
|
__ v##instruction(xmm10, xmm5, xmm1); \
|
|
|
|
|
__ v##instruction(xmm10, xmm5, Operand(rbx, rcx, times_4, 10000)); \
|
|
|
|
|
__ v##instruction(ymm10, ymm5, ymm1); \
|
|
|
|
|
__ v##instruction(ymm10, ymm5, Operand(rbx, rcx, times_4, 10000));
|
2019-11-25 19:26:01 +00:00
|
|
|
|
|
|
|
|
SSE_BINOP_INSTRUCTION_LIST(EMIT_SSE_BINOP_AVXINSTR)
|
|
|
|
|
#undef EMIT_SSE_BINOP_AVXINSTR
|
|
|
|
|
|
2016-09-12 06:24:06 +00:00
|
|
|
#define EMIT_SSE2_AVXINSTR(instruction, notUsed1, notUsed2, notUsed3) \
|
|
|
|
|
__ v##instruction(xmm10, xmm5, xmm1); \
|
|
|
|
|
__ v##instruction(xmm10, xmm5, Operand(rdx, 4));
|
|
|
|
|
|
Fix assembler for sqrtpd
The assembly of sqrtpd when using Sqrtpd macro was wrong, since
Sqrtpd(xmm1, xmm1) will incorrect generated vsqrtpd(xmm1, xmm1, xmm1),
which is nonsensical, since vsqrtpd only takes two operands. The
expected instruction should be vsqrtpd(xmm1, xmm0, xmm1) in terms of the
encoding, which is vsqrtpd(xmm1, xmm1).
So, move sqrtpd and cvtps2dq out into their own macro list, because
they have two operands in their AVX form, unlike the rest of the
instructions in SSE2_INSTRUCTION_LIST.
Also updated disasm and tests to use this new list.
Fixed: v8:10170
Change-Id: Ia9343c9a3ae64596bbc876744556e1dcea2a443b
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2032195
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#66088}
2020-01-31 18:28:11 +00:00
|
|
|
SSE2_INSTRUCTION_LIST(EMIT_SSE2_AVXINSTR)
|
|
|
|
|
#undef EMIT_SSE2_AVXINSTR
|
|
|
|
|
|
|
|
|
|
#define EMIT_SSE2_UNOP_AVXINSTR(instruction, notUsed1, notUsed2, notUsed3) \
|
|
|
|
|
__ v##instruction(xmm10, xmm1); \
|
|
|
|
|
__ v##instruction(xmm10, Operand(rdx, 4));
|
|
|
|
|
|
|
|
|
|
SSE2_UNOP_INSTRUCTION_LIST(EMIT_SSE2_UNOP_AVXINSTR)
|
|
|
|
|
#undef EMIT_SSE2_AVXINSTR
|
|
|
|
|
|
2020-02-03 22:51:57 +00:00
|
|
|
#define EMIT_SSE2_SD_AVXINSTR(instruction, notUsed1, notUsed2, notUsed3) \
|
|
|
|
|
__ v##instruction(xmm10, xmm5, xmm1); \
|
|
|
|
|
__ v##instruction(xmm10, xmm5, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
SSE2_INSTRUCTION_LIST_SD(EMIT_SSE2_SD_AVXINSTR)
|
|
|
|
|
#undef EMIT_SSE2_SD_AVXINSTR
|
|
|
|
|
|
2016-09-12 06:24:06 +00:00
|
|
|
#define EMIT_SSE34_AVXINSTR(instruction, notUsed1, notUsed2, notUsed3, \
|
|
|
|
|
notUsed4) \
|
|
|
|
|
__ v##instruction(xmm10, xmm5, xmm1); \
|
|
|
|
|
__ v##instruction(xmm10, xmm5, Operand(rdx, 4));
|
|
|
|
|
|
|
|
|
|
SSSE3_INSTRUCTION_LIST(EMIT_SSE34_AVXINSTR)
|
|
|
|
|
SSE4_INSTRUCTION_LIST(EMIT_SSE34_AVXINSTR)
|
2020-01-10 17:54:18 +00:00
|
|
|
SSE4_2_INSTRUCTION_LIST(EMIT_SSE34_AVXINSTR)
|
2016-09-12 06:24:06 +00:00
|
|
|
#undef EMIT_SSE34_AVXINSTR
|
|
|
|
|
|
2020-02-19 10:26:51 +00:00
|
|
|
#define EMIT_SSSE3_UNOP_AVXINSTR(instruction, notUsed1, notUsed2, notUsed3, \
|
|
|
|
|
notUsed4) \
|
|
|
|
|
__ v##instruction(xmm9, xmm3); \
|
|
|
|
|
__ v##instruction(xmm9, Operand(rdx, 5));
|
|
|
|
|
SSSE3_UNOP_INSTRUCTION_LIST(EMIT_SSSE3_UNOP_AVXINSTR)
|
|
|
|
|
#undef EMIT_SSSE3_UNOP_AVXINSTR
|
|
|
|
|
|
2020-01-06 18:51:23 +00:00
|
|
|
#define EMIT_SSE4_PMOV_AVXINSTR(instruction, notUsed1, notUsed2, notUsed3, \
|
|
|
|
|
notUsed4) \
|
|
|
|
|
__ v##instruction(xmm10, xmm1); \
|
|
|
|
|
__ v##instruction(xmm10, Operand(rdx, 4));
|
2020-02-27 08:45:39 +00:00
|
|
|
SSE4_UNOP_INSTRUCTION_LIST(EMIT_SSE4_PMOV_AVXINSTR)
|
2020-01-06 18:51:23 +00:00
|
|
|
#undef EMIT_SSE4_PMOV_AVXINSTR
|
|
|
|
|
|
2019-12-04 14:56:48 +00:00
|
|
|
#define EMIT_SSE2_SHIFT_IMM_AVX(instruction, notUsed1, notUsed2, notUsed3, \
|
|
|
|
|
notUsed4) \
|
|
|
|
|
__ v##instruction(xmm0, xmm15, 21);
|
|
|
|
|
SSE2_INSTRUCTION_LIST_SHIFT_IMM(EMIT_SSE2_SHIFT_IMM_AVX)
|
|
|
|
|
#undef EMIT_SSE2_SHIFT_IMM_AVX
|
|
|
|
|
|
2019-10-23 20:58:25 +00:00
|
|
|
__ vinsertps(xmm1, xmm2, xmm3, 1);
|
|
|
|
|
__ vinsertps(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 1);
|
|
|
|
|
__ vextractps(rax, xmm1, 1);
|
|
|
|
|
|
2016-09-12 06:24:06 +00:00
|
|
|
__ vlddqu(xmm1, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ vpextrb(rax, xmm2, 12);
|
|
|
|
|
__ vpextrb(Operand(rbx, rcx, times_4, 10000), xmm2, 12);
|
|
|
|
|
__ vpextrw(rax, xmm2, 5);
|
|
|
|
|
__ vpextrw(Operand(rbx, rcx, times_4, 10000), xmm2, 5);
|
|
|
|
|
__ vpextrd(rax, xmm2, 2);
|
|
|
|
|
__ vpextrd(Operand(rbx, rcx, times_4, 10000), xmm2, 2);
|
2020-01-07 23:16:33 +00:00
|
|
|
__ vpextrq(rax, xmm2, 2);
|
2016-09-12 06:24:06 +00:00
|
|
|
|
|
|
|
|
__ vpinsrb(xmm1, xmm2, rax, 12);
|
|
|
|
|
__ vpinsrb(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 12);
|
|
|
|
|
__ vpinsrw(xmm1, xmm2, rax, 5);
|
|
|
|
|
__ vpinsrw(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 5);
|
|
|
|
|
__ vpinsrd(xmm1, xmm2, rax, 2);
|
|
|
|
|
__ vpinsrd(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 2);
|
2019-12-04 11:15:11 +00:00
|
|
|
__ vpinsrq(xmm1, xmm2, rax, 9);
|
|
|
|
|
__ vpinsrq(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 9);
|
2016-09-12 06:24:06 +00:00
|
|
|
__ vpshufd(xmm1, xmm2, 85);
|
2020-03-20 00:05:30 +00:00
|
|
|
__ vpshufd(xmm1, Operand(rbx, rcx, times_4, 10000), 85);
|
2019-12-02 09:20:32 +00:00
|
|
|
__ vpshuflw(xmm1, xmm2, 85);
|
|
|
|
|
__ vpshuflw(xmm1, Operand(rbx, rcx, times_4, 10000), 85);
|
2020-03-20 00:05:30 +00:00
|
|
|
__ vpshufhw(xmm1, xmm2, 85);
|
|
|
|
|
__ vpshufhw(xmm1, Operand(rbx, rcx, times_4, 10000), 85);
|
2019-10-19 00:44:25 +00:00
|
|
|
__ vshufps(xmm3, xmm2, xmm3, 3);
|
2019-12-09 09:17:33 +00:00
|
|
|
__ vpblendw(xmm1, xmm2, xmm3, 23);
|
|
|
|
|
__ vpblendw(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 23);
|
2020-01-06 19:02:52 +00:00
|
|
|
__ vpalignr(xmm1, xmm2, xmm3, 4);
|
2020-08-25 17:15:47 +00:00
|
|
|
__ vpalignr(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 4);
|
2019-12-02 09:20:32 +00:00
|
|
|
|
2020-10-28 02:43:49 +00:00
|
|
|
__ vpblendvb(xmm1, xmm2, xmm3, xmm4);
|
|
|
|
|
__ vblendvps(xmm1, xmm2, xmm3, xmm4);
|
2020-01-10 17:54:44 +00:00
|
|
|
__ vblendvpd(xmm1, xmm2, xmm3, xmm4);
|
|
|
|
|
|
2019-12-04 11:15:11 +00:00
|
|
|
__ vmovddup(xmm1, xmm2);
|
2019-12-02 09:20:32 +00:00
|
|
|
__ vmovddup(xmm1, Operand(rbx, rcx, times_4, 10000));
|
2020-12-15 05:41:56 +00:00
|
|
|
__ vmovshdup(xmm1, xmm2);
|
2019-12-02 09:20:32 +00:00
|
|
|
__ vbroadcastss(xmm1, Operand(rbx, rcx, times_4, 10000));
|
2014-12-01 10:45:02 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2020-12-23 05:21:46 +00:00
|
|
|
// AVX2 instruction
|
|
|
|
|
{
|
|
|
|
|
if (CpuFeatures::IsSupported(AVX2)) {
|
|
|
|
|
CpuFeatureScope scope(&assm, AVX2);
|
|
|
|
|
__ vbroadcastss(xmm1, xmm2);
|
2020-12-23 01:06:45 +00:00
|
|
|
#define EMIT_AVX2_BROADCAST(instruction, notUsed1, notUsed2, notUsed3, \
|
|
|
|
|
notUsed4) \
|
|
|
|
|
__ instruction(xmm0, xmm1); \
|
|
|
|
|
__ instruction(xmm0, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
AVX2_BROADCAST_LIST(EMIT_AVX2_BROADCAST)
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2014-11-26 05:31:41 +00:00
|
|
|
// FMA3 instruction
|
|
|
|
|
{
|
|
|
|
|
if (CpuFeatures::IsSupported(FMA3)) {
|
|
|
|
|
CpuFeatureScope scope(&assm, FMA3);
|
2020-01-02 23:24:28 +00:00
|
|
|
#define EMIT_FMA(instr, notUsed1, notUsed2, notUsed3, notUsed4, notUsed5, \
|
|
|
|
|
notUsed6) \
|
|
|
|
|
__ instr(xmm9, xmm10, xmm11); \
|
|
|
|
|
__ instr(xmm9, xmm10, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
FMA_INSTRUCTION_LIST(EMIT_FMA)
|
|
|
|
|
#undef EMIT_FMA
|
2014-11-26 05:31:41 +00:00
|
|
|
}
|
|
|
|
|
}
|
2015-04-08 07:15:51 +00:00
|
|
|
|
|
|
|
|
// BMI1 instructions
|
|
|
|
|
{
|
|
|
|
|
if (CpuFeatures::IsSupported(BMI1)) {
|
|
|
|
|
CpuFeatureScope scope(&assm, BMI1);
|
|
|
|
|
__ andnq(rax, rbx, rcx);
|
|
|
|
|
__ andnq(rax, rbx, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ andnl(rax, rbx, rcx);
|
|
|
|
|
__ andnl(rax, rbx, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ bextrq(rax, rbx, rcx);
|
|
|
|
|
__ bextrq(rax, Operand(rbx, rcx, times_4, 10000), rbx);
|
|
|
|
|
__ bextrl(rax, rbx, rcx);
|
|
|
|
|
__ bextrl(rax, Operand(rbx, rcx, times_4, 10000), rbx);
|
|
|
|
|
__ blsiq(rax, rbx);
|
|
|
|
|
__ blsiq(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ blsil(rax, rbx);
|
|
|
|
|
__ blsil(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ blsmskq(rax, rbx);
|
|
|
|
|
__ blsmskq(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ blsmskl(rax, rbx);
|
|
|
|
|
__ blsmskl(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ blsrq(rax, rbx);
|
|
|
|
|
__ blsrq(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ blsrl(rax, rbx);
|
|
|
|
|
__ blsrl(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ tzcntq(rax, rbx);
|
|
|
|
|
__ tzcntq(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ tzcntl(rax, rbx);
|
|
|
|
|
__ tzcntl(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// LZCNT instructions
|
|
|
|
|
{
|
|
|
|
|
if (CpuFeatures::IsSupported(LZCNT)) {
|
|
|
|
|
CpuFeatureScope scope(&assm, LZCNT);
|
|
|
|
|
__ lzcntq(rax, rbx);
|
|
|
|
|
__ lzcntq(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ lzcntl(rax, rbx);
|
|
|
|
|
__ lzcntl(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// POPCNT instructions
|
|
|
|
|
{
|
|
|
|
|
if (CpuFeatures::IsSupported(POPCNT)) {
|
|
|
|
|
CpuFeatureScope scope(&assm, POPCNT);
|
|
|
|
|
__ popcntq(rax, rbx);
|
|
|
|
|
__ popcntq(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ popcntl(rax, rbx);
|
|
|
|
|
__ popcntl(rax, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// BMI2 instructions
|
|
|
|
|
{
|
|
|
|
|
if (CpuFeatures::IsSupported(BMI2)) {
|
|
|
|
|
CpuFeatureScope scope(&assm, BMI2);
|
|
|
|
|
__ bzhiq(rax, rbx, rcx);
|
|
|
|
|
__ bzhiq(rax, Operand(rbx, rcx, times_4, 10000), rbx);
|
|
|
|
|
__ bzhil(rax, rbx, rcx);
|
|
|
|
|
__ bzhil(rax, Operand(rbx, rcx, times_4, 10000), rbx);
|
|
|
|
|
__ mulxq(rax, rbx, rcx);
|
|
|
|
|
__ mulxq(rax, rbx, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ mulxl(rax, rbx, rcx);
|
|
|
|
|
__ mulxl(rax, rbx, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ pdepq(rax, rbx, rcx);
|
|
|
|
|
__ pdepq(rax, rbx, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ pdepl(rax, rbx, rcx);
|
|
|
|
|
__ pdepl(rax, rbx, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ pextq(rax, rbx, rcx);
|
|
|
|
|
__ pextq(rax, rbx, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ pextl(rax, rbx, rcx);
|
|
|
|
|
__ pextl(rax, rbx, Operand(rbx, rcx, times_4, 10000));
|
|
|
|
|
__ sarxq(rax, rbx, rcx);
|
|
|
|
|
__ sarxq(rax, Operand(rbx, rcx, times_4, 10000), rbx);
|
|
|
|
|
__ sarxl(rax, rbx, rcx);
|
|
|
|
|
__ sarxl(rax, Operand(rbx, rcx, times_4, 10000), rbx);
|
|
|
|
|
__ shlxq(rax, rbx, rcx);
|
|
|
|
|
__ shlxq(rax, Operand(rbx, rcx, times_4, 10000), rbx);
|
|
|
|
|
__ shlxl(rax, rbx, rcx);
|
|
|
|
|
__ shlxl(rax, Operand(rbx, rcx, times_4, 10000), rbx);
|
|
|
|
|
__ shrxq(rax, rbx, rcx);
|
|
|
|
|
__ shrxq(rax, Operand(rbx, rcx, times_4, 10000), rbx);
|
|
|
|
|
__ shrxl(rax, rbx, rcx);
|
|
|
|
|
__ shrxl(rax, Operand(rbx, rcx, times_4, 10000), rbx);
|
|
|
|
|
__ rorxq(rax, rbx, 63);
|
|
|
|
|
__ rorxq(rax, Operand(rbx, rcx, times_4, 10000), 63);
|
|
|
|
|
__ rorxl(rax, rbx, 31);
|
|
|
|
|
__ rorxl(rax, Operand(rbx, rcx, times_4, 10000), 31);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2014-07-30 13:54:45 +00:00
|
|
|
// xchg.
|
|
|
|
|
{
|
2016-05-19 00:55:08 +00:00
|
|
|
__ xchgb(rax, Operand(rax, 8));
|
|
|
|
|
__ xchgw(rax, Operand(rbx, 8));
|
2014-07-30 13:54:45 +00:00
|
|
|
__ xchgq(rax, rax);
|
|
|
|
|
__ xchgq(rax, rbx);
|
|
|
|
|
__ xchgq(rbx, rbx);
|
|
|
|
|
__ xchgq(rbx, Operand(rsp, 12));
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-19 00:55:08 +00:00
|
|
|
// cmpxchg.
|
|
|
|
|
{
|
|
|
|
|
__ cmpxchgb(Operand(rsp, 12), rax);
|
|
|
|
|
__ cmpxchgw(Operand(rbx, rcx, times_4, 10000), rax);
|
|
|
|
|
__ cmpxchgl(Operand(rbx, rcx, times_4, 10000), rax);
|
|
|
|
|
__ cmpxchgq(Operand(rbx, rcx, times_4, 10000), rax);
|
|
|
|
|
}
|
|
|
|
|
|
2020-01-20 17:33:17 +00:00
|
|
|
// xadd.
|
|
|
|
|
{
|
|
|
|
|
__ xaddb(Operand(rsp, 12), rax);
|
|
|
|
|
__ xaddw(Operand(rsp, 12), rax);
|
|
|
|
|
__ xaddl(Operand(rsp, 12), rax);
|
|
|
|
|
__ xaddq(Operand(rsp, 12), rax);
|
|
|
|
|
__ xaddb(Operand(rbx, rcx, times_4, 10000), rax);
|
|
|
|
|
__ xaddw(Operand(rbx, rcx, times_4, 10000), rax);
|
|
|
|
|
__ xaddl(Operand(rbx, rcx, times_4, 10000), rax);
|
|
|
|
|
__ xaddq(Operand(rbx, rcx, times_4, 10000), rax);
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-19 00:55:08 +00:00
|
|
|
// lock prefix.
|
|
|
|
|
{
|
|
|
|
|
__ lock();
|
|
|
|
|
__ cmpxchgl(Operand(rsp, 12), rbx);
|
|
|
|
|
|
|
|
|
|
__ lock();
|
|
|
|
|
__ xchgw(rax, Operand(rcx, 8));
|
|
|
|
|
}
|
|
|
|
|
|
2011-12-05 08:58:01 +00:00
|
|
|
// Nop instructions
|
|
|
|
|
for (int i = 0; i < 16; i++) {
|
|
|
|
|
__ Nop(i);
|
|
|
|
|
}
|
|
|
|
|
|
2019-07-18 09:10:30 +00:00
|
|
|
__ mfence();
|
|
|
|
|
__ lfence();
|
2018-05-09 15:02:15 +00:00
|
|
|
__ pause();
|
2011-12-05 08:58:01 +00:00
|
|
|
__ ret(0);
|
|
|
|
|
|
|
|
|
|
CodeDesc desc;
|
2017-05-31 14:00:11 +00:00
|
|
|
assm.GetCode(isolate, &desc);
|
Reland "Reland "[deoptimizer] Change deopt entries into builtins""
This is a reland of fbfa9bf4ec72b1b73a96b70ccb68cd98c321511b
The arm64 was missing proper codegen for CFI, thus sizes were off.
Original change's description:
> Reland "[deoptimizer] Change deopt entries into builtins"
>
> This is a reland of 7f58ced72eb65b6b5530ccabaf2eaebe45bf9d33
>
> It fixes the different exit size emitted on x64/Atom CPUs due to
> performance tuning in TurboAssembler::Call. Additionally, add
> cctests to verify the fixed size exits.
>
> Original change's description:
> > [deoptimizer] Change deopt entries into builtins
> >
> > While the overall goal of this commit is to change deoptimization
> > entries into builtins, there are multiple related things happening:
> >
> > - Deoptimization entries, formerly stubs (i.e. Code objects generated
> > at runtime, guaranteed to be immovable), have been converted into
> > builtins. The major restriction is that we now need to preserve the
> > kRootRegister, which was formerly used on most architectures to pass
> > the deoptimization id. The solution differs based on platform.
> > - Renamed DEOPT_ENTRIES_OR_FOR_TESTING code kind to FOR_TESTING.
> > - Removed heap/ support for immovable Code generation.
> > - Removed the DeserializerData class (no longer needed).
> > - arm64: to preserve 4-byte deopt exits, introduced a new optimization
> > in which the final jump to the deoptimization entry is generated
> > once per Code object, and deopt exits can continue to emit a
> > near-call.
> > - arm,ia32,x64: change to fixed-size deopt exits. This reduces exit
> > sizes by 4/8, 5, and 5 bytes, respectively.
> >
> > On arm the deopt exit size is reduced from 12 (or 16) bytes to 8 bytes
> > by using the same strategy as on arm64 (recalc deopt id from return
> > address). Before:
> >
> > e300a002 movw r10, <id>
> > e59fc024 ldr ip, [pc, <entry offset>]
> > e12fff3c blx ip
> >
> > After:
> >
> > e59acb35 ldr ip, [r10, <entry offset>]
> > e12fff3c blx ip
> >
> > On arm64 the deopt exit size remains 4 bytes (or 8 bytes in same cases
> > with CFI). Additionally, up to 4 builtin jumps are emitted per Code
> > object (max 32 bytes added overhead per Code object). Before:
> >
> > 9401cdae bl <entry offset>
> >
> > After:
> >
> > # eager deoptimization entry jump.
> > f95b1f50 ldr x16, [x26, <eager entry offset>]
> > d61f0200 br x16
> > # lazy deoptimization entry jump.
> > f95b2b50 ldr x16, [x26, <lazy entry offset>]
> > d61f0200 br x16
> > # the deopt exit.
> > 97fffffc bl <eager deoptimization entry jump offset>
> >
> > On ia32 the deopt exit size is reduced from 10 to 5 bytes. Before:
> >
> > bb00000000 mov ebx,<id>
> > e825f5372b call <entry>
> >
> > After:
> >
> > e8ea2256ba call <entry>
> >
> > On x64 the deopt exit size is reduced from 12 to 7 bytes. Before:
> >
> > 49c7c511000000 REX.W movq r13,<id>
> > e8ea2f0700 call <entry>
> >
> > After:
> >
> > 41ff9560360000 call [r13+<entry offset>]
> >
> > Bug: v8:8661,v8:8768
> > Change-Id: I13e30aedc360474dc818fecc528ce87c3bfeed42
> > Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2465834
> > Commit-Queue: Jakob Gruber <jgruber@chromium.org>
> > Reviewed-by: Ross McIlroy <rmcilroy@chromium.org>
> > Reviewed-by: Tobias Tebbi <tebbi@chromium.org>
> > Reviewed-by: Ulan Degenbaev <ulan@chromium.org>
> > Cr-Commit-Position: refs/heads/master@{#70597}
>
> Tbr: ulan@chromium.org, tebbi@chromium.org, rmcilroy@chromium.org
> Bug: v8:8661,v8:8768,chromium:1140165
> Change-Id: Ibcd5c39c58a70bf2b2ac221aa375fc68d495e144
> Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2485506
> Reviewed-by: Jakob Gruber <jgruber@chromium.org>
> Reviewed-by: Tobias Tebbi <tebbi@chromium.org>
> Commit-Queue: Jakob Gruber <jgruber@chromium.org>
> Cr-Commit-Position: refs/heads/master@{#70655}
Tbr: ulan@chromium.org, tebbi@chromium.org, rmcilroy@chromium.org
Bug: v8:8661
Bug: v8:8768
Bug: chromium:1140165
Change-Id: I471cc94fc085e527dc9bfb5a84b96bd907c2333f
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2488682
Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Commit-Queue: Jakob Gruber <jgruber@chromium.org>
Cr-Commit-Position: refs/heads/master@{#70672}
2020-10-21 05:12:25 +00:00
|
|
|
Handle<Code> code =
|
|
|
|
|
Factory::CodeBuilder(isolate, desc, CodeKind::FOR_TESTING).Build();
|
2014-04-16 11:50:24 +00:00
|
|
|
USE(code);
|
2011-12-05 08:58:01 +00:00
|
|
|
#ifdef OBJECT_PRINT
|
2018-06-14 12:46:07 +00:00
|
|
|
StdoutStream os;
|
2018-07-12 10:06:42 +00:00
|
|
|
code->Print(os);
|
2018-04-13 22:28:05 +00:00
|
|
|
Address begin = code->raw_instruction_start();
|
|
|
|
|
Address end = code->raw_instruction_end();
|
|
|
|
|
disasm::Disassembler::Disassemble(stdout, reinterpret_cast<byte*>(begin),
|
|
|
|
|
reinterpret_cast<byte*>(end));
|
2011-12-05 08:58:01 +00:00
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
2021-09-23 16:30:22 +00:00
|
|
|
constexpr int kAssemblerBufferSize = 8192;
|
|
|
|
|
|
|
|
|
|
// Helper to package up all the required classes for disassembling into a
|
|
|
|
|
// buffer using |InstructionDecode|.
|
|
|
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struct DisassemblerTester {
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DisassemblerTester()
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: assm_(AssemblerOptions{},
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ExternalAssemblerBuffer(buffer_, sizeof(buffer_))),
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disasm(converter_) {}
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std::string InstructionDecode() {
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disasm.InstructionDecode(disasm_buffer, buffer_ + prev_offset);
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return std::string{disasm_buffer.begin()};
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}
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int pc_offset() { return assm_.pc_offset(); }
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2021-10-01 20:35:37 +00:00
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Assembler* assm() { return &assm_; }
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2021-09-23 16:30:22 +00:00
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v8::internal::byte buffer_[kAssemblerBufferSize];
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Assembler assm_;
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disasm::NameConverter converter_;
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disasm::Disassembler disasm;
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base::EmbeddedVector<char, 128> disasm_buffer;
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int prev_offset = 0;
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};
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// Helper macro to compare the disassembly of an assembler function call with
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// the expected disassembly output. We reuse |Assembler|, so we need to keep
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// track of the offset into |buffer| which the Assembler has used, and
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// disassemble the instruction at that offset.
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// Requires a DisassemblerTester named t.
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#define COMPARE(str, ASM) \
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t.prev_offset = t.pc_offset(); \
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t.assm_.ASM; \
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CHECK_EQ(str, t.InstructionDecode());
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2021-09-09 21:03:41 +00:00
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// Tests that compares the checks the disassembly output with an expected
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// string.
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2021-09-14 21:01:51 +00:00
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UNINITIALIZED_TEST(DisasmX64CheckOutput) {
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2021-09-23 16:30:22 +00:00
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DisassemblerTester t;
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2021-09-09 21:03:41 +00:00
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2021-09-15 17:44:42 +00:00
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// Short immediate instructions
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2021-10-04 21:26:52 +00:00
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COMPARE("48054e61bc00 REX.W add rax,0xbc614e",
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2021-09-09 21:03:41 +00:00
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addq(rax, Immediate(12345678)));
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2021-10-04 21:26:52 +00:00
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COMPARE("480d4e61bc00 REX.W or rax,0xbc614e",
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2021-09-15 17:44:42 +00:00
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orq(rax, Immediate(12345678)));
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2021-10-04 21:26:52 +00:00
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COMPARE("482d4e61bc00 REX.W sub rax,0xbc614e",
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2021-09-15 17:44:42 +00:00
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subq(rax, Immediate(12345678)));
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2021-10-04 21:26:52 +00:00
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COMPARE("48354e61bc00 REX.W xor rax,0xbc614e",
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2021-09-15 17:44:42 +00:00
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xorq(rax, Immediate(12345678)));
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2021-10-04 21:26:52 +00:00
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COMPARE("48254e61bc00 REX.W and rax,0xbc614e",
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2021-09-15 17:44:42 +00:00
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andq(rax, Immediate(12345678)));
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2021-10-04 21:26:52 +00:00
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COMPARE("488b1c4c REX.W movq rbx,[rsp+rcx*2]",
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2021-09-15 17:44:42 +00:00
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movq(rbx, Operand(rsp, rcx, times_2, 0))); // [rsp+rcx*2);
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2021-10-04 21:26:52 +00:00
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COMPARE("4803d3 REX.W addq rdx,rbx", addq(rdx, rbx));
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COMPARE("480313 REX.W addq rdx,[rbx]",
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2021-09-15 17:44:42 +00:00
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addq(rdx, Operand(rbx, 0)));
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2021-10-04 21:26:52 +00:00
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COMPARE("48035310 REX.W addq rdx,[rbx+0x10]",
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2021-09-15 17:44:42 +00:00
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addq(rdx, Operand(rbx, 16)));
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2021-10-04 21:26:52 +00:00
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COMPARE("480393cf070000 REX.W addq rdx,[rbx+0x7cf]",
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2021-09-15 17:44:42 +00:00
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addq(rdx, Operand(rbx, 1999)));
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2021-10-04 21:26:52 +00:00
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COMPARE("480353fc REX.W addq rdx,[rbx-0x4]",
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2021-09-15 17:44:42 +00:00
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addq(rdx, Operand(rbx, -4)));
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2021-10-04 21:26:52 +00:00
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COMPARE("48039331f8ffff REX.W addq rdx,[rbx-0x7cf]",
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2021-09-15 17:44:42 +00:00
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addq(rdx, Operand(rbx, -1999)));
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2021-10-04 21:26:52 +00:00
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COMPARE("48031424 REX.W addq rdx,[rsp]",
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2021-09-15 17:44:42 +00:00
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addq(rdx, Operand(rsp, 0)));
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2021-10-04 21:26:52 +00:00
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COMPARE("4803542410 REX.W addq rdx,[rsp+0x10]",
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2021-09-15 17:44:42 +00:00
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addq(rdx, Operand(rsp, 16)));
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2021-10-04 21:26:52 +00:00
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COMPARE("48039424cf070000 REX.W addq rdx,[rsp+0x7cf]",
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2021-09-15 17:44:42 +00:00
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addq(rdx, Operand(rsp, 1999)));
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2021-10-04 21:26:52 +00:00
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COMPARE("48035424fc REX.W addq rdx,[rsp-0x4]",
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2021-09-15 17:44:42 +00:00
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addq(rdx, Operand(rsp, -4)));
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2021-10-04 21:26:52 +00:00
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COMPARE("4803942431f8ffff REX.W addq rdx,[rsp-0x7cf]",
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2021-09-15 17:44:42 +00:00
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addq(rdx, Operand(rsp, -1999)));
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2021-10-04 21:26:52 +00:00
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COMPARE("4803348d00000000 REX.W addq rsi,[rcx*4+0x0]",
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2021-09-15 17:44:42 +00:00
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addq(rsi, Operand(rcx, times_4, 0)));
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2021-10-04 21:26:52 +00:00
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COMPARE("4803348d18000000 REX.W addq rsi,[rcx*4+0x18]",
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2021-09-15 17:44:42 +00:00
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addq(rsi, Operand(rcx, times_4, 24)));
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2021-10-04 21:26:52 +00:00
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COMPARE("4803348dfcffffff REX.W addq rsi,[rcx*4-0x4]",
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2021-09-15 17:44:42 +00:00
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addq(rsi, Operand(rcx, times_4, -4)));
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2021-10-04 21:26:52 +00:00
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COMPARE("4803348d31f8ffff REX.W addq rsi,[rcx*4-0x7cf]",
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2021-09-15 17:44:42 +00:00
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addq(rsi, Operand(rcx, times_4, -1999)));
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2021-10-04 21:26:52 +00:00
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COMPARE("48037c8d00 REX.W addq rdi,[rbp+rcx*4+0x0]",
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2021-09-15 17:44:42 +00:00
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addq(rdi, Operand(rbp, rcx, times_4, 0)));
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2021-10-04 21:26:52 +00:00
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COMPARE("48037c8d0c REX.W addq rdi,[rbp+rcx*4+0xc]",
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2021-09-15 17:44:42 +00:00
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addq(rdi, Operand(rbp, rcx, times_4, 12)));
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2021-10-04 21:26:52 +00:00
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COMPARE("48037c8df8 REX.W addq rdi,[rbp+rcx*4-0x8]",
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2021-09-15 17:44:42 +00:00
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addq(rdi, Operand(rbp, rcx, times_4, -8)));
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2021-10-04 21:26:52 +00:00
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COMPARE("4803bc8d61f0ffff REX.W addq rdi,[rbp+rcx*4-0xf9f]",
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2021-09-15 17:44:42 +00:00
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addq(rdi, Operand(rbp, rcx, times_4, -3999)));
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2021-10-04 21:26:52 +00:00
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COMPARE("4883448d0c0c REX.W addq [rbp+rcx*4+0xc],0xc",
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2021-09-15 17:44:42 +00:00
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addq(Operand(rbp, rcx, times_4, 12), Immediate(12)));
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2021-10-04 21:26:52 +00:00
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COMPARE("400fc8 bswapl rax", bswapl(rax));
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COMPARE("480fcf REX.W bswapq rdi", bswapq(rdi));
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COMPARE("410fbdc7 bsrl rax,r15", bsrl(rax, r15));
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COMPARE("440fbd0ccd0f670100 bsrl r9,[rcx*8+0x1670f]",
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2021-09-15 17:44:42 +00:00
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bsrl(r9, Operand(rcx, times_8, 91919)));
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2021-10-04 21:26:52 +00:00
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COMPARE("90 nop", nop());
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COMPARE("4883c30c REX.W addq rbx,0xc", addq(rbx, Immediate(12)));
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COMPARE("4883e203 REX.W andq rdx,0x3", andq(rdx, Immediate(3)));
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COMPARE("4823542404 REX.W andq rdx,[rsp+0x4]",
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2021-09-15 17:44:42 +00:00
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andq(rdx, Operand(rsp, 4)));
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2021-10-04 21:26:52 +00:00
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COMPARE("4883fa03 REX.W cmpq rdx,0x3", cmpq(rdx, Immediate(3)));
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COMPARE("483b542404 REX.W cmpq rdx,[rsp+0x4]",
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2021-09-15 17:44:42 +00:00
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cmpq(rdx, Operand(rsp, 4)));
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2021-10-04 21:26:52 +00:00
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COMPARE("48817c8d00e8030000 REX.W cmpq [rbp+rcx*4+0x0],0x3e8",
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2021-09-15 17:44:42 +00:00
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cmpq(Operand(rbp, rcx, times_4, 0), Immediate(1000)));
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2021-10-04 21:26:52 +00:00
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COMPARE("3a5c4d00 cmpb bl,[rbp+rcx*2+0x0]",
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2021-09-15 17:44:42 +00:00
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cmpb(rbx, Operand(rbp, rcx, times_2, 0)));
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2021-10-04 21:26:52 +00:00
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COMPARE("385c4d00 cmpb [rbp+rcx*2+0x0],bl",
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2021-09-15 17:44:42 +00:00
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cmpb(Operand(rbp, rcx, times_2, 0), rbx));
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2021-10-04 21:26:52 +00:00
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COMPARE("4883ca03 REX.W orq rdx,0x3", orq(rdx, Immediate(3)));
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COMPARE("4883f203 REX.W xorq rdx,0x3", xorq(rdx, Immediate(3)));
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COMPARE("90 nop", nop());
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COMPARE("0fa2 cpuid", cpuid());
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COMPARE("0fbe11 movsxbl rdx,[rcx]",
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2021-09-15 17:44:42 +00:00
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movsxbl(rdx, Operand(rcx, 0)));
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2021-10-04 21:26:52 +00:00
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COMPARE("480fbe11 REX.W movsxbq rdx,[rcx]",
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2021-09-15 17:44:42 +00:00
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movsxbq(rdx, Operand(rcx, 0)));
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2021-10-04 21:26:52 +00:00
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COMPARE("0fbf11 movsxwl rdx,[rcx]",
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2021-09-15 17:44:42 +00:00
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movsxwl(rdx, Operand(rcx, 0)));
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2021-10-04 21:26:52 +00:00
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COMPARE("480fbf11 REX.W movsxwq rdx,[rcx]",
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2021-09-15 17:44:42 +00:00
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movsxwq(rdx, Operand(rcx, 0)));
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2021-10-04 21:26:52 +00:00
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COMPARE("0fb611 movzxbl rdx,[rcx]",
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2021-09-15 17:44:42 +00:00
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movzxbl(rdx, Operand(rcx, 0)));
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2021-10-04 21:26:52 +00:00
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COMPARE("0fb711 movzxwl rdx,[rcx]",
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2021-09-15 17:44:42 +00:00
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movzxwl(rdx, Operand(rcx, 0)));
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2021-10-04 21:26:52 +00:00
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COMPARE("0fb611 movzxbl rdx,[rcx]",
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2021-09-15 17:44:42 +00:00
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movzxbq(rdx, Operand(rcx, 0)));
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2021-10-04 21:26:52 +00:00
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COMPARE("0fb711 movzxwl rdx,[rcx]",
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2021-09-15 17:44:42 +00:00
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movzxwq(rdx, Operand(rcx, 0)));
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2021-10-04 21:26:52 +00:00
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COMPARE("480fafd1 REX.W imulq rdx,rcx", imulq(rdx, rcx));
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COMPARE("480fa5ca REX.W shld rdx,rcx,cl", shld(rdx, rcx));
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COMPARE("480fadca REX.W shrd rdx,rcx,cl", shrd(rdx, rcx));
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COMPARE("48d1648764 REX.W shlq [rdi+rax*4+0x64], 1",
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2021-09-15 17:44:42 +00:00
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shlq(Operand(rdi, rax, times_4, 100), Immediate(1)));
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2021-10-04 21:26:52 +00:00
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COMPARE("48c164876406 REX.W shlq [rdi+rax*4+0x64], 6",
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2021-09-15 17:44:42 +00:00
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shlq(Operand(rdi, rax, times_4, 100), Immediate(6)));
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2021-10-04 21:26:52 +00:00
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COMPARE("49d127 REX.W shlq [r15], 1",
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2021-09-15 17:44:42 +00:00
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shlq(Operand(r15, 0), Immediate(1)));
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2021-10-04 21:26:52 +00:00
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COMPARE("49c12706 REX.W shlq [r15], 6",
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2021-09-15 17:44:42 +00:00
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shlq(Operand(r15, 0), Immediate(6)));
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2021-10-04 21:26:52 +00:00
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COMPARE("49d327 REX.W shlq [r15], cl",
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shlq_cl(Operand(r15, 0)));
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COMPARE("49d327 REX.W shlq [r15], cl",
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shlq_cl(Operand(r15, 0)));
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COMPARE("48d3648764 REX.W shlq [rdi+rax*4+0x64], cl",
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2021-09-15 17:44:42 +00:00
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shlq_cl(Operand(rdi, rax, times_4, 100)));
|
2021-10-04 21:26:52 +00:00
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COMPARE("48d3648764 REX.W shlq [rdi+rax*4+0x64], cl",
|
2021-09-15 17:44:42 +00:00
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shlq_cl(Operand(rdi, rax, times_4, 100)));
|
2021-10-04 21:26:52 +00:00
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COMPARE("48d1e2 REX.W shlq rdx, 1", shlq(rdx, Immediate(1)));
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COMPARE("48c1e206 REX.W shlq rdx, 6", shlq(rdx, Immediate(6)));
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COMPARE("d1648764 shll [rdi+rax*4+0x64], 1",
|
2021-09-15 17:44:42 +00:00
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shll(Operand(rdi, rax, times_4, 100), Immediate(1)));
|
2021-10-04 21:26:52 +00:00
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COMPARE("c164876406 shll [rdi+rax*4+0x64], 6",
|
2021-09-15 17:44:42 +00:00
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|
shll(Operand(rdi, rax, times_4, 100), Immediate(6)));
|
2021-10-04 21:26:52 +00:00
|
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|
COMPARE("41d127 shll [r15], 1",
|
2021-09-15 17:44:42 +00:00
|
|
|
shll(Operand(r15, 0), Immediate(1)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("41c12706 shll [r15], 6",
|
2021-09-15 17:44:42 +00:00
|
|
|
shll(Operand(r15, 0), Immediate(6)));
|
2021-10-04 21:26:52 +00:00
|
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|
COMPARE("41d327 shll [r15], cl", shll_cl(Operand(r15, 0)));
|
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|
|
COMPARE("41d327 shll [r15], cl", shll_cl(Operand(r15, 0)));
|
|
|
|
|
COMPARE("d3648764 shll [rdi+rax*4+0x64], cl",
|
2021-09-15 17:44:42 +00:00
|
|
|
shll_cl(Operand(rdi, rax, times_4, 100)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("d3648764 shll [rdi+rax*4+0x64], cl",
|
2021-09-15 17:44:42 +00:00
|
|
|
shll_cl(Operand(rdi, rax, times_4, 100)));
|
2021-10-04 21:26:52 +00:00
|
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|
COMPARE("d1e2 shll rdx, 1", shll(rdx, Immediate(1)));
|
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|
|
COMPARE("c1e206 shll rdx, 6", shll(rdx, Immediate(6)));
|
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|
|
COMPARE("480fa30a REX.W bt [rdx],rcx,cl",
|
2021-09-15 17:44:42 +00:00
|
|
|
btq(Operand(rdx, 0), rcx));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("480fab0a REX.W bts [rdx],rcx",
|
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|
|
btsq(Operand(rdx, 0), rcx));
|
|
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|
COMPARE("480fab0c8b REX.W bts [rbx+rcx*4],rcx",
|
2021-09-15 17:44:42 +00:00
|
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|
btsq(Operand(rbx, rcx, times_4, 0), rcx));
|
2021-10-04 21:26:52 +00:00
|
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|
COMPARE("480fbae90d REX.W bts rcx,13", btsq(rcx, Immediate(13)));
|
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|
COMPARE("480fbaf10d REX.W btr rcx,13", btrq(rcx, Immediate(13)));
|
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|
COMPARE("6a0c push 0xc", pushq(Immediate(12)));
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|
COMPARE("68a05b0000 push 0x5ba0", pushq(Immediate(23456)));
|
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|
COMPARE("51 push rcx", pushq(rcx));
|
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|
COMPARE("56 push rsi", pushq(rsi));
|
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|
COMPARE("ff75f0 push [rbp-0x10]",
|
2021-09-15 17:44:42 +00:00
|
|
|
pushq(Operand(rbp, StandardFrameConstants::kFunctionOffset)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("ff348b push [rbx+rcx*4]",
|
2021-09-15 17:44:42 +00:00
|
|
|
pushq(Operand(rbx, rcx, times_4, 0)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("ff348b push [rbx+rcx*4]",
|
2021-09-15 17:44:42 +00:00
|
|
|
pushq(Operand(rbx, rcx, times_4, 0)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("ffb48b10270000 push [rbx+rcx*4+0x2710]",
|
2021-09-15 17:44:42 +00:00
|
|
|
pushq(Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("5a pop rdx", popq(rdx));
|
|
|
|
|
COMPARE("58 pop rax", popq(rax));
|
|
|
|
|
COMPARE("8f048b pop [rbx+rcx*4]",
|
2021-09-15 17:44:42 +00:00
|
|
|
popq(Operand(rbx, rcx, times_4, 0)));
|
|
|
|
|
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("4803542410 REX.W addq rdx,[rsp+0x10]",
|
2021-09-15 17:44:42 +00:00
|
|
|
addq(rdx, Operand(rsp, 16)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("4803d1 REX.W addq rdx,rcx", addq(rdx, rcx));
|
|
|
|
|
COMPARE("8a11 movb dl,[rcx]", movb(rdx, Operand(rcx, 0)));
|
|
|
|
|
COMPARE("b106 movb cl,6", movb(rcx, Immediate(6)));
|
|
|
|
|
COMPARE("88542410 movb [rsp+0x10],dl",
|
|
|
|
|
movb(Operand(rsp, 16), rdx));
|
|
|
|
|
COMPARE("6689542410 movw [rsp+0x10],rdx",
|
2021-09-15 17:44:42 +00:00
|
|
|
movw(Operand(rsp, 16), rdx));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("90 nop", nop());
|
|
|
|
|
COMPARE("480fbf54240c REX.W movsxwq rdx,[rsp+0xc]",
|
2021-09-15 17:44:42 +00:00
|
|
|
movsxwq(rdx, Operand(rsp, 12)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("480fbe54240c REX.W movsxbq rdx,[rsp+0xc]",
|
2021-09-15 17:44:42 +00:00
|
|
|
movsxbq(rdx, Operand(rsp, 12)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("486354240c REX.W movsxlq rdx,[rsp+0xc]",
|
2021-09-15 17:44:42 +00:00
|
|
|
movsxlq(rdx, Operand(rsp, 12)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("0fb754240c movzxwl rdx,[rsp+0xc]",
|
2021-09-15 17:44:42 +00:00
|
|
|
movzxwq(rdx, Operand(rsp, 12)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("0fb654240c movzxbl rdx,[rsp+0xc]",
|
2021-09-15 17:44:42 +00:00
|
|
|
movzxbq(rdx, Operand(rsp, 12)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("90 nop", nop());
|
|
|
|
|
COMPARE("48c7c287d61200 REX.W movq rdx,0x12d687",
|
2021-09-15 17:44:42 +00:00
|
|
|
movq(rdx, Immediate(1234567)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("488b54240c REX.W movq rdx,[rsp+0xc]",
|
2021-09-15 17:44:42 +00:00
|
|
|
movq(rdx, Operand(rsp, 12)));
|
|
|
|
|
COMPARE("48c7848b1027000039300000 REX.W movq [rbx+rcx*4+0x2710],0x3039",
|
|
|
|
|
movq(Operand(rbx, rcx, times_4, 10000), Immediate(12345)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("4889948b10270000 REX.W movq [rbx+rcx*4+0x2710],rdx",
|
2021-09-15 17:44:42 +00:00
|
|
|
movq(Operand(rbx, rcx, times_4, 10000), rdx));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("90 nop", nop());
|
|
|
|
|
COMPARE("feca decb dl", decb(rdx));
|
|
|
|
|
COMPARE("fe480a decb [rax+0xa]", decb(Operand(rax, 10)));
|
|
|
|
|
COMPARE("fe8c8b10270000 decb [rbx+rcx*4+0x2710]",
|
2021-09-15 17:44:42 +00:00
|
|
|
decb(Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("48ffca REX.W decq rdx", decq(rdx));
|
|
|
|
|
COMPARE("99 cdql", cdq());
|
|
|
|
|
|
|
|
|
|
COMPARE("f3ab rep stosl", repstosl());
|
|
|
|
|
COMPARE("f348ab REX.W rep stosq", repstosq());
|
|
|
|
|
|
|
|
|
|
COMPARE("48f7fa REX.W idivq rdx", idivq(rdx));
|
|
|
|
|
COMPARE("f7e2 mull rdx", mull(rdx));
|
|
|
|
|
COMPARE("48f7e2 REX.W mulq rdx", mulq(rdx));
|
|
|
|
|
|
|
|
|
|
COMPARE("f6da negb rdx", negb(rdx));
|
|
|
|
|
COMPARE("41f6da negb r10", negb(r10));
|
|
|
|
|
COMPARE("66f7da negw rdx", negw(rdx));
|
|
|
|
|
COMPARE("f7da negl rdx", negl(rdx));
|
|
|
|
|
COMPARE("48f7da REX.W negq rdx", negq(rdx));
|
|
|
|
|
COMPARE("f65c240c negb [rsp+0xc]", negb(Operand(rsp, 12)));
|
|
|
|
|
COMPARE("66f75c240c negw [rsp+0xc]", negw(Operand(rsp, 12)));
|
|
|
|
|
COMPARE("f75c240c negl [rsp+0xc]", negl(Operand(rsp, 12)));
|
|
|
|
|
COMPARE("f65c240c negb [rsp+0xc]", negb(Operand(rsp, 12)));
|
|
|
|
|
|
|
|
|
|
COMPARE("48f7d2 REX.W notq rdx", notq(rdx));
|
|
|
|
|
COMPARE("4885948b10270000 REX.W testq rdx,[rbx+rcx*4+0x2710]",
|
2021-09-15 17:44:42 +00:00
|
|
|
testq(Operand(rbx, rcx, times_4, 10000), rdx));
|
|
|
|
|
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("486bd10c REX.W imulq rdx,rcx,0xc",
|
2021-09-15 17:44:42 +00:00
|
|
|
imulq(rdx, rcx, Immediate(12)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("4869d1e8030000 REX.W imulq rdx,rcx,0x3e8",
|
2021-09-15 17:44:42 +00:00
|
|
|
imulq(rdx, rcx, Immediate(1000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("480faf948b10270000 REX.W imulq rdx,[rbx+rcx*4+0x2710]",
|
2021-09-15 17:44:42 +00:00
|
|
|
imulq(rdx, Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("486b948b102700000c REX.W imulq rdx,[rbx+rcx*4+0x2710],0xc",
|
2021-09-15 17:44:42 +00:00
|
|
|
imulq(rdx, Operand(rbx, rcx, times_4, 10000), Immediate(12)));
|
|
|
|
|
COMPARE("4869948b10270000e8030000 REX.W imulq rdx,[rbx+rcx*4+0x2710],0x3e8",
|
|
|
|
|
imulq(rdx, Operand(rbx, rcx, times_4, 10000), Immediate(1000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("446bf90c imull r15,rcx,0xc",
|
2021-09-15 17:44:42 +00:00
|
|
|
imull(r15, rcx, Immediate(12)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("4469f9e8030000 imull r15,rcx,0x3e8",
|
2021-09-15 17:44:42 +00:00
|
|
|
imull(r15, rcx, Immediate(1000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("440fafbc8b10270000 imull r15,[rbx+rcx*4+0x2710]",
|
2021-09-15 17:44:42 +00:00
|
|
|
imull(r15, Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("446bbc8b102700000c imull r15,[rbx+rcx*4+0x2710],0xc",
|
2021-09-15 17:44:42 +00:00
|
|
|
imull(r15, Operand(rbx, rcx, times_4, 10000), Immediate(12)));
|
|
|
|
|
COMPARE("4469bc8b10270000e8030000 imull r15,[rbx+rcx*4+0x2710],0x3e8",
|
|
|
|
|
imull(r15, Operand(rbx, rcx, times_4, 10000), Immediate(1000)));
|
|
|
|
|
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("48ffc2 REX.W incq rdx", incq(rdx));
|
|
|
|
|
COMPARE("48ff848b10270000 REX.W incq [rbx+rcx*4+0x2710]",
|
2021-09-15 17:44:42 +00:00
|
|
|
incq(Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("ffb48b10270000 push [rbx+rcx*4+0x2710]",
|
2021-09-15 17:44:42 +00:00
|
|
|
pushq(Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("8f848b10270000 pop [rbx+rcx*4+0x2710]",
|
2021-09-15 17:44:42 +00:00
|
|
|
popq(Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("ffa48b10270000 jmp [rbx+rcx*4+0x2710]",
|
2021-09-15 17:44:42 +00:00
|
|
|
jmp(Operand(rbx, rcx, times_4, 10000)));
|
|
|
|
|
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("488d948b10270000 REX.W leaq rdx,[rbx+rcx*4+0x2710]",
|
2021-09-15 17:44:42 +00:00
|
|
|
leaq(rdx, Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("4881ca39300000 REX.W orq rdx,0x3039",
|
2021-09-15 17:44:42 +00:00
|
|
|
orq(rdx, Immediate(12345)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("480b948b10270000 REX.W orq rdx,[rbx+rcx*4+0x2710]",
|
2021-09-15 17:44:42 +00:00
|
|
|
orq(rdx, Operand(rbx, rcx, times_4, 10000)));
|
|
|
|
|
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("48d1d2 REX.W rclq rdx, 1", rclq(rdx, Immediate(1)));
|
|
|
|
|
COMPARE("48c1d207 REX.W rclq rdx, 7", rclq(rdx, Immediate(7)));
|
|
|
|
|
COMPARE("48d1da REX.W rcrq rdx, 1", rcrq(rdx, Immediate(1)));
|
|
|
|
|
COMPARE("48c1da07 REX.W rcrq rdx, 7", rcrq(rdx, Immediate(7)));
|
|
|
|
|
COMPARE("48d1fa REX.W sarq rdx, 1", sarq(rdx, Immediate(1)));
|
|
|
|
|
COMPARE("48c1fa06 REX.W sarq rdx, 6", sarq(rdx, Immediate(6)));
|
|
|
|
|
COMPARE("48d3fa REX.W sarq rdx, cl", sarq_cl(rdx));
|
|
|
|
|
COMPARE("481bd3 REX.W sbbq rdx,rbx", sbbq(rdx, rbx));
|
|
|
|
|
COMPARE("480fa5da REX.W shld rdx,rbx,cl", shld(rdx, rbx));
|
|
|
|
|
COMPARE("48d1e2 REX.W shlq rdx, 1", shlq(rdx, Immediate(1)));
|
|
|
|
|
COMPARE("48c1e206 REX.W shlq rdx, 6", shlq(rdx, Immediate(6)));
|
|
|
|
|
COMPARE("48d3e2 REX.W shlq rdx, cl", shlq_cl(rdx));
|
|
|
|
|
COMPARE("480fadda REX.W shrd rdx,rbx,cl", shrd(rdx, rbx));
|
|
|
|
|
COMPARE("48d1ea REX.W shrq rdx, 1", shrq(rdx, Immediate(1)));
|
|
|
|
|
COMPARE("48c1ea07 REX.W shrq rdx, 7", shrq(rdx, Immediate(7)));
|
|
|
|
|
COMPARE("48d3ea REX.W shrq rdx, cl", shrq_cl(rdx));
|
|
|
|
|
|
|
|
|
|
COMPARE("4883c30c REX.W addq rbx,0xc", addq(rbx, Immediate(12)));
|
|
|
|
|
COMPARE("4883848a102700000c REX.W addq [rdx+rcx*4+0x2710],0xc",
|
2021-09-15 17:44:42 +00:00
|
|
|
addq(Operand(rdx, rcx, times_4, 10000), Immediate(12)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("4881e339300000 REX.W andq rbx,0x3039",
|
2021-09-15 17:44:42 +00:00
|
|
|
andq(rbx, Immediate(12345)));
|
|
|
|
|
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("4881fb39300000 REX.W cmpq rbx,0x3039",
|
2021-09-15 17:44:42 +00:00
|
|
|
cmpq(rbx, Immediate(12345)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("4883fb0c REX.W cmpq rbx,0xc", cmpq(rbx, Immediate(12)));
|
|
|
|
|
COMPARE("4883bc8a102700000c REX.W cmpq [rdx+rcx*4+0x2710],0xc",
|
2021-09-15 17:44:42 +00:00
|
|
|
cmpq(Operand(rdx, rcx, times_4, 10000), Immediate(12)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("80f864 cmpb al,0x64", cmpb(rax, Immediate(100)));
|
2021-09-15 17:44:42 +00:00
|
|
|
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("4881cb39300000 REX.W orq rbx,0x3039",
|
2021-09-15 17:44:42 +00:00
|
|
|
orq(rbx, Immediate(12345)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("4883eb0c REX.W subq rbx,0xc", subq(rbx, Immediate(12)));
|
|
|
|
|
COMPARE("4883ac8a102700000c REX.W subq [rdx+rcx*4+0x2710],0xc",
|
2021-09-15 17:44:42 +00:00
|
|
|
subq(Operand(rdx, rcx, times_4, 10000), Immediate(12)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("4881f339300000 REX.W xorq rbx,0x3039",
|
2021-09-15 17:44:42 +00:00
|
|
|
xorq(rbx, Immediate(12345)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("486bd10c REX.W imulq rdx,rcx,0xc",
|
2021-09-15 17:44:42 +00:00
|
|
|
imulq(rdx, rcx, Immediate(12)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("4869d1e8030000 REX.W imulq rdx,rcx,0x3e8",
|
2021-09-15 17:44:42 +00:00
|
|
|
imulq(rdx, rcx, Immediate(1000)));
|
|
|
|
|
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("fc cldl", cld());
|
2021-09-15 17:44:42 +00:00
|
|
|
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("482b948b10270000 REX.W subq rdx,[rbx+rcx*4+0x2710]",
|
2021-09-15 17:44:42 +00:00
|
|
|
subq(rdx, Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("482bd3 REX.W subq rdx,rbx", subq(rdx, rbx));
|
2021-09-15 17:44:42 +00:00
|
|
|
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("66f7c23930 testw rdx,0x3039",
|
|
|
|
|
testq(rdx, Immediate(12345)));
|
|
|
|
|
COMPARE("488594cb10270000 REX.W testq rdx,[rbx+rcx*8+0x2710]",
|
2021-09-15 17:44:42 +00:00
|
|
|
testq(Operand(rbx, rcx, times_8, 10000), rdx));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("849459e8030000 testb dl,[rcx+rbx*2+0x3e8]",
|
2021-09-15 17:44:42 +00:00
|
|
|
testb(Operand(rcx, rbx, times_2, 1000), rdx));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("f640ec9a testb [rax-0x14],0x9a",
|
2021-09-15 17:44:42 +00:00
|
|
|
testb(Operand(rax, -20), Immediate(0x9A)));
|
|
|
|
|
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("4881f239300000 REX.W xorq rdx,0x3039",
|
2021-09-15 17:44:42 +00:00
|
|
|
xorq(rdx, Immediate(12345)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("483394cb10270000 REX.W xorq rdx,[rbx+rcx*8+0x2710]",
|
2021-09-15 17:44:42 +00:00
|
|
|
xorq(rdx, Operand(rbx, rcx, times_8, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("f4 hltl", hlt());
|
|
|
|
|
COMPARE("cc int3l", int3());
|
|
|
|
|
COMPARE("c3 retl", ret(0));
|
|
|
|
|
COMPARE("c20800 ret 0x8", ret(8));
|
2021-09-20 22:45:03 +00:00
|
|
|
|
|
|
|
|
// 0xD9 instructions
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("d9c1 fld st1", fld(1));
|
|
|
|
|
COMPARE("d9e8 fld1", fld1());
|
|
|
|
|
COMPARE("d9ee fldz", fldz());
|
|
|
|
|
COMPARE("d9eb fldpi", fldpi());
|
|
|
|
|
COMPARE("d9e1 fabs", fabs());
|
|
|
|
|
COMPARE("d9e0 fchs", fchs());
|
|
|
|
|
COMPARE("d9f8 fprem", fprem());
|
|
|
|
|
COMPARE("d9f5 fprem1", fprem1());
|
|
|
|
|
COMPARE("d9f7 fincstp", fincstp());
|
|
|
|
|
COMPARE("d9e4 ftst", ftst());
|
|
|
|
|
COMPARE("d9cb fxch st3", fxch(3));
|
|
|
|
|
COMPARE("d9848b10270000 fld_s [rbx+rcx*4+0x2710]",
|
2021-09-20 22:45:03 +00:00
|
|
|
fld_s(Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("d99c8b10270000 fstp_s [rbx+rcx*4+0x2710]",
|
2021-09-20 22:45:03 +00:00
|
|
|
fstp_s(Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("ddc3 ffree st3", ffree(3));
|
|
|
|
|
COMPARE("dd848b10270000 fld_d [rbx+rcx*4+0x2710]",
|
2021-09-20 22:45:03 +00:00
|
|
|
fld_d(Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("dd9c8b10270000 fstp_d [rbx+rcx*4+0x2710]",
|
2021-09-20 22:45:03 +00:00
|
|
|
fstp_d(Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("db848b10270000 fild_s [rbx+rcx*4+0x2710]",
|
2021-09-20 22:45:03 +00:00
|
|
|
fild_s(Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("db9c8b10270000 fistp_s [rbx+rcx*4+0x2710]",
|
2021-09-20 22:45:03 +00:00
|
|
|
fistp_s(Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("dfac8b10270000 fild_d [rbx+rcx*4+0x2710]",
|
2021-09-20 22:45:03 +00:00
|
|
|
fild_d(Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("dfbc8b10270000 fistp_d [rbx+rcx*4+0x2710]",
|
2021-09-20 22:45:03 +00:00
|
|
|
fistp_d(Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("dfe0 fnstsw_ax", fnstsw_ax());
|
|
|
|
|
COMPARE("dcc3 fadd st3", fadd(3));
|
|
|
|
|
COMPARE("dceb fsub st3", fsub(3));
|
|
|
|
|
COMPARE("dccb fmul st3", fmul(3));
|
|
|
|
|
COMPARE("dcfb fdiv st3", fdiv(3));
|
|
|
|
|
COMPARE("dec3 faddp st3", faddp(3));
|
|
|
|
|
COMPARE("deeb fsubp st3", fsubp(3));
|
|
|
|
|
COMPARE("decb fmulp st3", fmulp(3));
|
|
|
|
|
COMPARE("defb fdivp st3", fdivp(3));
|
|
|
|
|
COMPARE("ded9 fcompp", fcompp());
|
|
|
|
|
COMPARE("9b fwaitl", fwait());
|
|
|
|
|
COMPARE("d9fc frndint", frndint());
|
|
|
|
|
COMPARE("dbe3 fninit", fninit());
|
|
|
|
|
|
|
|
|
|
COMPARE("480f4000 REX.W cmovoq rax,[rax]",
|
2021-09-24 16:29:32 +00:00
|
|
|
cmovq(overflow, rax, Operand(rax, 0)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("480f414001 REX.W cmovnoq rax,[rax+0x1]",
|
2021-09-24 16:29:32 +00:00
|
|
|
cmovq(no_overflow, rax, Operand(rax, 1)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("480f424002 REX.W cmovcq rax,[rax+0x2]",
|
2021-09-24 16:29:32 +00:00
|
|
|
cmovq(below, rax, Operand(rax, 2)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("480f434003 REX.W cmovncq rax,[rax+0x3]",
|
2021-09-24 16:29:32 +00:00
|
|
|
cmovq(above_equal, rax, Operand(rax, 3)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("480f4403 REX.W cmovzq rax,[rbx]",
|
2021-09-24 16:29:32 +00:00
|
|
|
cmovq(equal, rax, Operand(rbx, 0)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("480f454301 REX.W cmovnzq rax,[rbx+0x1]",
|
2021-09-24 16:29:32 +00:00
|
|
|
cmovq(not_equal, rax, Operand(rbx, 1)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("480f464302 REX.W cmovnaq rax,[rbx+0x2]",
|
2021-09-24 16:29:32 +00:00
|
|
|
cmovq(below_equal, rax, Operand(rbx, 2)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("480f474303 REX.W cmovaq rax,[rbx+0x3]",
|
2021-09-24 16:29:32 +00:00
|
|
|
cmovq(above, rax, Operand(rbx, 3)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("480f4801 REX.W cmovsq rax,[rcx]",
|
2021-09-24 16:29:32 +00:00
|
|
|
cmovq(sign, rax, Operand(rcx, 0)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("480f494101 REX.W cmovnsq rax,[rcx+0x1]",
|
2021-09-24 16:29:32 +00:00
|
|
|
cmovq(not_sign, rax, Operand(rcx, 1)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("480f4a4102 REX.W cmovpeq rax,[rcx+0x2]",
|
2021-09-24 16:29:32 +00:00
|
|
|
cmovq(parity_even, rax, Operand(rcx, 2)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("480f4b4103 REX.W cmovpoq rax,[rcx+0x3]",
|
2021-09-24 16:29:32 +00:00
|
|
|
cmovq(parity_odd, rax, Operand(rcx, 3)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("480f4c02 REX.W cmovlq rax,[rdx]",
|
2021-09-24 16:29:32 +00:00
|
|
|
cmovq(less, rax, Operand(rdx, 0)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("480f4d4201 REX.W cmovgeq rax,[rdx+0x1]",
|
2021-09-24 16:29:32 +00:00
|
|
|
cmovq(greater_equal, rax, Operand(rdx, 1)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("480f4e4202 REX.W cmovleq rax,[rdx+0x2]",
|
2021-09-24 16:29:32 +00:00
|
|
|
cmovq(less_equal, rax, Operand(rdx, 2)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("480f4f4203 REX.W cmovgq rax,[rdx+0x3]",
|
2021-09-24 16:29:32 +00:00
|
|
|
cmovq(greater, rax, Operand(rdx, 3)));
|
2021-09-09 21:03:41 +00:00
|
|
|
}
|
|
|
|
|
|
2021-09-23 16:30:22 +00:00
|
|
|
// This compares just the disassemble instruction (without the hex).
|
|
|
|
|
// Requires a |std::string actual| to be in scope.
|
2021-10-04 21:26:52 +00:00
|
|
|
// Hard coded offset of 21, the hex part is 20 bytes, plus a space. If and when
|
2021-09-23 16:30:22 +00:00
|
|
|
// the padding changes, this should be adjusted.
|
2021-10-04 21:26:52 +00:00
|
|
|
constexpr int kHexOffset = 21;
|
2021-09-23 16:30:22 +00:00
|
|
|
#define COMPARE_INSTR(str, ASM) \
|
|
|
|
|
t.prev_offset = t.pc_offset(); \
|
|
|
|
|
t.assm_.ASM; \
|
|
|
|
|
actual = t.InstructionDecode(); \
|
|
|
|
|
actual = std::string(actual, kHexOffset, actual.size() - kHexOffset); \
|
|
|
|
|
CHECK_EQ(str, actual);
|
|
|
|
|
|
|
|
|
|
UNINITIALIZED_TEST(DisasmX64CheckOutputSSE) {
|
|
|
|
|
DisassemblerTester t;
|
|
|
|
|
std::string actual;
|
|
|
|
|
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("f30f2c948b10270000 cvttss2sil rdx,[rbx+rcx*4+0x2710]",
|
2021-09-23 16:30:22 +00:00
|
|
|
cvttss2si(rdx, Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("f30f2cd1 cvttss2sil rdx,xmm1", cvttss2si(rdx, xmm1));
|
2021-09-23 16:30:22 +00:00
|
|
|
COMPARE("f3480f2a8c8b10270000 REX.W cvtsi2ss xmm1,[rbx+rcx*4+0x2710]",
|
|
|
|
|
cvtqsi2ss(xmm1, Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("f3480f2aca REX.W cvtsi2ss xmm1,rdx", cvtqsi2ss(xmm1, rdx));
|
|
|
|
|
COMPARE("f3480f5bc1 REX.W cvttps2dq xmm0,xmm1",
|
2021-09-23 16:30:22 +00:00
|
|
|
cvttps2dq(xmm0, xmm1));
|
|
|
|
|
COMPARE("f3480f5b848b10270000 REX.W cvttps2dq xmm0,[rbx+rcx*4+0x2710]",
|
|
|
|
|
cvttps2dq(xmm0, Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("0f28c1 movaps xmm0,xmm1", movaps(xmm0, xmm1));
|
|
|
|
|
COMPARE("0f28848b10270000 movaps xmm0,[rbx+rcx*4+0x2710]",
|
2021-09-23 16:30:22 +00:00
|
|
|
movaps(xmm0, Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("66480f6f44240c REX.W movdqa xmm0,[rsp+0xc]",
|
2021-09-23 16:30:22 +00:00
|
|
|
movdqa(xmm0, Operand(rsp, 12)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("66480f7f44240c REX.W movdqa [rsp+0xc],xmm0",
|
2021-09-23 16:30:22 +00:00
|
|
|
movdqa(Operand(rsp, 12), xmm0));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("f3480f6f44240c REX.W movdqu xmm0,[rsp+0xc]",
|
2021-09-23 16:30:22 +00:00
|
|
|
movdqu(xmm0, Operand(rsp, 12)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("f3480f7f44240c REX.W movdqu [rsp+0xc],xmm0",
|
2021-09-23 16:30:22 +00:00
|
|
|
movdqu(Operand(rsp, 12), xmm0));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("f3480f6fc8 REX.W movdqu xmm1,xmm0", movdqu(xmm1, xmm0));
|
|
|
|
|
COMPARE("0f12e9 movhlps xmm5,xmm1", movhlps(xmm5, xmm1));
|
|
|
|
|
COMPARE("440f12848b10270000 movlps xmm8,[rbx+rcx*4+0x2710]",
|
2021-09-23 16:30:22 +00:00
|
|
|
movlps(xmm8, Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("440f138c8b10270000 movlps [rbx+rcx*4+0x2710],xmm9",
|
2021-09-23 16:30:22 +00:00
|
|
|
movlps(Operand(rbx, rcx, times_4, 10000), xmm9));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("0f16e9 movlhps xmm5,xmm1", movlhps(xmm5, xmm1));
|
|
|
|
|
COMPARE("440f16848b10270000 movhps xmm8,[rbx+rcx*4+0x2710]",
|
2021-09-23 16:30:22 +00:00
|
|
|
movhps(xmm8, Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("440f178c8b10270000 movhps [rbx+rcx*4+0x2710],xmm9",
|
2021-09-23 16:30:22 +00:00
|
|
|
movhps(Operand(rbx, rcx, times_4, 10000), xmm9));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("410fc6c100 shufps xmm0, xmm9, 0", shufps(xmm0, xmm9, 0x0));
|
|
|
|
|
COMPARE("0f2ec1 ucomiss xmm0,xmm1", ucomiss(xmm0, xmm1));
|
|
|
|
|
COMPARE("0f2e848b10270000 ucomiss xmm0,[rbx+rcx*4+0x2710]",
|
2021-09-23 16:30:22 +00:00
|
|
|
ucomiss(xmm0, Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("410f50d1 movmskps rdx,xmm9", movmskps(rdx, xmm9));
|
2021-09-23 16:30:22 +00:00
|
|
|
|
|
|
|
|
std::string exp;
|
|
|
|
|
|
|
|
|
|
#define COMPARE_SSE_INSTR(instruction, _, __) \
|
|
|
|
|
exp = #instruction " xmm1,xmm0"; \
|
|
|
|
|
COMPARE_INSTR(exp, instruction(xmm1, xmm0)); \
|
|
|
|
|
exp = #instruction " xmm1,[rbx+rcx*4+0x2710]"; \
|
|
|
|
|
COMPARE_INSTR(exp, instruction(xmm1, Operand(rbx, rcx, times_4, 10000)));
|
|
|
|
|
SSE_BINOP_INSTRUCTION_LIST(COMPARE_SSE_INSTR)
|
|
|
|
|
SSE_UNOP_INSTRUCTION_LIST(COMPARE_SSE_INSTR)
|
|
|
|
|
#undef COMPARE_SSE_INSTR
|
|
|
|
|
|
|
|
|
|
#define COMPARE_SSE_INSTR(instruction, _, __, ___) \
|
|
|
|
|
exp = #instruction " xmm1,xmm0"; \
|
|
|
|
|
COMPARE_INSTR(exp, instruction(xmm1, xmm0)); \
|
|
|
|
|
exp = #instruction " xmm1,[rbx+rcx*4+0x2710]"; \
|
|
|
|
|
COMPARE_INSTR(exp, instruction(xmm1, Operand(rbx, rcx, times_4, 10000)));
|
|
|
|
|
SSE_INSTRUCTION_LIST_SS(COMPARE_SSE_INSTR)
|
|
|
|
|
#undef COMPARE_SSE_INSTR
|
|
|
|
|
}
|
|
|
|
|
|
2021-09-23 22:30:45 +00:00
|
|
|
UNINITIALIZED_TEST(DisasmX64CheckOutputSSE2) {
|
|
|
|
|
DisassemblerTester t;
|
|
|
|
|
std::string actual, exp;
|
|
|
|
|
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("f30fe6dc cvtdq2pd xmm3,xmm4", cvtdq2pd(xmm3, xmm4));
|
|
|
|
|
COMPARE("f20f2c948b10270000 cvttsd2sil rdx,[rbx+rcx*4+0x2710]",
|
2021-09-23 22:30:45 +00:00
|
|
|
cvttsd2si(rdx, Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("f20f2cd1 cvttsd2sil rdx,xmm1", cvttsd2si(rdx, xmm1));
|
|
|
|
|
COMPARE("f2480f2cd1 REX.W cvttsd2siq rdx,xmm1",
|
2021-09-23 22:30:45 +00:00
|
|
|
cvttsd2siq(rdx, xmm1));
|
|
|
|
|
COMPARE("f2480f2c948b10270000 REX.W cvttsd2siq rdx,[rbx+rcx*4+0x2710]",
|
|
|
|
|
cvttsd2siq(rdx, Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("f20f2a8c8b10270000 cvtsi2sd xmm1,[rbx+rcx*4+0x2710]",
|
2021-09-23 22:30:45 +00:00
|
|
|
cvtlsi2sd(xmm1, Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("f20f2aca cvtsi2sd xmm1,rdx", cvtlsi2sd(xmm1, rdx));
|
2021-09-23 22:30:45 +00:00
|
|
|
COMPARE("f2480f2a8c8b10270000 REX.W cvtsi2sd xmm1,[rbx+rcx*4+0x2710]",
|
|
|
|
|
cvtqsi2sd(xmm1, Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("f2480f2aca REX.W cvtsi2sd xmm1,rdx", cvtqsi2sd(xmm1, rdx));
|
|
|
|
|
COMPARE("f3410f5ac9 cvtss2sd xmm1,xmm9", cvtss2sd(xmm1, xmm9));
|
|
|
|
|
COMPARE("f30f5a8c8b10270000 cvtss2sd xmm1,[rbx+rcx*4+0x2710]",
|
2021-09-23 22:30:45 +00:00
|
|
|
cvtss2sd(xmm1, Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("f2410f2dd1 cvtsd2sil rdx,xmm9", cvtsd2si(rdx, xmm9));
|
|
|
|
|
COMPARE("f2490f2dd1 REX.W cvtsd2siq rdx,xmm9",
|
|
|
|
|
cvtsd2siq(rdx, xmm9););
|
2021-09-23 22:30:45 +00:00
|
|
|
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("f20f108c8b10270000 movsd xmm1,[rbx+rcx*4+0x2710]",
|
2021-09-23 22:30:45 +00:00
|
|
|
movsd(xmm1, Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("f20f118c8b10270000 movsd [rbx+rcx*4+0x2710],xmm1",
|
2021-09-23 22:30:45 +00:00
|
|
|
movsd(Operand(rbx, rcx, times_4, 10000), xmm1));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("660f10848b10270000 movupd xmm0,[rbx+rcx*4+0x2710]",
|
2021-09-23 22:30:45 +00:00
|
|
|
movupd(xmm0, Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("660f11848b10270000 movupd [rbx+rcx*4+0x2710],xmm0",
|
2021-09-23 22:30:45 +00:00
|
|
|
movupd(Operand(rbx, rcx, times_4, 10000), xmm0));
|
|
|
|
|
COMPARE("66480f6f848b10270000 REX.W movdqa xmm0,[rbx+rcx*4+0x2710]",
|
|
|
|
|
movdqa(xmm0, Operand(rbx, rcx, times_4, 10000)));
|
|
|
|
|
COMPARE("66480f7f848b10270000 REX.W movdqa [rbx+rcx*4+0x2710],xmm0",
|
|
|
|
|
movdqa(Operand(rbx, rcx, times_4, 10000), xmm0));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("66480f7fc8 REX.W movdqa xmm0,xmm1", movdqa(xmm0, xmm1));
|
|
|
|
|
COMPARE("660f2ec1 ucomisd xmm0,xmm1", ucomisd(xmm0, xmm1));
|
2021-09-23 22:30:45 +00:00
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COMPARE("66440f2e849310270000 ucomisd xmm8,[rbx+rdx*4+0x2710]",
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ucomisd(xmm8, Operand(rbx, rdx, times_4, 10000)));
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2021-10-04 21:26:52 +00:00
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COMPARE("f2410fc2db01 cmpltsd xmm3,xmm11", cmpltsd(xmm3, xmm11));
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COMPARE("66410f50d1 movmskpd rdx,xmm9", movmskpd(rdx, xmm9));
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COMPARE("66410fd7d1 pmovmskb r9,xmm2", pmovmskb(rdx, xmm9));
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COMPARE("660f76c8 pcmpeqd xmm1,xmm0", pcmpeqd(xmm1, xmm0));
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COMPARE("66410f62cb punpckldq xmm1,xmm11", punpckldq(xmm1, xmm11));
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COMPARE("660f626a04 punpckldq xmm5,[rdx+0x4]",
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2021-09-23 22:30:45 +00:00
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punpckldq(xmm5, Operand(rdx, 4)));
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2021-10-04 21:26:52 +00:00
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COMPARE("66450f6ac7 punpckhdq xmm8,xmm15", punpckhdq(xmm8, xmm15));
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COMPARE("f20f70d403 pshuflw xmm2,xmm4,3", pshuflw(xmm2, xmm4, 3));
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COMPARE("f3410f70c906 pshufhw xmm1,xmm9, 6", pshufhw(xmm1, xmm9, 6));
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2021-09-23 22:30:45 +00:00
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#define COMPARE_SSE2_INSTR(instruction, _, __, ___) \
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exp = #instruction " xmm1,xmm0"; \
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COMPARE_INSTR(exp, instruction(xmm1, xmm0)); \
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exp = #instruction " xmm1,[rbx+rcx*4+0x2710]"; \
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COMPARE_INSTR(exp, instruction(xmm1, Operand(rbx, rcx, times_4, 10000)));
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SSE2_INSTRUCTION_LIST(COMPARE_SSE2_INSTR)
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SSE2_UNOP_INSTRUCTION_LIST(COMPARE_SSE2_INSTR)
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SSE2_INSTRUCTION_LIST_SD(COMPARE_SSE2_INSTR)
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|
#undef COMPARE_SSE2_INSTR
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#define COMPARE_SSE2_SHIFT_IMM(instruction, _, __, ___, ____) \
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exp = #instruction " xmm3,35"; \
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|
COMPARE_INSTR(exp, instruction(xmm3, 0xA3));
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|
SSE2_INSTRUCTION_LIST_SHIFT_IMM(COMPARE_SSE2_SHIFT_IMM)
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|
|
#undef COMPARE_SSE2_SHIFT_IMM
|
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|
|
|
}
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|
|
2021-09-24 16:29:54 +00:00
|
|
|
UNINITIALIZED_TEST(DisasmX64CheckOutputSSE3) {
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|
|
|
|
if (!CpuFeatures::IsSupported(SSE3)) {
|
|
|
|
|
return;
|
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|
|
}
|
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|
DisassemblerTester t;
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|
CpuFeatureScope scope(&t.assm_, SSE3);
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|
2021-10-04 21:26:52 +00:00
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|
COMPARE("f20f7cc8 haddps xmm1,xmm0", haddps(xmm1, xmm0));
|
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|
|
|
COMPARE("f20f7c8c8b10270000 haddps xmm1,[rbx+rcx*4+0x2710]",
|
2021-09-24 16:29:54 +00:00
|
|
|
haddps(xmm1, Operand(rbx, rcx, times_4, 10000)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("f20ff04a04 lddqu xmm1,[rdx+0x4]",
|
2021-09-24 16:29:54 +00:00
|
|
|
lddqu(xmm1, Operand(rdx, 4)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("f20f124805 movddup xmm1,[rax+0x5]",
|
2021-09-24 16:29:54 +00:00
|
|
|
movddup(xmm1, Operand(rax, 5)));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("f20f12ca movddup xmm1,xmm2", movddup(xmm1, xmm2));
|
|
|
|
|
COMPARE("f30f16ca movshdup xmm1,xmm2", movshdup(xmm1, xmm2));
|
2021-09-24 16:29:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
UNINITIALIZED_TEST(DisasmX64CheckOutputSSSE3) {
|
|
|
|
|
if (!CpuFeatures::IsSupported(SSSE3)) {
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
DisassemblerTester t;
|
|
|
|
|
std::string actual, exp;
|
|
|
|
|
CpuFeatureScope scope(&t.assm_, SSSE3);
|
|
|
|
|
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("660f3a0fe905 palignr xmm5,xmm1,0x5", palignr(xmm5, xmm1, 5));
|
|
|
|
|
COMPARE("660f3a0f6a0405 palignr xmm5,[rdx+0x4],0x5",
|
2021-09-24 16:29:54 +00:00
|
|
|
palignr(xmm5, Operand(rdx, 4), 5));
|
|
|
|
|
|
|
|
|
|
#define COMPARE_SSSE3_INSTR(instruction, _, __, ___, ____) \
|
|
|
|
|
exp = #instruction " xmm5,xmm1"; \
|
|
|
|
|
COMPARE_INSTR(exp, instruction(xmm5, xmm1)); \
|
2021-10-04 21:26:52 +00:00
|
|
|
exp = #instruction " xmm5,[rbx+rcx*4+0x2710]"; \
|
|
|
|
|
COMPARE_INSTR(exp, instruction(xmm5, Operand(rbx, rcx, times_4, 10000)));
|
2021-09-24 16:29:54 +00:00
|
|
|
SSSE3_INSTRUCTION_LIST(COMPARE_SSSE3_INSTR)
|
|
|
|
|
SSSE3_UNOP_INSTRUCTION_LIST(COMPARE_SSSE3_INSTR)
|
|
|
|
|
#undef COMPARE_SSSE3_INSTR
|
|
|
|
|
}
|
|
|
|
|
|
2021-09-14 21:01:51 +00:00
|
|
|
UNINITIALIZED_TEST(DisasmX64YMMRegister) {
|
2021-09-07 22:14:40 +00:00
|
|
|
if (!CpuFeatures::IsSupported(AVX)) return;
|
2021-10-01 20:35:37 +00:00
|
|
|
DisassemblerTester t;
|
|
|
|
|
CpuFeatureScope fscope(t.assm(), AVX);
|
2021-09-07 22:14:40 +00:00
|
|
|
|
2021-10-01 20:35:37 +00:00
|
|
|
// Short immediate instructions
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("c5fd6fc1 vmovdqa ymm0,ymm1", vmovdqa(ymm0, ymm1));
|
|
|
|
|
COMPARE("c5f77cc2 vhaddps ymm0,ymm1,ymm2",
|
2021-10-01 20:35:37 +00:00
|
|
|
vhaddps(ymm0, ymm1, ymm2));
|
2021-10-04 21:26:52 +00:00
|
|
|
COMPARE("c5f77c848b10270000 vhaddps ymm0,ymm1,[rbx+rcx*4+0x2710]",
|
2021-10-01 20:35:37 +00:00
|
|
|
vhaddps(ymm0, ymm1, Operand(rbx, rcx, times_4, 10000)));
|
2021-09-07 22:14:40 +00:00
|
|
|
}
|
|
|
|
|
|
2011-12-05 08:58:01 +00:00
|
|
|
#undef __
|
2017-08-11 11:22:28 +00:00
|
|
|
|
|
|
|
|
} // namespace internal
|
|
|
|
|
} // namespace v8
|
